O3CPU.py revision 13563
111986Sandreas.sandberg@arm.com# Copyright (c) 2016, 2019 ARM Limited 211986Sandreas.sandberg@arm.com# All rights reserved. 311986Sandreas.sandberg@arm.com# 411986Sandreas.sandberg@arm.com# The license below extends only to copyright in the software and shall 511986Sandreas.sandberg@arm.com# not be construed as granting a license to any other intellectual 611986Sandreas.sandberg@arm.com# property including but not limited to intellectual property relating 711986Sandreas.sandberg@arm.com# to a hardware implementation of the functionality of the software 811986Sandreas.sandberg@arm.com# licensed hereunder. You may use the software subject to the license 911986Sandreas.sandberg@arm.com# terms below provided that you ensure that this notice is replicated 1011986Sandreas.sandberg@arm.com# unmodified and in its entirety in all distributions of the software, 1111986Sandreas.sandberg@arm.com# modified or unmodified, in source code or in binary form. 1211986Sandreas.sandberg@arm.com# 1312037Sandreas.sandberg@arm.com# Copyright (c) 2005-2007 The Regents of The University of Michigan 1411986Sandreas.sandberg@arm.com# All rights reserved. 1511986Sandreas.sandberg@arm.com# 1611986Sandreas.sandberg@arm.com# Redistribution and use in source and binary forms, with or without 1711986Sandreas.sandberg@arm.com# modification, are permitted provided that the following conditions are 1812037Sandreas.sandberg@arm.com# met: redistributions of source code must retain the above copyright 1912037Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer; 2012037Sandreas.sandberg@arm.com# redistributions in binary form must reproduce the above copyright 2112037Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer in the 2212037Sandreas.sandberg@arm.com# documentation and/or other materials provided with the distribution; 2311986Sandreas.sandberg@arm.com# neither the name of the copyright holders nor the names of its 2411986Sandreas.sandberg@arm.com# contributors may be used to endorse or promote products derived from 2511986Sandreas.sandberg@arm.com# this software without specific prior written permission. 2611986Sandreas.sandberg@arm.com# 2711986Sandreas.sandberg@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2811986Sandreas.sandberg@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2911986Sandreas.sandberg@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3011986Sandreas.sandberg@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3111986Sandreas.sandberg@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3211986Sandreas.sandberg@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3311986Sandreas.sandberg@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3411986Sandreas.sandberg@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3511986Sandreas.sandberg@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3611986Sandreas.sandberg@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3711986Sandreas.sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3811986Sandreas.sandberg@arm.com# 3911986Sandreas.sandberg@arm.com# Authors: Kevin Lim 4011986Sandreas.sandberg@arm.com 4111986Sandreas.sandberg@arm.comfrom __future__ import print_function 4211986Sandreas.sandberg@arm.com 4311986Sandreas.sandberg@arm.comfrom m5.defines import buildEnv 4411986Sandreas.sandberg@arm.comfrom m5.params import * 4511986Sandreas.sandberg@arm.comfrom m5.proxy import * 4611986Sandreas.sandberg@arm.comfrom BaseCPU import BaseCPU 4711986Sandreas.sandberg@arm.comfrom FUPool import * 4811986Sandreas.sandberg@arm.comfrom O3Checker import O3Checker 4911986Sandreas.sandberg@arm.comfrom BranchPredictor import * 5011986Sandreas.sandberg@arm.com 5111986Sandreas.sandberg@arm.comclass FetchPolicy(ScopedEnum): 5211986Sandreas.sandberg@arm.com vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ] 5311986Sandreas.sandberg@arm.com 5411986Sandreas.sandberg@arm.comclass SMTQueuePolicy(ScopedEnum): 5511986Sandreas.sandberg@arm.com vals = [ 'Dynamic', 'Partitioned', 'Threshold' ] 5611986Sandreas.sandberg@arm.com 5711986Sandreas.sandberg@arm.comclass CommitPolicy(ScopedEnum): 5811986Sandreas.sandberg@arm.com vals = [ 'Aggressive', 'RoundRobin', 'OldestReady' ] 5911986Sandreas.sandberg@arm.com 6011986Sandreas.sandberg@arm.comclass DerivO3CPU(BaseCPU): 6111986Sandreas.sandberg@arm.com type = 'DerivO3CPU' 6212037Sandreas.sandberg@arm.com cxx_header = 'cpu/o3/deriv.hh' 6312037Sandreas.sandberg@arm.com 6412037Sandreas.sandberg@arm.com @classmethod 6512037Sandreas.sandberg@arm.com def memory_mode(cls): 6612037Sandreas.sandberg@arm.com return 'timing' 6712037Sandreas.sandberg@arm.com 6812037Sandreas.sandberg@arm.com @classmethod 6912037Sandreas.sandberg@arm.com def require_caches(cls): 7012037Sandreas.sandberg@arm.com return True 7112037Sandreas.sandberg@arm.com 7212037Sandreas.sandberg@arm.com @classmethod 7312037Sandreas.sandberg@arm.com def support_take_over(cls): 7412037Sandreas.sandberg@arm.com return True 7512037Sandreas.sandberg@arm.com 7611986Sandreas.sandberg@arm.com activity = Param.Unsigned(0, "Initial count") 7711986Sandreas.sandberg@arm.com 7811986Sandreas.sandberg@arm.com cacheStorePorts = Param.Unsigned(200, "Cache Ports. " 7911986Sandreas.sandberg@arm.com "Constrains stores only. Loads are constrained by load FUs.") 8012037Sandreas.sandberg@arm.com 8112037Sandreas.sandberg@arm.com decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 8211986Sandreas.sandberg@arm.com renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 8311986Sandreas.sandberg@arm.com iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 8411986Sandreas.sandberg@arm.com "delay") 8511986Sandreas.sandberg@arm.com commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 8611986Sandreas.sandberg@arm.com fetchWidth = Param.Unsigned(8, "Fetch width") 8711986Sandreas.sandberg@arm.com fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") 8812037Sandreas.sandberg@arm.com fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops " 8912037Sandreas.sandberg@arm.com "per-thread") 9012037Sandreas.sandberg@arm.com 9112037Sandreas.sandberg@arm.com renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 9212037Sandreas.sandberg@arm.com iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 9312037Sandreas.sandberg@arm.com "delay") 9412037Sandreas.sandberg@arm.com commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 9512037Sandreas.sandberg@arm.com fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 9612037Sandreas.sandberg@arm.com decodeWidth = Param.Unsigned(8, "Decode width") 9712037Sandreas.sandberg@arm.com 9812037Sandreas.sandberg@arm.com iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 9912037Sandreas.sandberg@arm.com "delay") 10012037Sandreas.sandberg@arm.com commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 10111986Sandreas.sandberg@arm.com decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 10211986Sandreas.sandberg@arm.com renameWidth = Param.Unsigned(8, "Rename width") 10311986Sandreas.sandberg@arm.com 10411986Sandreas.sandberg@arm.com commitToIEWDelay = Param.Cycles(1, "Commit to " 10511986Sandreas.sandberg@arm.com "Issue/Execute/Writeback delay") 10611986Sandreas.sandberg@arm.com renameToIEWDelay = Param.Cycles(2, "Rename to " 10711986Sandreas.sandberg@arm.com "Issue/Execute/Writeback delay") 10811986Sandreas.sandberg@arm.com issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 10911986Sandreas.sandberg@arm.com "to the IEW stage)") 11011986Sandreas.sandberg@arm.com dispatchWidth = Param.Unsigned(8, "Dispatch width") 11111986Sandreas.sandberg@arm.com issueWidth = Param.Unsigned(8, "Issue width") 11211986Sandreas.sandberg@arm.com wbWidth = Param.Unsigned(8, "Writeback width") 11311986Sandreas.sandberg@arm.com fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 11411986Sandreas.sandberg@arm.com 11511986Sandreas.sandberg@arm.com iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 11611986Sandreas.sandberg@arm.com "delay") 11711986Sandreas.sandberg@arm.com renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 11811986Sandreas.sandberg@arm.com commitWidth = Param.Unsigned(8, "Commit width") 11911986Sandreas.sandberg@arm.com squashWidth = Param.Unsigned(8, "Squash width") 12011986Sandreas.sandberg@arm.com trapLatency = Param.Cycles(13, "Trap latency") 12111986Sandreas.sandberg@arm.com fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 12211986Sandreas.sandberg@arm.com 12311986Sandreas.sandberg@arm.com backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 12411986Sandreas.sandberg@arm.com forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 12511986Sandreas.sandberg@arm.com 12611986Sandreas.sandberg@arm.com LQEntries = Param.Unsigned(32, "Number of load queue entries") 12711986Sandreas.sandberg@arm.com SQEntries = Param.Unsigned(32, "Number of store queue entries") 12811986Sandreas.sandberg@arm.com LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 129 LSQCheckLoads = Param.Bool(True, 130 "Should dependency violations be checked for loads & stores or just stores") 131 store_set_clear_period = Param.Unsigned(250000, 132 "Number of load/store insts before the dep predictor should be invalidated") 133 LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 134 SSITSize = Param.Unsigned(1024, "Store set ID table size") 135 136 numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 137 138 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 139 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 140 "registers") 141 # most ISAs don't use condition-code regs, so default is 0 142 _defaultNumPhysCCRegs = 0 143 if buildEnv['TARGET_ISA'] in ('arm','x86'): 144 # For x86, each CC reg is used to hold only a subset of the 145 # flags, so we need 4-5 times the number of CC regs as 146 # physical integer regs to be sure we don't run out. In 147 # typical real machines, CC regs are not explicitly renamed 148 # (it's a side effect of int reg renaming), so they should 149 # never be the bottleneck here. 150 _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 151 numPhysVecRegs = Param.Unsigned(256, "Number of physical vector " 152 "registers") 153 numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, 154 "Number of physical cc registers") 155 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 156 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 157 158 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 159 smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy") 160 smtLSQPolicy = Param.SMTQueuePolicy('Partitioned', 161 "SMT LSQ Sharing Policy") 162 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 163 smtIQPolicy = Param.SMTQueuePolicy('Partitioned', 164 "SMT IQ Sharing Policy") 165 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 166 smtROBPolicy = Param.SMTQueuePolicy('Partitioned', 167 "SMT ROB Sharing Policy") 168 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 169 smtCommitPolicy = Param.CommitPolicy('RoundRobin', "SMT Commit Policy") 170 171 branchPred = Param.BranchPredictor(TournamentBP(numThreads = 172 Parent.numThreads), 173 "Branch Predictor") 174 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 175 "Enable TSO Memory model") 176 177 def addCheckerCpu(self): 178 if buildEnv['TARGET_ISA'] in ['arm']: 179 from ArmTLB import ArmTLB 180 181 self.checker = O3Checker(workload=self.workload, 182 exitOnError=False, 183 updateOnError=True, 184 warnOnlyOnLoadError=True) 185 self.checker.itb = ArmTLB(size = self.itb.size) 186 self.checker.dtb = ArmTLB(size = self.dtb.size) 187 self.checker.cpu_id = self.cpu_id 188 189 else: 190 print("ERROR: Checker only supported under ARM ISA!") 191 exit(1) 192