O3CPU.py revision 13561
113559Snikos.nikoleris@arm.com# Copyright (c) 2016, 2019 ARM Limited 212109SRekai.GonzalezAlberquilla@arm.com# All rights reserved. 312109SRekai.GonzalezAlberquilla@arm.com# 412109SRekai.GonzalezAlberquilla@arm.com# The license below extends only to copyright in the software and shall 512109SRekai.GonzalezAlberquilla@arm.com# not be construed as granting a license to any other intellectual 612109SRekai.GonzalezAlberquilla@arm.com# property including but not limited to intellectual property relating 712109SRekai.GonzalezAlberquilla@arm.com# to a hardware implementation of the functionality of the software 812109SRekai.GonzalezAlberquilla@arm.com# licensed hereunder. You may use the software subject to the license 912109SRekai.GonzalezAlberquilla@arm.com# terms below provided that you ensure that this notice is replicated 1012109SRekai.GonzalezAlberquilla@arm.com# unmodified and in its entirety in all distributions of the software, 1112109SRekai.GonzalezAlberquilla@arm.com# modified or unmodified, in source code or in binary form. 1212109SRekai.GonzalezAlberquilla@arm.com# 134486Sbinkertn@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 144486Sbinkertn@umich.edu# All rights reserved. 154486Sbinkertn@umich.edu# 164486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 174486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 184486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 194486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 204486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 214486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 224486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 234486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 244486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 254486Sbinkertn@umich.edu# this software without specific prior written permission. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486Sbinkertn@umich.edu# 394486Sbinkertn@umich.edu# Authors: Kevin Lim 404486Sbinkertn@umich.edu 4112563Sgabeblack@google.comfrom __future__ import print_function 4212563Sgabeblack@google.com 436654Snate@binkert.orgfrom m5.defines import buildEnv 443102SN/Afrom m5.params import * 453102SN/Afrom m5.proxy import * 461681SN/Afrom BaseCPU import BaseCPU 473223SN/Afrom FUPool import * 488887Sgeoffrey.blake@arm.comfrom O3Checker import O3Checker 4910785Sgope@wisc.edufrom BranchPredictor import * 504486Sbinkertn@umich.edu 5113559Snikos.nikoleris@arm.comclass FetchPolicy(ScopedEnum): 5213559Snikos.nikoleris@arm.com vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ] 5313559Snikos.nikoleris@arm.com 5413560Snikos.nikoleris@arm.comclass SMTQueuePolicy(ScopedEnum): 5513560Snikos.nikoleris@arm.com vals = [ 'Dynamic', 'Partitioned', 'Threshold' ] 5613560Snikos.nikoleris@arm.com 572817SN/Aclass DerivO3CPU(BaseCPU): 582817SN/A type = 'DerivO3CPU' 599341SAndreas.Sandberg@arm.com cxx_header = 'cpu/o3/deriv.hh' 609341SAndreas.Sandberg@arm.com 619518SAndreas.Sandberg@ARM.com @classmethod 629518SAndreas.Sandberg@ARM.com def memory_mode(cls): 639518SAndreas.Sandberg@ARM.com return 'timing' 649518SAndreas.Sandberg@ARM.com 659518SAndreas.Sandberg@ARM.com @classmethod 669518SAndreas.Sandberg@ARM.com def require_caches(cls): 679518SAndreas.Sandberg@ARM.com return True 689518SAndreas.Sandberg@ARM.com 699518SAndreas.Sandberg@ARM.com @classmethod 709518SAndreas.Sandberg@ARM.com def support_take_over(cls): 719518SAndreas.Sandberg@ARM.com return True 729518SAndreas.Sandberg@ARM.com 732932SN/A activity = Param.Unsigned(0, "Initial count") 741681SN/A 7511780Sarthur.perais@inria.fr cacheStorePorts = Param.Unsigned(200, "Cache Ports. " 7611780Sarthur.perais@inria.fr "Constrains stores only. Loads are constrained by load FUs.") 771681SN/A 789184Sandreas.hansson@arm.com decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 799184Sandreas.hansson@arm.com renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 809184Sandreas.hansson@arm.com iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 819184Sandreas.hansson@arm.com "delay") 829184Sandreas.hansson@arm.com commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 832932SN/A fetchWidth = Param.Unsigned(8, "Fetch width") 849982Satgutier@umich.edu fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") 8510331Smitch.hayenga@arm.com fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops " 8610331Smitch.hayenga@arm.com "per-thread") 872932SN/A 889184Sandreas.hansson@arm.com renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 899184Sandreas.hansson@arm.com iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 909184Sandreas.hansson@arm.com "delay") 919184Sandreas.hansson@arm.com commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 929184Sandreas.hansson@arm.com fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 932932SN/A decodeWidth = Param.Unsigned(8, "Decode width") 941681SN/A 959184Sandreas.hansson@arm.com iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 969184Sandreas.hansson@arm.com "delay") 979184Sandreas.hansson@arm.com commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 989184Sandreas.hansson@arm.com decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 992932SN/A renameWidth = Param.Unsigned(8, "Rename width") 1001681SN/A 1019184Sandreas.hansson@arm.com commitToIEWDelay = Param.Cycles(1, "Commit to " 1022932SN/A "Issue/Execute/Writeback delay") 1039184Sandreas.hansson@arm.com renameToIEWDelay = Param.Cycles(2, "Rename to " 1042932SN/A "Issue/Execute/Writeback delay") 1059184Sandreas.hansson@arm.com issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 1062932SN/A "to the IEW stage)") 1072932SN/A dispatchWidth = Param.Unsigned(8, "Dispatch width") 1082932SN/A issueWidth = Param.Unsigned(8, "Issue width") 1092932SN/A wbWidth = Param.Unsigned(8, "Writeback width") 1103223SN/A fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 1112932SN/A 1129184Sandreas.hansson@arm.com iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 1131681SN/A "delay") 1149184Sandreas.hansson@arm.com renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 1152932SN/A commitWidth = Param.Unsigned(8, "Commit width") 1162932SN/A squashWidth = Param.Unsigned(8, "Squash width") 1179184Sandreas.hansson@arm.com trapLatency = Param.Cycles(13, "Trap latency") 1189184Sandreas.hansson@arm.com fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 1191681SN/A 1202932SN/A backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 1212932SN/A forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 1221681SN/A 1232932SN/A LQEntries = Param.Unsigned(32, "Number of load queue entries") 1242932SN/A SQEntries = Param.Unsigned(32, "Number of store queue entries") 1258199SAli.Saidi@ARM.com LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 1268199SAli.Saidi@ARM.com LSQCheckLoads = Param.Bool(True, 1278199SAli.Saidi@ARM.com "Should dependency violations be checked for loads & stores or just stores") 1288519SAli.Saidi@ARM.com store_set_clear_period = Param.Unsigned(250000, 1298519SAli.Saidi@ARM.com "Number of load/store insts before the dep predictor should be invalidated") 1302932SN/A LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 1312932SN/A SSITSize = Param.Unsigned(1024, "Store set ID table size") 1321681SN/A 1332932SN/A numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 1341681SN/A 1352932SN/A numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 1362932SN/A numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 1372932SN/A "registers") 1389921Syasuko.eckert@amd.com # most ISAs don't use condition-code regs, so default is 0 1399921Syasuko.eckert@amd.com _defaultNumPhysCCRegs = 0 14010338SCurtis.Dunham@arm.com if buildEnv['TARGET_ISA'] in ('arm','x86'): 1419921Syasuko.eckert@amd.com # For x86, each CC reg is used to hold only a subset of the 1429921Syasuko.eckert@amd.com # flags, so we need 4-5 times the number of CC regs as 1439921Syasuko.eckert@amd.com # physical integer regs to be sure we don't run out. In 1449921Syasuko.eckert@amd.com # typical real machines, CC regs are not explicitly renamed 1459921Syasuko.eckert@amd.com # (it's a side effect of int reg renaming), so they should 1469921Syasuko.eckert@amd.com # never be the bottleneck here. 1479921Syasuko.eckert@amd.com _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 14812109SRekai.GonzalezAlberquilla@arm.com numPhysVecRegs = Param.Unsigned(256, "Number of physical vector " 14912109SRekai.GonzalezAlberquilla@arm.com "registers") 1509921Syasuko.eckert@amd.com numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, 1519921Syasuko.eckert@amd.com "Number of physical cc registers") 1522932SN/A numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 1532932SN/A numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 1541681SN/A 1554597Sbinkertn@umich.edu smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 15613559Snikos.nikoleris@arm.com smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy") 15713560Snikos.nikoleris@arm.com smtLSQPolicy = Param.SMTQueuePolicy('Partitioned', 15813560Snikos.nikoleris@arm.com "SMT LSQ Sharing Policy") 1594597Sbinkertn@umich.edu smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 16013561Snikos.nikoleris@arm.com smtIQPolicy = Param.SMTQueuePolicy('Partitioned', 16113561Snikos.nikoleris@arm.com "SMT IQ Sharing Policy") 1624597Sbinkertn@umich.edu smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 1634597Sbinkertn@umich.edu smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 1644597Sbinkertn@umich.edu smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 1654597Sbinkertn@umich.edu smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 1664303SN/A 16710785Sgope@wisc.edu branchPred = Param.BranchPredictor(TournamentBP(numThreads = 1689849Sandreas.hansson@arm.com Parent.numThreads), 1699849Sandreas.hansson@arm.com "Branch Predictor") 1708727Snilay@cs.wisc.edu needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 1718727Snilay@cs.wisc.edu "Enable TSO Memory model") 1728887Sgeoffrey.blake@arm.com 1738887Sgeoffrey.blake@arm.com def addCheckerCpu(self): 1748887Sgeoffrey.blake@arm.com if buildEnv['TARGET_ISA'] in ['arm']: 1758887Sgeoffrey.blake@arm.com from ArmTLB import ArmTLB 1768887Sgeoffrey.blake@arm.com 1778887Sgeoffrey.blake@arm.com self.checker = O3Checker(workload=self.workload, 1788887Sgeoffrey.blake@arm.com exitOnError=False, 1798887Sgeoffrey.blake@arm.com updateOnError=True, 1808887Sgeoffrey.blake@arm.com warnOnlyOnLoadError=True) 1818887Sgeoffrey.blake@arm.com self.checker.itb = ArmTLB(size = self.itb.size) 1828887Sgeoffrey.blake@arm.com self.checker.dtb = ArmTLB(size = self.dtb.size) 1839132Satgutier@umich.edu self.checker.cpu_id = self.cpu_id 1848887Sgeoffrey.blake@arm.com 1858887Sgeoffrey.blake@arm.com else: 18612563Sgabeblack@google.com print("ERROR: Checker only supported under ARM ISA!") 1878887Sgeoffrey.blake@arm.com exit(1) 188