O3CPU.py revision 13560
14604Sgblack@eecs.umich.edu# Copyright (c) 2016, 2019 ARM Limited 24604Sgblack@eecs.umich.edu# All rights reserved. 34604Sgblack@eecs.umich.edu# 44604Sgblack@eecs.umich.edu# The license below extends only to copyright in the software and shall 54604Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 64604Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 74604Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 84604Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 94604Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 104604Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 114604Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 124604Sgblack@eecs.umich.edu# 134604Sgblack@eecs.umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 144604Sgblack@eecs.umich.edu# All rights reserved. 154604Sgblack@eecs.umich.edu# 164604Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 174604Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 184604Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 194604Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 204604Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 214604Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 224604Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 234604Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 244604Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 254604Sgblack@eecs.umich.edu# this software without specific prior written permission. 264604Sgblack@eecs.umich.edu# 274604Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284604Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294604Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304604Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314604Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324604Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334604Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344604Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354604Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364604Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374604Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384604Sgblack@eecs.umich.edu# 394604Sgblack@eecs.umich.edu# Authors: Kevin Lim 404604Sgblack@eecs.umich.edu 414604Sgblack@eecs.umich.edufrom __future__ import print_function 424604Sgblack@eecs.umich.edu 434604Sgblack@eecs.umich.edufrom m5.defines import buildEnv 444604Sgblack@eecs.umich.edufrom m5.params import * 454604Sgblack@eecs.umich.edufrom m5.proxy import * 464604Sgblack@eecs.umich.edufrom BaseCPU import BaseCPU 474604Sgblack@eecs.umich.edufrom FUPool import * 484604Sgblack@eecs.umich.edufrom O3Checker import O3Checker 494604Sgblack@eecs.umich.edufrom BranchPredictor import * 504604Sgblack@eecs.umich.edu 514604Sgblack@eecs.umich.educlass FetchPolicy(ScopedEnum): 524604Sgblack@eecs.umich.edu vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ] 534604Sgblack@eecs.umich.edu 544604Sgblack@eecs.umich.educlass SMTQueuePolicy(ScopedEnum): 554604Sgblack@eecs.umich.edu vals = [ 'Dynamic', 'Partitioned', 'Threshold' ] 564604Sgblack@eecs.umich.edu 574604Sgblack@eecs.umich.educlass DerivO3CPU(BaseCPU): 585616Snate@binkert.org type = 'DerivO3CPU' 595616Snate@binkert.org cxx_header = 'cpu/o3/deriv.hh' 604604Sgblack@eecs.umich.edu 614604Sgblack@eecs.umich.edu @classmethod 624604Sgblack@eecs.umich.edu def memory_mode(cls): 634604Sgblack@eecs.umich.edu return 'timing' 644604Sgblack@eecs.umich.edu 654604Sgblack@eecs.umich.edu @classmethod 664604Sgblack@eecs.umich.edu def require_caches(cls): 674604Sgblack@eecs.umich.edu return True 684604Sgblack@eecs.umich.edu 694604Sgblack@eecs.umich.edu @classmethod 704604Sgblack@eecs.umich.edu def support_take_over(cls): 714712Sgblack@eecs.umich.edu return True 724712Sgblack@eecs.umich.edu 734604Sgblack@eecs.umich.edu activity = Param.Unsigned(0, "Initial count") 744604Sgblack@eecs.umich.edu 754604Sgblack@eecs.umich.edu cacheStorePorts = Param.Unsigned(200, "Cache Ports. " 764604Sgblack@eecs.umich.edu "Constrains stores only. Loads are constrained by load FUs.") 774604Sgblack@eecs.umich.edu 784848Sgblack@eecs.umich.edu decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 794604Sgblack@eecs.umich.edu renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 804604Sgblack@eecs.umich.edu iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 814604Sgblack@eecs.umich.edu "delay") 826071Sgblack@eecs.umich.edu commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 836071Sgblack@eecs.umich.edu fetchWidth = Param.Unsigned(8, "Fetch width") 846071Sgblack@eecs.umich.edu fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") 856071Sgblack@eecs.umich.edu fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops " 866071Sgblack@eecs.umich.edu "per-thread") 876071Sgblack@eecs.umich.edu 886071Sgblack@eecs.umich.edu renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 896071Sgblack@eecs.umich.edu iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 906071Sgblack@eecs.umich.edu "delay") 916071Sgblack@eecs.umich.edu commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 926071Sgblack@eecs.umich.edu fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 936071Sgblack@eecs.umich.edu decodeWidth = Param.Unsigned(8, "Decode width") 946071Sgblack@eecs.umich.edu 956071Sgblack@eecs.umich.edu iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 966071Sgblack@eecs.umich.edu "delay") 976071Sgblack@eecs.umich.edu commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 986071Sgblack@eecs.umich.edu decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 996071Sgblack@eecs.umich.edu renameWidth = Param.Unsigned(8, "Rename width") 1006071Sgblack@eecs.umich.edu 1016071Sgblack@eecs.umich.edu commitToIEWDelay = Param.Cycles(1, "Commit to " 1026071Sgblack@eecs.umich.edu "Issue/Execute/Writeback delay") 1036071Sgblack@eecs.umich.edu renameToIEWDelay = Param.Cycles(2, "Rename to " 1046071Sgblack@eecs.umich.edu "Issue/Execute/Writeback delay") 1056071Sgblack@eecs.umich.edu issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 1066071Sgblack@eecs.umich.edu "to the IEW stage)") 1076071Sgblack@eecs.umich.edu dispatchWidth = Param.Unsigned(8, "Dispatch width") 1084604Sgblack@eecs.umich.edu issueWidth = Param.Unsigned(8, "Issue width") 1094604Sgblack@eecs.umich.edu wbWidth = Param.Unsigned(8, "Writeback width") 1104712Sgblack@eecs.umich.edu fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 1114604Sgblack@eecs.umich.edu 1124712Sgblack@eecs.umich.edu iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 1134712Sgblack@eecs.umich.edu "delay") 1144848Sgblack@eecs.umich.edu renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 1154604Sgblack@eecs.umich.edu commitWidth = Param.Unsigned(8, "Commit width") 1164604Sgblack@eecs.umich.edu squashWidth = Param.Unsigned(8, "Squash width") 1174604Sgblack@eecs.umich.edu trapLatency = Param.Cycles(13, "Trap latency") 1184863Sgblack@eecs.umich.edu fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 1194863Sgblack@eecs.umich.edu 1204863Sgblack@eecs.umich.edu backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 1216437Sgblack@eecs.umich.edu forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 1224863Sgblack@eecs.umich.edu 1234863Sgblack@eecs.umich.edu LQEntries = Param.Unsigned(32, "Number of load queue entries") 1244863Sgblack@eecs.umich.edu SQEntries = Param.Unsigned(32, "Number of store queue entries") 1254863Sgblack@eecs.umich.edu LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 1264863Sgblack@eecs.umich.edu LSQCheckLoads = Param.Bool(True, 1274863Sgblack@eecs.umich.edu "Should dependency violations be checked for loads & stores or just stores") 1284863Sgblack@eecs.umich.edu store_set_clear_period = Param.Unsigned(250000, 1294863Sgblack@eecs.umich.edu "Number of load/store insts before the dep predictor should be invalidated") 1304604Sgblack@eecs.umich.edu LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 1314604Sgblack@eecs.umich.edu SSITSize = Param.Unsigned(1024, "Store set ID table size") 1325966Sgblack@eecs.umich.edu 1335966Sgblack@eecs.umich.edu numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 1345966Sgblack@eecs.umich.edu 1355966Sgblack@eecs.umich.edu numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 1365966Sgblack@eecs.umich.edu numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 1375966Sgblack@eecs.umich.edu "registers") 1385966Sgblack@eecs.umich.edu # most ISAs don't use condition-code regs, so default is 0 1395966Sgblack@eecs.umich.edu _defaultNumPhysCCRegs = 0 140 if buildEnv['TARGET_ISA'] in ('arm','x86'): 141 # For x86, each CC reg is used to hold only a subset of the 142 # flags, so we need 4-5 times the number of CC regs as 143 # physical integer regs to be sure we don't run out. In 144 # typical real machines, CC regs are not explicitly renamed 145 # (it's a side effect of int reg renaming), so they should 146 # never be the bottleneck here. 147 _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 148 numPhysVecRegs = Param.Unsigned(256, "Number of physical vector " 149 "registers") 150 numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, 151 "Number of physical cc registers") 152 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 153 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 154 155 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 156 smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy") 157 smtLSQPolicy = Param.SMTQueuePolicy('Partitioned', 158 "SMT LSQ Sharing Policy") 159 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 160 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 161 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 162 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 163 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 164 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 165 166 branchPred = Param.BranchPredictor(TournamentBP(numThreads = 167 Parent.numThreads), 168 "Branch Predictor") 169 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 170 "Enable TSO Memory model") 171 172 def addCheckerCpu(self): 173 if buildEnv['TARGET_ISA'] in ['arm']: 174 from ArmTLB import ArmTLB 175 176 self.checker = O3Checker(workload=self.workload, 177 exitOnError=False, 178 updateOnError=True, 179 warnOnlyOnLoadError=True) 180 self.checker.itb = ArmTLB(size = self.itb.size) 181 self.checker.dtb = ArmTLB(size = self.dtb.size) 182 self.checker.cpu_id = self.cpu_id 183 184 else: 185 print("ERROR: Checker only supported under ARM ISA!") 186 exit(1) 187