O3CPU.py revision 10331
14604Sgblack@eecs.umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 24604Sgblack@eecs.umich.edu# All rights reserved. 34604Sgblack@eecs.umich.edu# 44604Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 57087Snate@binkert.org# modification, are permitted provided that the following conditions are 67087Snate@binkert.org# met: redistributions of source code must retain the above copyright 77087Snate@binkert.org# notice, this list of conditions and the following disclaimer; 87087Snate@binkert.org# redistributions in binary form must reproduce the above copyright 97087Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 107087Snate@binkert.org# documentation and/or other materials provided with the distribution; 117087Snate@binkert.org# neither the name of the copyright holders nor the names of its 127087Snate@binkert.org# contributors may be used to endorse or promote products derived from 134604Sgblack@eecs.umich.edu# this software without specific prior written permission. 147087Snate@binkert.org# 157087Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167087Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177087Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187087Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197087Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207087Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217087Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224604Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237087Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244604Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254604Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264604Sgblack@eecs.umich.edu# 274604Sgblack@eecs.umich.edu# Authors: Kevin Lim 284604Sgblack@eecs.umich.edu 294604Sgblack@eecs.umich.edufrom m5.defines import buildEnv 304604Sgblack@eecs.umich.edufrom m5.params import * 314604Sgblack@eecs.umich.edufrom m5.proxy import * 324604Sgblack@eecs.umich.edufrom BaseCPU import BaseCPU 334604Sgblack@eecs.umich.edufrom FUPool import * 344604Sgblack@eecs.umich.edufrom O3Checker import O3Checker 354604Sgblack@eecs.umich.edufrom BranchPredictor import BranchPredictor 364604Sgblack@eecs.umich.edu 374604Sgblack@eecs.umich.educlass DerivO3CPU(BaseCPU): 384604Sgblack@eecs.umich.edu type = 'DerivO3CPU' 394604Sgblack@eecs.umich.edu cxx_header = 'cpu/o3/deriv.hh' 4011793Sbrandon.potter@amd.com 4111793Sbrandon.potter@amd.com @classmethod 425616Snate@binkert.org def memory_mode(cls): 435616Snate@binkert.org return 'timing' 444604Sgblack@eecs.umich.edu 454604Sgblack@eecs.umich.edu @classmethod 464604Sgblack@eecs.umich.edu def require_caches(cls): 474604Sgblack@eecs.umich.edu return True 484604Sgblack@eecs.umich.edu 494604Sgblack@eecs.umich.edu @classmethod 504604Sgblack@eecs.umich.edu def support_take_over(cls): 514604Sgblack@eecs.umich.edu return True 524604Sgblack@eecs.umich.edu 534604Sgblack@eecs.umich.edu activity = Param.Unsigned(0, "Initial count") 544712Sgblack@eecs.umich.edu 554712Sgblack@eecs.umich.edu cachePorts = Param.Unsigned(200, "Cache Ports") 564604Sgblack@eecs.umich.edu 579023Sgblack@eecs.umich.edu decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay") 584604Sgblack@eecs.umich.edu renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay") 594604Sgblack@eecs.umich.edu iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch " 604604Sgblack@eecs.umich.edu "delay") 614848Sgblack@eecs.umich.edu commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay") 624604Sgblack@eecs.umich.edu fetchWidth = Param.Unsigned(8, "Fetch width") 634604Sgblack@eecs.umich.edu fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes") 644604Sgblack@eecs.umich.edu fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops " 656071Sgblack@eecs.umich.edu "per-thread") 666071Sgblack@eecs.umich.edu 676071Sgblack@eecs.umich.edu renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay") 686071Sgblack@eecs.umich.edu iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode " 696071Sgblack@eecs.umich.edu "delay") 706071Sgblack@eecs.umich.edu commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay") 716071Sgblack@eecs.umich.edu fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay") 726071Sgblack@eecs.umich.edu decodeWidth = Param.Unsigned(8, "Decode width") 736071Sgblack@eecs.umich.edu 746071Sgblack@eecs.umich.edu iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename " 756071Sgblack@eecs.umich.edu "delay") 766071Sgblack@eecs.umich.edu commitToRenameDelay = Param.Cycles(1, "Commit to rename delay") 776071Sgblack@eecs.umich.edu decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay") 786071Sgblack@eecs.umich.edu renameWidth = Param.Unsigned(8, "Rename width") 796071Sgblack@eecs.umich.edu 806071Sgblack@eecs.umich.edu commitToIEWDelay = Param.Cycles(1, "Commit to " 816071Sgblack@eecs.umich.edu "Issue/Execute/Writeback delay") 826071Sgblack@eecs.umich.edu renameToIEWDelay = Param.Cycles(2, "Rename to " 836071Sgblack@eecs.umich.edu "Issue/Execute/Writeback delay") 846071Sgblack@eecs.umich.edu issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal " 856071Sgblack@eecs.umich.edu "to the IEW stage)") 866071Sgblack@eecs.umich.edu dispatchWidth = Param.Unsigned(8, "Dispatch width") 876071Sgblack@eecs.umich.edu issueWidth = Param.Unsigned(8, "Issue width") 886071Sgblack@eecs.umich.edu wbWidth = Param.Unsigned(8, "Writeback width") 896071Sgblack@eecs.umich.edu fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool") 906071Sgblack@eecs.umich.edu 914604Sgblack@eecs.umich.edu iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit " 924604Sgblack@eecs.umich.edu "delay") 934712Sgblack@eecs.umich.edu renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay") 944604Sgblack@eecs.umich.edu commitWidth = Param.Unsigned(8, "Commit width") 954712Sgblack@eecs.umich.edu squashWidth = Param.Unsigned(8, "Squash width") 964712Sgblack@eecs.umich.edu trapLatency = Param.Cycles(13, "Trap latency") 974848Sgblack@eecs.umich.edu fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 984604Sgblack@eecs.umich.edu 994604Sgblack@eecs.umich.edu backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 1004604Sgblack@eecs.umich.edu forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 1014863Sgblack@eecs.umich.edu 1024863Sgblack@eecs.umich.edu LQEntries = Param.Unsigned(32, "Number of load queue entries") 1034863Sgblack@eecs.umich.edu SQEntries = Param.Unsigned(32, "Number of store queue entries") 1046437Sgblack@eecs.umich.edu LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 1054863Sgblack@eecs.umich.edu LSQCheckLoads = Param.Bool(True, 1064863Sgblack@eecs.umich.edu "Should dependency violations be checked for loads & stores or just stores") 1074863Sgblack@eecs.umich.edu store_set_clear_period = Param.Unsigned(250000, 1084863Sgblack@eecs.umich.edu "Number of load/store insts before the dep predictor should be invalidated") 1094863Sgblack@eecs.umich.edu LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 1104863Sgblack@eecs.umich.edu SSITSize = Param.Unsigned(1024, "Store set ID table size") 1114863Sgblack@eecs.umich.edu 1124863Sgblack@eecs.umich.edu numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 1134604Sgblack@eecs.umich.edu 1144604Sgblack@eecs.umich.edu numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 1155966Sgblack@eecs.umich.edu numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 1165966Sgblack@eecs.umich.edu "registers") 1175966Sgblack@eecs.umich.edu # most ISAs don't use condition-code regs, so default is 0 1185966Sgblack@eecs.umich.edu _defaultNumPhysCCRegs = 0 1195966Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'x86': 1205966Sgblack@eecs.umich.edu # For x86, each CC reg is used to hold only a subset of the 1215966Sgblack@eecs.umich.edu # flags, so we need 4-5 times the number of CC regs as 1225966Sgblack@eecs.umich.edu # physical integer regs to be sure we don't run out. In 123 # typical real machines, CC regs are not explicitly renamed 124 # (it's a side effect of int reg renaming), so they should 125 # never be the bottleneck here. 126 _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 127 numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, 128 "Number of physical cc registers") 129 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 130 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 131 132 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 133 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 134 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 135 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 136 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 137 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 138 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 139 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 140 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 141 142 branchPred = Param.BranchPredictor(BranchPredictor(numThreads = 143 Parent.numThreads), 144 "Branch Predictor") 145 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 146 "Enable TSO Memory model") 147 148 def addCheckerCpu(self): 149 if buildEnv['TARGET_ISA'] in ['arm']: 150 from ArmTLB import ArmTLB 151 152 self.checker = O3Checker(workload=self.workload, 153 exitOnError=False, 154 updateOnError=True, 155 warnOnlyOnLoadError=True) 156 self.checker.itb = ArmTLB(size = self.itb.size) 157 self.checker.dtb = ArmTLB(size = self.dtb.size) 158 self.checker.cpu_id = self.cpu_id 159 160 else: 161 print "ERROR: Checker only supported under ARM ISA!" 162 exit(1) 163