FuncUnitConfig.py revision 10806:b9410e821c41 
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396145Snate@binkert.org# Authors: Kevin Lim
406145Snate@binkert.org
416145Snate@binkert.orgfrom m5.SimObject import SimObject
427039Snate@binkert.orgfrom m5.defines import buildEnv
437039Snate@binkert.orgfrom m5.params import *
447039Snate@binkert.orgfrom FuncUnit import *
457039Snate@binkert.org
467039Snate@binkert.orgclass IntALU(FUDesc):
477039Snate@binkert.org    opList = [ OpDesc(opClass='IntAlu') ]
487039Snate@binkert.org    count = 6
497039Snate@binkert.org
507039Snate@binkert.orgclass IntMultDiv(FUDesc):
517039Snate@binkert.org    opList = [ OpDesc(opClass='IntMult', opLat=3),
526145Snate@binkert.org               OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
537039Snate@binkert.org
546145Snate@binkert.org    # DIV and IDIV instructions in x86 are implemented using a loop which
557039Snate@binkert.org    # issues division microops.  The latency of these microops should really be
567039Snate@binkert.org    # one (or a small number) cycle each since each of these computes one bit
577039Snate@binkert.org    # of the quotient.
586145Snate@binkert.org    if buildEnv['TARGET_ISA'] in ('x86'):
597039Snate@binkert.org        opList[1].opLat=1
607039Snate@binkert.org        opList[1].issueLat=1
617039Snate@binkert.org
627039Snate@binkert.org    count=2
637039Snate@binkert.org
647039Snate@binkert.orgclass FP_ALU(FUDesc):
656145Snate@binkert.org    opList = [ OpDesc(opClass='FloatAdd', opLat=2),
667039Snate@binkert.org               OpDesc(opClass='FloatCmp', opLat=2),
677039Snate@binkert.org               OpDesc(opClass='FloatCvt', opLat=2) ]
686145Snate@binkert.org    count = 4
697039Snate@binkert.org
707039Snate@binkert.orgclass FP_MultDiv(FUDesc):
717039Snate@binkert.org    opList = [ OpDesc(opClass='FloatMult', opLat=4),
727039Snate@binkert.org               OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
736145Snate@binkert.org               OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
746145Snate@binkert.org    count = 2
757039Snate@binkert.org
767039Snate@binkert.orgclass SIMD_Unit(FUDesc):
776145Snate@binkert.org    opList = [ OpDesc(opClass='SimdAdd'),
787039Snate@binkert.org               OpDesc(opClass='SimdAddAcc'),
797039Snate@binkert.org               OpDesc(opClass='SimdAlu'),
807039Snate@binkert.org               OpDesc(opClass='SimdCmp'),
816145Snate@binkert.org               OpDesc(opClass='SimdCvt'),
826145Snate@binkert.org               OpDesc(opClass='SimdMisc'),
837039Snate@binkert.org               OpDesc(opClass='SimdMult'),
84               OpDesc(opClass='SimdMultAcc'),
85               OpDesc(opClass='SimdShift'),
86               OpDesc(opClass='SimdShiftAcc'),
87               OpDesc(opClass='SimdSqrt'),
88               OpDesc(opClass='SimdFloatAdd'),
89               OpDesc(opClass='SimdFloatAlu'),
90               OpDesc(opClass='SimdFloatCmp'),
91               OpDesc(opClass='SimdFloatCvt'),
92               OpDesc(opClass='SimdFloatDiv'),
93               OpDesc(opClass='SimdFloatMisc'),
94               OpDesc(opClass='SimdFloatMult'),
95               OpDesc(opClass='SimdFloatMultAcc'),
96               OpDesc(opClass='SimdFloatSqrt') ]
97    count = 4
98
99class ReadPort(FUDesc):
100    opList = [ OpDesc(opClass='MemRead') ]
101    count = 0
102
103class WritePort(FUDesc):
104    opList = [ OpDesc(opClass='MemWrite') ]
105    count = 0
106
107class RdWrPort(FUDesc):
108    opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
109    count = 4
110
111class IprPort(FUDesc):
112    opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
113    count = 1
114
115