FuncUnitConfig.py revision 4486
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274486Sbinkertn@umich.edu# Authors: Kevin Lim
284486Sbinkertn@umich.edu
293223SN/Afrom m5.SimObject import SimObject
303223SN/Afrom m5.params import *
313223SN/Afrom FuncUnit import *
323223SN/A
333223SN/Aclass IntALU(FUDesc):
343223SN/A    opList = [ OpDesc(opClass='IntAlu') ]
353223SN/A    count = 6
363223SN/A
373223SN/Aclass IntMultDiv(FUDesc):
383223SN/A    opList = [ OpDesc(opClass='IntMult', opLat=3),
393223SN/A               OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
403223SN/A    count=2
413223SN/A
423223SN/Aclass FP_ALU(FUDesc):
433223SN/A    opList = [ OpDesc(opClass='FloatAdd', opLat=2),
443223SN/A               OpDesc(opClass='FloatCmp', opLat=2),
453223SN/A               OpDesc(opClass='FloatCvt', opLat=2) ]
463223SN/A    count = 4
473223SN/A
483223SN/Aclass FP_MultDiv(FUDesc):
493223SN/A    opList = [ OpDesc(opClass='FloatMult', opLat=4),
503223SN/A               OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
513223SN/A               OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
523223SN/A    count = 2
533223SN/A
543223SN/Aclass ReadPort(FUDesc):
553223SN/A    opList = [ OpDesc(opClass='MemRead') ]
563223SN/A    count = 0
573223SN/A
583223SN/Aclass WritePort(FUDesc):
593223SN/A    opList = [ OpDesc(opClass='MemWrite') ]
603223SN/A    count = 0
613223SN/A
623223SN/Aclass RdWrPort(FUDesc):
633223SN/A    opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
643223SN/A    count = 4
653223SN/A
663223SN/Aclass IprPort(FUDesc):
673223SN/A    opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
683223SN/A    count = 1
693223SN/A
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