scoreboard.hh revision 13597:6b0f8e9cdeb5
1451SN/A/* 22212SN/A * Copyright (c) 2013-2014, 2016 ARM Limited 3451SN/A * All rights reserved 4451SN/A * 5451SN/A * The license below extends only to copyright in the software and shall 6451SN/A * not be construed as granting a license to any other intellectual 7451SN/A * property including but not limited to intellectual property relating 8451SN/A * to a hardware implementation of the functionality of the software 9451SN/A * licensed hereunder. You may use the software subject to the license 10451SN/A * terms below provided that you ensure that this notice is replicated 11451SN/A * unmodified and in its entirety in all distributions of the software, 12451SN/A * modified or unmodified, in source code or in binary form. 13451SN/A * 14451SN/A * Redistribution and use in source and binary forms, with or without 15451SN/A * modification, are permitted provided that the following conditions are 16451SN/A * met: redistributions of source code must retain the above copyright 17451SN/A * notice, this list of conditions and the following disclaimer; 18451SN/A * redistributions in binary form must reproduce the above copyright 19451SN/A * notice, this list of conditions and the following disclaimer in the 20451SN/A * documentation and/or other materials provided with the distribution; 21451SN/A * neither the name of the copyright holders nor the names of its 22451SN/A * contributors may be used to endorse or promote products derived from 23451SN/A * this software without specific prior written permission. 24451SN/A * 25451SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26451SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292665Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302665Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31451SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32451SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332212SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342212SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35451SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362680Sktlim@umich.edu * 371070SN/A * Authors: Andrew Bardsley 381070SN/A */ 391070SN/A 402212SN/A/** 412212SN/A * @file 422212SN/A * 432212SN/A * A simple instruction scoreboard for tracking dependencies in Execute. 442212SN/A */ 452212SN/A 46451SN/A#ifndef __CPU_MINOR_SCOREBOARD_HH__ 47885SN/A#define __CPU_MINOR_SCOREBOARD_HH__ 48885SN/A 49885SN/A#include "cpu/minor/cpu.hh" 50885SN/A#include "cpu/minor/dyn_inst.hh" 51885SN/A#include "cpu/minor/trace.hh" 522212SN/A 53451SN/Anamespace Minor 54451SN/A{ 551885SN/A 561885SN/A/** A scoreboard of register dependencies including, for each register: 571885SN/A * The number of in-flight instructions which will generate a result for 581885SN/A * this register */ 591885SN/Aclass Scoreboard : public Named 602680Sktlim@umich.edu{ 611885SN/A public: 621885SN/A /** The number of registers in the Scoreboard. These 631885SN/A * are just the integer, CC and float registers packed 641885SN/A * together with integer regs in the range [0,NumIntRegs-1], 651885SN/A * CC regs in the range [NumIntRegs, NumIntRegs+NumCCRegs-1] 661885SN/A * and float regs in the range 671885SN/A * [NumIntRegs+NumCCRegs, NumFloatRegs+NumIntRegs+NumCCRegs-1] */ 682680Sktlim@umich.edu const unsigned numRegs; 691885SN/A 701885SN/A /** Type to use when indexing numResults */ 712212SN/A typedef unsigned short int Index; 721855SN/A 731855SN/A /** Count of the number of in-flight instructions that 741855SN/A * have results for each register */ 751855SN/A std::vector<Index> numResults; 761855SN/A 771855SN/A /** Count of the number of results which can't be predicted */ 781855SN/A std::vector<Index> numUnpredictableResults; 791855SN/A 801855SN/A /** Index of the FU generating this result */ 811855SN/A std::vector<int> fuIndices; 821855SN/A 831855SN/A /** The estimated cycle number that the result will be presented. 841855SN/A * This can be offset from to allow forwarding to be simulated as 851855SN/A * long as instruction completion is *strictly* in order with 861855SN/A * respect to instructions with unpredictable result timing */ 871855SN/A std::vector<Cycles> returnCycle; 881855SN/A 891855SN/A /** The execute sequence number of the most recent inst to generate this 901855SN/A * register value */ 911855SN/A std::vector<InstSeqNum> writingInst; 921492SN/A 93887SN/A public: 94451SN/A Scoreboard(const std::string &name) : 951492SN/A Named(name), 961492SN/A numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs + 971492SN/A TheISA::NumFloatRegs + 981070SN/A (TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg)), 99887SN/A numResults(numRegs, 0), 1001070SN/A numUnpredictableResults(numRegs, 0), 1011070SN/A fuIndices(numRegs, 0), 1021070SN/A returnCycle(numRegs, Cycles(0)), 103887SN/A writingInst(numRegs, 0) 104885SN/A { } 105887SN/A 106887SN/A public: 107885SN/A /** Sets scoreboard_index to the index into numResults of the 108887SN/A * given register index. Returns true if the given register 1091070SN/A * is in the scoreboard and false if it isn't */ 1101070SN/A bool findIndex(const RegId& reg, Index &scoreboard_index); 1111070SN/A 1121070SN/A /** Mark up an instruction's effects by incrementing 1131039SN/A * numResults counts. If mark_unpredictable is true, the inst's 1141039SN/A * destination registers are marked as being unpredictable without 1151070SN/A * an estimated retire time */ 1161070SN/A void markupInstDests(MinorDynInstPtr inst, Cycles retire_time, 117887SN/A ThreadContext *thread_context, bool mark_unpredictable); 118887SN/A 1191885SN/A /** Clear down the dependencies for this instruction. clear_unpredictable 120841SN/A * must match mark_unpredictable for the same inst. */ 1211082SN/A void clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable); 1221082SN/A 1231082SN/A /** Returns the exec sequence number of the most recent inst on 1241082SN/A * which the given inst depends. Useful for determining which 1251067SN/A * inst must actually be committed before a dependent inst 1261067SN/A * can call initiateAcc */ 1271082SN/A InstSeqNum execSeqNumToWaitFor(MinorDynInstPtr inst, 1281082SN/A ThreadContext *thread_context); 1291082SN/A 1301082SN/A /** Can this instruction be issued. Are any of its source registers 1311082SN/A * due to be written by other marked-up instructions in flight */ 1321082SN/A bool canInstIssue(MinorDynInstPtr inst, 1331082SN/A const std::vector<Cycles> *src_reg_relative_latencies, 1341082SN/A const std::vector<bool> *cant_forward_from_fu_indices, 1351082SN/A Cycles now, ThreadContext *thread_context); 1361084SN/A 1371084SN/A /** MinorTraceIF interface */ 1381082SN/A void minorTrace() const; 1391070SN/A}; 1401070SN/A 141451SN/A} 142451SN/A 1432212SN/A#endif /* __CPU_MINOR_SCOREBOARD_HH__ */ 1442212SN/A