lsq.cc revision 13954
110259SAndrew.Bardsley@arm.com/* 213954Sgiacomo.gabrielli@arm.com * Copyright (c) 2013-2014,2017-2018 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1510259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1610259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 1710259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 1810259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1910259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2010259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2110259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2210259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2310259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2410259SAndrew.Bardsley@arm.com * 2510259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610259SAndrew.Bardsley@arm.com * 3710259SAndrew.Bardsley@arm.com * Authors: Andrew Bardsley 3810259SAndrew.Bardsley@arm.com */ 3910259SAndrew.Bardsley@arm.com 4011793Sbrandon.potter@amd.com#include "cpu/minor/lsq.hh" 4111793Sbrandon.potter@amd.com 4210259SAndrew.Bardsley@arm.com#include <iomanip> 4310259SAndrew.Bardsley@arm.com#include <sstream> 4410259SAndrew.Bardsley@arm.com 4510259SAndrew.Bardsley@arm.com#include "arch/locked_mem.hh" 4610259SAndrew.Bardsley@arm.com#include "arch/mmapped_ipr.hh" 4713449Sgabeblack@google.com#include "base/logging.hh" 4810259SAndrew.Bardsley@arm.com#include "cpu/minor/cpu.hh" 4910259SAndrew.Bardsley@arm.com#include "cpu/minor/exec_context.hh" 5010259SAndrew.Bardsley@arm.com#include "cpu/minor/execute.hh" 5110259SAndrew.Bardsley@arm.com#include "cpu/minor/pipeline.hh" 5213954Sgiacomo.gabrielli@arm.com#include "cpu/utils.hh" 5310259SAndrew.Bardsley@arm.com#include "debug/Activity.hh" 5410259SAndrew.Bardsley@arm.com#include "debug/MinorMem.hh" 5510259SAndrew.Bardsley@arm.com 5610259SAndrew.Bardsley@arm.comnamespace Minor 5710259SAndrew.Bardsley@arm.com{ 5810259SAndrew.Bardsley@arm.com 5910259SAndrew.Bardsley@arm.comLSQ::LSQRequest::LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_, 6010259SAndrew.Bardsley@arm.com PacketDataPtr data_, uint64_t *res_) : 6110259SAndrew.Bardsley@arm.com SenderState(), 6210259SAndrew.Bardsley@arm.com port(port_), 6310259SAndrew.Bardsley@arm.com inst(inst_), 6410259SAndrew.Bardsley@arm.com isLoad(isLoad_), 6510259SAndrew.Bardsley@arm.com data(data_), 6610259SAndrew.Bardsley@arm.com packet(NULL), 6710259SAndrew.Bardsley@arm.com request(), 6810259SAndrew.Bardsley@arm.com fault(NoFault), 6910259SAndrew.Bardsley@arm.com res(res_), 7010259SAndrew.Bardsley@arm.com skipped(false), 7110259SAndrew.Bardsley@arm.com issuedToMemory(false), 7210259SAndrew.Bardsley@arm.com state(NotIssued) 7312749Sgiacomo.travaglini@arm.com{ 7412749Sgiacomo.travaglini@arm.com request = std::make_shared<Request>(); 7512749Sgiacomo.travaglini@arm.com} 7610259SAndrew.Bardsley@arm.com 7713954Sgiacomo.gabrielli@arm.comvoid 7813954Sgiacomo.gabrielli@arm.comLSQ::LSQRequest::disableMemAccess() 7913954Sgiacomo.gabrielli@arm.com{ 8013954Sgiacomo.gabrielli@arm.com port.cpu.threads[inst->id.threadId]->setMemAccPredicate(false); 8113954Sgiacomo.gabrielli@arm.com DPRINTFS(MinorMem, (&port), "Disable mem access for inst:%s\n", *inst); 8213954Sgiacomo.gabrielli@arm.com} 8313954Sgiacomo.gabrielli@arm.com 8410259SAndrew.Bardsley@arm.comLSQ::AddrRangeCoverage 8510259SAndrew.Bardsley@arm.comLSQ::LSQRequest::containsAddrRangeOf( 8610259SAndrew.Bardsley@arm.com Addr req1_addr, unsigned int req1_size, 8710259SAndrew.Bardsley@arm.com Addr req2_addr, unsigned int req2_size) 8810259SAndrew.Bardsley@arm.com{ 8910259SAndrew.Bardsley@arm.com /* 'end' here means the address of the byte just past the request 9010259SAndrew.Bardsley@arm.com * blocks */ 9110259SAndrew.Bardsley@arm.com Addr req2_end_addr = req2_addr + req2_size; 9210259SAndrew.Bardsley@arm.com Addr req1_end_addr = req1_addr + req1_size; 9310259SAndrew.Bardsley@arm.com 9410259SAndrew.Bardsley@arm.com AddrRangeCoverage ret; 9510259SAndrew.Bardsley@arm.com 9612179Spau.cabre@metempsy.com if (req1_addr >= req2_end_addr || req1_end_addr <= req2_addr) 9710259SAndrew.Bardsley@arm.com ret = NoAddrRangeCoverage; 9810259SAndrew.Bardsley@arm.com else if (req1_addr <= req2_addr && req1_end_addr >= req2_end_addr) 9910259SAndrew.Bardsley@arm.com ret = FullAddrRangeCoverage; 10010259SAndrew.Bardsley@arm.com else 10110259SAndrew.Bardsley@arm.com ret = PartialAddrRangeCoverage; 10210259SAndrew.Bardsley@arm.com 10310259SAndrew.Bardsley@arm.com return ret; 10410259SAndrew.Bardsley@arm.com} 10510259SAndrew.Bardsley@arm.com 10610259SAndrew.Bardsley@arm.comLSQ::AddrRangeCoverage 10710259SAndrew.Bardsley@arm.comLSQ::LSQRequest::containsAddrRangeOf(LSQRequestPtr other_request) 10810259SAndrew.Bardsley@arm.com{ 10912749Sgiacomo.travaglini@arm.com return containsAddrRangeOf(request->getPaddr(), request->getSize(), 11012749Sgiacomo.travaglini@arm.com other_request->request->getPaddr(), other_request->request->getSize()); 11110259SAndrew.Bardsley@arm.com} 11210259SAndrew.Bardsley@arm.com 11310259SAndrew.Bardsley@arm.combool 11410259SAndrew.Bardsley@arm.comLSQ::LSQRequest::isBarrier() 11510259SAndrew.Bardsley@arm.com{ 11610259SAndrew.Bardsley@arm.com return inst->isInst() && inst->staticInst->isMemBarrier(); 11710259SAndrew.Bardsley@arm.com} 11810259SAndrew.Bardsley@arm.com 11910259SAndrew.Bardsley@arm.combool 12010259SAndrew.Bardsley@arm.comLSQ::LSQRequest::needsToBeSentToStoreBuffer() 12110259SAndrew.Bardsley@arm.com{ 12210259SAndrew.Bardsley@arm.com return state == StoreToStoreBuffer; 12310259SAndrew.Bardsley@arm.com} 12410259SAndrew.Bardsley@arm.com 12510259SAndrew.Bardsley@arm.comvoid 12610259SAndrew.Bardsley@arm.comLSQ::LSQRequest::setState(LSQRequestState new_state) 12710259SAndrew.Bardsley@arm.com{ 12810259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Setting state from %d to %d for request:" 12910259SAndrew.Bardsley@arm.com " %s\n", state, new_state, *inst); 13010259SAndrew.Bardsley@arm.com state = new_state; 13110259SAndrew.Bardsley@arm.com} 13210259SAndrew.Bardsley@arm.com 13310259SAndrew.Bardsley@arm.combool 13410259SAndrew.Bardsley@arm.comLSQ::LSQRequest::isComplete() const 13510259SAndrew.Bardsley@arm.com{ 13610259SAndrew.Bardsley@arm.com /* @todo, There is currently only one 'completed' state. This 13710259SAndrew.Bardsley@arm.com * may not be a good choice */ 13810259SAndrew.Bardsley@arm.com return state == Complete; 13910259SAndrew.Bardsley@arm.com} 14010259SAndrew.Bardsley@arm.com 14110259SAndrew.Bardsley@arm.comvoid 14210259SAndrew.Bardsley@arm.comLSQ::LSQRequest::reportData(std::ostream &os) const 14310259SAndrew.Bardsley@arm.com{ 14410259SAndrew.Bardsley@arm.com os << (isLoad ? 'R' : 'W') << ';'; 14510259SAndrew.Bardsley@arm.com inst->reportData(os); 14610259SAndrew.Bardsley@arm.com os << ';' << state; 14710259SAndrew.Bardsley@arm.com} 14810259SAndrew.Bardsley@arm.com 14910259SAndrew.Bardsley@arm.comstd::ostream & 15010259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, LSQ::AddrRangeCoverage coverage) 15110259SAndrew.Bardsley@arm.com{ 15210259SAndrew.Bardsley@arm.com switch (coverage) { 15310259SAndrew.Bardsley@arm.com case LSQ::PartialAddrRangeCoverage: 15410259SAndrew.Bardsley@arm.com os << "PartialAddrRangeCoverage"; 15510259SAndrew.Bardsley@arm.com break; 15610259SAndrew.Bardsley@arm.com case LSQ::FullAddrRangeCoverage: 15710259SAndrew.Bardsley@arm.com os << "FullAddrRangeCoverage"; 15810259SAndrew.Bardsley@arm.com break; 15910259SAndrew.Bardsley@arm.com case LSQ::NoAddrRangeCoverage: 16010259SAndrew.Bardsley@arm.com os << "NoAddrRangeCoverage"; 16110259SAndrew.Bardsley@arm.com break; 16210259SAndrew.Bardsley@arm.com default: 16310259SAndrew.Bardsley@arm.com os << "AddrRangeCoverage-" << static_cast<int>(coverage); 16410259SAndrew.Bardsley@arm.com break; 16510259SAndrew.Bardsley@arm.com } 16610259SAndrew.Bardsley@arm.com return os; 16710259SAndrew.Bardsley@arm.com} 16810259SAndrew.Bardsley@arm.com 16910259SAndrew.Bardsley@arm.comstd::ostream & 17010259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, LSQ::LSQRequest::LSQRequestState state) 17110259SAndrew.Bardsley@arm.com{ 17210259SAndrew.Bardsley@arm.com switch (state) { 17310259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::NotIssued: 17410259SAndrew.Bardsley@arm.com os << "NotIssued"; 17510259SAndrew.Bardsley@arm.com break; 17610259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::InTranslation: 17710259SAndrew.Bardsley@arm.com os << "InTranslation"; 17810259SAndrew.Bardsley@arm.com break; 17910259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::Translated: 18010259SAndrew.Bardsley@arm.com os << "Translated"; 18110259SAndrew.Bardsley@arm.com break; 18210259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::Failed: 18310259SAndrew.Bardsley@arm.com os << "Failed"; 18410259SAndrew.Bardsley@arm.com break; 18510259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::RequestIssuing: 18610259SAndrew.Bardsley@arm.com os << "RequestIssuing"; 18710259SAndrew.Bardsley@arm.com break; 18810259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreToStoreBuffer: 18910259SAndrew.Bardsley@arm.com os << "StoreToStoreBuffer"; 19010259SAndrew.Bardsley@arm.com break; 19110259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreInStoreBuffer: 19210259SAndrew.Bardsley@arm.com os << "StoreInStoreBuffer"; 19310259SAndrew.Bardsley@arm.com break; 19410259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreBufferIssuing: 19510259SAndrew.Bardsley@arm.com os << "StoreBufferIssuing"; 19610259SAndrew.Bardsley@arm.com break; 19710259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::RequestNeedsRetry: 19810259SAndrew.Bardsley@arm.com os << "RequestNeedsRetry"; 19910259SAndrew.Bardsley@arm.com break; 20010259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreBufferNeedsRetry: 20110259SAndrew.Bardsley@arm.com os << "StoreBufferNeedsRetry"; 20210259SAndrew.Bardsley@arm.com break; 20310259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::Complete: 20410259SAndrew.Bardsley@arm.com os << "Complete"; 20510259SAndrew.Bardsley@arm.com break; 20610259SAndrew.Bardsley@arm.com default: 20710259SAndrew.Bardsley@arm.com os << "LSQRequestState-" << static_cast<int>(state); 20810259SAndrew.Bardsley@arm.com break; 20910259SAndrew.Bardsley@arm.com } 21010259SAndrew.Bardsley@arm.com return os; 21110259SAndrew.Bardsley@arm.com} 21210259SAndrew.Bardsley@arm.com 21310259SAndrew.Bardsley@arm.comvoid 21410259SAndrew.Bardsley@arm.comLSQ::clearMemBarrier(MinorDynInstPtr inst) 21510259SAndrew.Bardsley@arm.com{ 21611567Smitch.hayenga@arm.com bool is_last_barrier = 21711567Smitch.hayenga@arm.com inst->id.execSeqNum >= lastMemBarrier[inst->id.threadId]; 21810259SAndrew.Bardsley@arm.com 21910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Moving %s barrier out of store buffer inst: %s\n", 22010259SAndrew.Bardsley@arm.com (is_last_barrier ? "last" : "a"), *inst); 22110259SAndrew.Bardsley@arm.com 22210259SAndrew.Bardsley@arm.com if (is_last_barrier) 22311567Smitch.hayenga@arm.com lastMemBarrier[inst->id.threadId] = 0; 22410259SAndrew.Bardsley@arm.com} 22510259SAndrew.Bardsley@arm.com 22610259SAndrew.Bardsley@arm.comvoid 22712749Sgiacomo.travaglini@arm.comLSQ::SingleDataRequest::finish(const Fault &fault_, const RequestPtr &request_, 22810379Sandreas.hansson@arm.com ThreadContext *tc, BaseTLB::Mode mode) 22910259SAndrew.Bardsley@arm.com{ 23010259SAndrew.Bardsley@arm.com fault = fault_; 23110259SAndrew.Bardsley@arm.com 23210259SAndrew.Bardsley@arm.com port.numAccessesInDTLB--; 23310259SAndrew.Bardsley@arm.com 23410259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Received translation response for" 23510259SAndrew.Bardsley@arm.com " request: %s\n", *inst); 23610259SAndrew.Bardsley@arm.com 23710259SAndrew.Bardsley@arm.com makePacket(); 23810259SAndrew.Bardsley@arm.com 23910259SAndrew.Bardsley@arm.com setState(Translated); 24010259SAndrew.Bardsley@arm.com port.tryToSendToTransfers(this); 24110259SAndrew.Bardsley@arm.com 24210259SAndrew.Bardsley@arm.com /* Let's try and wake up the processor for the next cycle */ 24310259SAndrew.Bardsley@arm.com port.cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 24410259SAndrew.Bardsley@arm.com} 24510259SAndrew.Bardsley@arm.com 24610259SAndrew.Bardsley@arm.comvoid 24710259SAndrew.Bardsley@arm.comLSQ::SingleDataRequest::startAddrTranslation() 24810259SAndrew.Bardsley@arm.com{ 24910259SAndrew.Bardsley@arm.com ThreadContext *thread = port.cpu.getContext( 25010259SAndrew.Bardsley@arm.com inst->id.threadId); 25110259SAndrew.Bardsley@arm.com 25213954Sgiacomo.gabrielli@arm.com const auto &byteEnable = request->getByteEnable(); 25313954Sgiacomo.gabrielli@arm.com if (byteEnable.size() == 0 || 25413954Sgiacomo.gabrielli@arm.com isAnyActiveElement(byteEnable.cbegin(), byteEnable.cend())) { 25513954Sgiacomo.gabrielli@arm.com port.numAccessesInDTLB++; 25610259SAndrew.Bardsley@arm.com 25713954Sgiacomo.gabrielli@arm.com setState(LSQ::LSQRequest::InTranslation); 25810259SAndrew.Bardsley@arm.com 25913954Sgiacomo.gabrielli@arm.com DPRINTFS(MinorMem, (&port), "Submitting DTLB request\n"); 26013954Sgiacomo.gabrielli@arm.com /* Submit the translation request. The response will come through 26113954Sgiacomo.gabrielli@arm.com * finish/markDelayed on the LSQRequest as it bears the Translation 26213954Sgiacomo.gabrielli@arm.com * interface */ 26313954Sgiacomo.gabrielli@arm.com thread->getDTBPtr()->translateTiming( 26413954Sgiacomo.gabrielli@arm.com request, thread, this, (isLoad ? BaseTLB::Read : BaseTLB::Write)); 26513954Sgiacomo.gabrielli@arm.com } else { 26613954Sgiacomo.gabrielli@arm.com disableMemAccess(); 26713954Sgiacomo.gabrielli@arm.com setState(LSQ::LSQRequest::Complete); 26813954Sgiacomo.gabrielli@arm.com } 26910259SAndrew.Bardsley@arm.com} 27010259SAndrew.Bardsley@arm.com 27110259SAndrew.Bardsley@arm.comvoid 27210259SAndrew.Bardsley@arm.comLSQ::SingleDataRequest::retireResponse(PacketPtr packet_) 27310259SAndrew.Bardsley@arm.com{ 27410259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Retiring packet\n"); 27510259SAndrew.Bardsley@arm.com packet = packet_; 27610259SAndrew.Bardsley@arm.com packetInFlight = false; 27710259SAndrew.Bardsley@arm.com setState(Complete); 27810259SAndrew.Bardsley@arm.com} 27910259SAndrew.Bardsley@arm.com 28010259SAndrew.Bardsley@arm.comvoid 28112749Sgiacomo.travaglini@arm.comLSQ::SplitDataRequest::finish(const Fault &fault_, const RequestPtr &request_, 28210379Sandreas.hansson@arm.com ThreadContext *tc, BaseTLB::Mode mode) 28310259SAndrew.Bardsley@arm.com{ 28410259SAndrew.Bardsley@arm.com fault = fault_; 28510259SAndrew.Bardsley@arm.com 28610259SAndrew.Bardsley@arm.com port.numAccessesInDTLB--; 28710259SAndrew.Bardsley@arm.com 28810259SAndrew.Bardsley@arm.com unsigned int M5_VAR_USED expected_fragment_index = 28910259SAndrew.Bardsley@arm.com numTranslatedFragments; 29010259SAndrew.Bardsley@arm.com 29110259SAndrew.Bardsley@arm.com numInTranslationFragments--; 29210259SAndrew.Bardsley@arm.com numTranslatedFragments++; 29310259SAndrew.Bardsley@arm.com 29410259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Received translation response for fragment" 29510259SAndrew.Bardsley@arm.com " %d of request: %s\n", expected_fragment_index, *inst); 29610259SAndrew.Bardsley@arm.com 29710259SAndrew.Bardsley@arm.com assert(request_ == fragmentRequests[expected_fragment_index]); 29810259SAndrew.Bardsley@arm.com 29910259SAndrew.Bardsley@arm.com /* Wake up next cycle to get things going again in case the 30010259SAndrew.Bardsley@arm.com * tryToSendToTransfers does take */ 30110259SAndrew.Bardsley@arm.com port.cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 30210259SAndrew.Bardsley@arm.com 30310259SAndrew.Bardsley@arm.com if (fault != NoFault) { 30410259SAndrew.Bardsley@arm.com /* tryToSendToTransfers will handle the fault */ 30510259SAndrew.Bardsley@arm.com 30610259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Faulting translation for fragment:" 30710259SAndrew.Bardsley@arm.com " %d of request: %s\n", 30810259SAndrew.Bardsley@arm.com expected_fragment_index, *inst); 30910259SAndrew.Bardsley@arm.com 31010259SAndrew.Bardsley@arm.com setState(Translated); 31110259SAndrew.Bardsley@arm.com port.tryToSendToTransfers(this); 31210259SAndrew.Bardsley@arm.com } else if (numTranslatedFragments == numFragments) { 31310259SAndrew.Bardsley@arm.com makeFragmentPackets(); 31410259SAndrew.Bardsley@arm.com 31510259SAndrew.Bardsley@arm.com setState(Translated); 31610259SAndrew.Bardsley@arm.com port.tryToSendToTransfers(this); 31710259SAndrew.Bardsley@arm.com } else { 31810259SAndrew.Bardsley@arm.com /* Avoid calling translateTiming from within ::finish */ 31910259SAndrew.Bardsley@arm.com assert(!translationEvent.scheduled()); 32010259SAndrew.Bardsley@arm.com port.cpu.schedule(translationEvent, curTick()); 32110259SAndrew.Bardsley@arm.com } 32210259SAndrew.Bardsley@arm.com} 32310259SAndrew.Bardsley@arm.com 32410259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_, 32510259SAndrew.Bardsley@arm.com bool isLoad_, PacketDataPtr data_, uint64_t *res_) : 32610259SAndrew.Bardsley@arm.com LSQRequest(port_, inst_, isLoad_, data_, res_), 32712127Sspwilson2@wisc.edu translationEvent([this]{ sendNextFragmentToTranslation(); }, 32812127Sspwilson2@wisc.edu "translationEvent"), 32910259SAndrew.Bardsley@arm.com numFragments(0), 33010259SAndrew.Bardsley@arm.com numInTranslationFragments(0), 33110259SAndrew.Bardsley@arm.com numTranslatedFragments(0), 33210259SAndrew.Bardsley@arm.com numIssuedFragments(0), 33310259SAndrew.Bardsley@arm.com numRetiredFragments(0), 33410259SAndrew.Bardsley@arm.com fragmentRequests(), 33510259SAndrew.Bardsley@arm.com fragmentPackets() 33610259SAndrew.Bardsley@arm.com{ 33710259SAndrew.Bardsley@arm.com /* Don't know how many elements are needed until the request is 33810259SAndrew.Bardsley@arm.com * populated by the caller. */ 33910259SAndrew.Bardsley@arm.com} 34010259SAndrew.Bardsley@arm.com 34110259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::~SplitDataRequest() 34210259SAndrew.Bardsley@arm.com{ 34310259SAndrew.Bardsley@arm.com for (auto i = fragmentPackets.begin(); 34410259SAndrew.Bardsley@arm.com i != fragmentPackets.end(); i++) 34510259SAndrew.Bardsley@arm.com { 34610259SAndrew.Bardsley@arm.com delete *i; 34710259SAndrew.Bardsley@arm.com } 34810259SAndrew.Bardsley@arm.com} 34910259SAndrew.Bardsley@arm.com 35010259SAndrew.Bardsley@arm.comvoid 35110259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::makeFragmentRequests() 35210259SAndrew.Bardsley@arm.com{ 35312749Sgiacomo.travaglini@arm.com Addr base_addr = request->getVaddr(); 35412749Sgiacomo.travaglini@arm.com unsigned int whole_size = request->getSize(); 35510259SAndrew.Bardsley@arm.com unsigned int line_width = port.lineWidth; 35610259SAndrew.Bardsley@arm.com 35710259SAndrew.Bardsley@arm.com unsigned int fragment_size; 35810259SAndrew.Bardsley@arm.com Addr fragment_addr; 35910259SAndrew.Bardsley@arm.com 36013954Sgiacomo.gabrielli@arm.com std::vector<bool> fragment_write_byte_en; 36113954Sgiacomo.gabrielli@arm.com 36210259SAndrew.Bardsley@arm.com /* Assume that this transfer is across potentially many block snap 36310259SAndrew.Bardsley@arm.com * boundaries: 36410259SAndrew.Bardsley@arm.com * 36510259SAndrew.Bardsley@arm.com * | _|________|________|________|___ | 36610259SAndrew.Bardsley@arm.com * | |0| 1 | 2 | 3 | 4 | | 36710259SAndrew.Bardsley@arm.com * | |_|________|________|________|___| | 36810259SAndrew.Bardsley@arm.com * | | | | | | 36910259SAndrew.Bardsley@arm.com * 37010259SAndrew.Bardsley@arm.com * The first transfer (0) can be up to lineWidth in size. 37110259SAndrew.Bardsley@arm.com * All the middle transfers (1-3) are lineWidth in size 37210259SAndrew.Bardsley@arm.com * The last transfer (4) can be from zero to lineWidth - 1 in size 37310259SAndrew.Bardsley@arm.com */ 37410259SAndrew.Bardsley@arm.com unsigned int first_fragment_offset = 37510259SAndrew.Bardsley@arm.com addrBlockOffset(base_addr, line_width); 37610259SAndrew.Bardsley@arm.com unsigned int last_fragment_size = 37710259SAndrew.Bardsley@arm.com addrBlockOffset(base_addr + whole_size, line_width); 37810259SAndrew.Bardsley@arm.com unsigned int first_fragment_size = 37910259SAndrew.Bardsley@arm.com line_width - first_fragment_offset; 38010259SAndrew.Bardsley@arm.com 38110259SAndrew.Bardsley@arm.com unsigned int middle_fragments_total_size = 38210259SAndrew.Bardsley@arm.com whole_size - (first_fragment_size + last_fragment_size); 38310259SAndrew.Bardsley@arm.com 38410259SAndrew.Bardsley@arm.com assert(addrBlockOffset(middle_fragments_total_size, line_width) == 0); 38510259SAndrew.Bardsley@arm.com 38610259SAndrew.Bardsley@arm.com unsigned int middle_fragment_count = 38710259SAndrew.Bardsley@arm.com middle_fragments_total_size / line_width; 38810259SAndrew.Bardsley@arm.com 38910259SAndrew.Bardsley@arm.com numFragments = 1 /* first */ + middle_fragment_count + 39010259SAndrew.Bardsley@arm.com (last_fragment_size == 0 ? 0 : 1); 39110259SAndrew.Bardsley@arm.com 39210259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Dividing transfer into %d fragmentRequests." 39310259SAndrew.Bardsley@arm.com " First fragment size: %d Last fragment size: %d\n", 39410259SAndrew.Bardsley@arm.com numFragments, first_fragment_size, 39510259SAndrew.Bardsley@arm.com (last_fragment_size == 0 ? line_width : last_fragment_size)); 39610259SAndrew.Bardsley@arm.com 39710259SAndrew.Bardsley@arm.com assert(((middle_fragment_count * line_width) + 39810259SAndrew.Bardsley@arm.com first_fragment_size + last_fragment_size) == whole_size); 39910259SAndrew.Bardsley@arm.com 40010259SAndrew.Bardsley@arm.com fragment_addr = base_addr; 40110259SAndrew.Bardsley@arm.com fragment_size = first_fragment_size; 40210259SAndrew.Bardsley@arm.com 40310259SAndrew.Bardsley@arm.com /* Just past the last address in the request */ 40410259SAndrew.Bardsley@arm.com Addr end_addr = base_addr + whole_size; 40510259SAndrew.Bardsley@arm.com 40613954Sgiacomo.gabrielli@arm.com auto& byte_enable = request->getByteEnable(); 40713954Sgiacomo.gabrielli@arm.com unsigned int num_disabled_fragments = 0; 40813954Sgiacomo.gabrielli@arm.com 40910259SAndrew.Bardsley@arm.com for (unsigned int fragment_index = 0; fragment_index < numFragments; 41010259SAndrew.Bardsley@arm.com fragment_index++) 41110259SAndrew.Bardsley@arm.com { 41210259SAndrew.Bardsley@arm.com bool M5_VAR_USED is_last_fragment = false; 41310259SAndrew.Bardsley@arm.com 41410259SAndrew.Bardsley@arm.com if (fragment_addr == base_addr) { 41510259SAndrew.Bardsley@arm.com /* First fragment */ 41610259SAndrew.Bardsley@arm.com fragment_size = first_fragment_size; 41710259SAndrew.Bardsley@arm.com } else { 41810259SAndrew.Bardsley@arm.com if ((fragment_addr + line_width) > end_addr) { 41910259SAndrew.Bardsley@arm.com /* Adjust size of last fragment */ 42010259SAndrew.Bardsley@arm.com fragment_size = end_addr - fragment_addr; 42110259SAndrew.Bardsley@arm.com is_last_fragment = true; 42210259SAndrew.Bardsley@arm.com } else { 42310259SAndrew.Bardsley@arm.com /* Middle fragments */ 42410259SAndrew.Bardsley@arm.com fragment_size = line_width; 42510259SAndrew.Bardsley@arm.com } 42610259SAndrew.Bardsley@arm.com } 42710259SAndrew.Bardsley@arm.com 42812749Sgiacomo.travaglini@arm.com RequestPtr fragment = std::make_shared<Request>(); 42913954Sgiacomo.gabrielli@arm.com bool disabled_fragment = false; 43010259SAndrew.Bardsley@arm.com 43112749Sgiacomo.travaglini@arm.com fragment->setContext(request->contextId()); 43213954Sgiacomo.gabrielli@arm.com if (byte_enable.empty()) { 43313954Sgiacomo.gabrielli@arm.com fragment->setVirt(0 /* asid */, 43413954Sgiacomo.gabrielli@arm.com fragment_addr, fragment_size, request->getFlags(), 43513954Sgiacomo.gabrielli@arm.com request->masterId(), 43613954Sgiacomo.gabrielli@arm.com request->getPC()); 43713954Sgiacomo.gabrielli@arm.com } else { 43813954Sgiacomo.gabrielli@arm.com // Set up byte-enable mask for the current fragment 43913954Sgiacomo.gabrielli@arm.com auto it_start = byte_enable.begin() + 44013954Sgiacomo.gabrielli@arm.com (fragment_addr - base_addr); 44113954Sgiacomo.gabrielli@arm.com auto it_end = byte_enable.begin() + 44213954Sgiacomo.gabrielli@arm.com (fragment_addr - base_addr) + fragment_size; 44313954Sgiacomo.gabrielli@arm.com if (isAnyActiveElement(it_start, it_end)) { 44413954Sgiacomo.gabrielli@arm.com fragment->setVirt(0 /* asid */, 44513954Sgiacomo.gabrielli@arm.com fragment_addr, fragment_size, request->getFlags(), 44613954Sgiacomo.gabrielli@arm.com request->masterId(), 44713954Sgiacomo.gabrielli@arm.com request->getPC()); 44813954Sgiacomo.gabrielli@arm.com fragment->setByteEnable(std::vector<bool>(it_start, it_end)); 44913954Sgiacomo.gabrielli@arm.com } else { 45013954Sgiacomo.gabrielli@arm.com disabled_fragment = true; 45113954Sgiacomo.gabrielli@arm.com } 45213954Sgiacomo.gabrielli@arm.com } 45310259SAndrew.Bardsley@arm.com 45413954Sgiacomo.gabrielli@arm.com if (!disabled_fragment) { 45513954Sgiacomo.gabrielli@arm.com DPRINTFS(MinorMem, (&port), "Generating fragment addr: 0x%x" 45613954Sgiacomo.gabrielli@arm.com " size: %d (whole request addr: 0x%x size: %d) %s\n", 45713954Sgiacomo.gabrielli@arm.com fragment_addr, fragment_size, base_addr, whole_size, 45813954Sgiacomo.gabrielli@arm.com (is_last_fragment ? "last fragment" : "")); 45913954Sgiacomo.gabrielli@arm.com 46013954Sgiacomo.gabrielli@arm.com fragmentRequests.push_back(fragment); 46113954Sgiacomo.gabrielli@arm.com } else { 46213954Sgiacomo.gabrielli@arm.com num_disabled_fragments++; 46313954Sgiacomo.gabrielli@arm.com } 46410259SAndrew.Bardsley@arm.com 46510259SAndrew.Bardsley@arm.com fragment_addr += fragment_size; 46610259SAndrew.Bardsley@arm.com } 46713954Sgiacomo.gabrielli@arm.com assert(numFragments >= num_disabled_fragments); 46813954Sgiacomo.gabrielli@arm.com numFragments -= num_disabled_fragments; 46910259SAndrew.Bardsley@arm.com} 47010259SAndrew.Bardsley@arm.com 47110259SAndrew.Bardsley@arm.comvoid 47210259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::makeFragmentPackets() 47310259SAndrew.Bardsley@arm.com{ 47413954Sgiacomo.gabrielli@arm.com assert(numTranslatedFragments > 0); 47512749Sgiacomo.travaglini@arm.com Addr base_addr = request->getVaddr(); 47610259SAndrew.Bardsley@arm.com 47710259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Making packets for request: %s\n", *inst); 47810259SAndrew.Bardsley@arm.com 47913954Sgiacomo.gabrielli@arm.com for (unsigned int fragment_index = 0; 48013954Sgiacomo.gabrielli@arm.com fragment_index < numTranslatedFragments; 48110259SAndrew.Bardsley@arm.com fragment_index++) 48210259SAndrew.Bardsley@arm.com { 48312748Sgiacomo.travaglini@arm.com RequestPtr fragment = fragmentRequests[fragment_index]; 48410259SAndrew.Bardsley@arm.com 48510259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Making packet %d for request: %s" 48610259SAndrew.Bardsley@arm.com " (%d, 0x%x)\n", 48710259SAndrew.Bardsley@arm.com fragment_index, *inst, 48810259SAndrew.Bardsley@arm.com (fragment->hasPaddr() ? "has paddr" : "no paddr"), 48910259SAndrew.Bardsley@arm.com (fragment->hasPaddr() ? fragment->getPaddr() : 0)); 49010259SAndrew.Bardsley@arm.com 49110259SAndrew.Bardsley@arm.com Addr fragment_addr = fragment->getVaddr(); 49210259SAndrew.Bardsley@arm.com unsigned int fragment_size = fragment->getSize(); 49310259SAndrew.Bardsley@arm.com 49410259SAndrew.Bardsley@arm.com uint8_t *request_data = NULL; 49510259SAndrew.Bardsley@arm.com 49610259SAndrew.Bardsley@arm.com if (!isLoad) { 49710259SAndrew.Bardsley@arm.com /* Split data for Packets. Will become the property of the 49810259SAndrew.Bardsley@arm.com * outgoing Packets */ 49910259SAndrew.Bardsley@arm.com request_data = new uint8_t[fragment_size]; 50010259SAndrew.Bardsley@arm.com std::memcpy(request_data, data + (fragment_addr - base_addr), 50110259SAndrew.Bardsley@arm.com fragment_size); 50210259SAndrew.Bardsley@arm.com } 50310259SAndrew.Bardsley@arm.com 50410259SAndrew.Bardsley@arm.com assert(fragment->hasPaddr()); 50510259SAndrew.Bardsley@arm.com 50610259SAndrew.Bardsley@arm.com PacketPtr fragment_packet = 50712749Sgiacomo.travaglini@arm.com makePacketForRequest(fragment, isLoad, this, request_data); 50810259SAndrew.Bardsley@arm.com 50910259SAndrew.Bardsley@arm.com fragmentPackets.push_back(fragment_packet); 51010368SAndrew.Bardsley@arm.com /* Accumulate flags in parent request */ 51112749Sgiacomo.travaglini@arm.com request->setFlags(fragment->getFlags()); 51210259SAndrew.Bardsley@arm.com } 51310259SAndrew.Bardsley@arm.com 51410259SAndrew.Bardsley@arm.com /* Might as well make the overall/response packet here */ 51510259SAndrew.Bardsley@arm.com /* Get the physical address for the whole request/packet from the first 51610259SAndrew.Bardsley@arm.com * fragment */ 51712749Sgiacomo.travaglini@arm.com request->setPaddr(fragmentRequests[0]->getPaddr()); 51810259SAndrew.Bardsley@arm.com makePacket(); 51910259SAndrew.Bardsley@arm.com} 52010259SAndrew.Bardsley@arm.com 52110259SAndrew.Bardsley@arm.comvoid 52210259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::startAddrTranslation() 52310259SAndrew.Bardsley@arm.com{ 52410259SAndrew.Bardsley@arm.com makeFragmentRequests(); 52510259SAndrew.Bardsley@arm.com 52613954Sgiacomo.gabrielli@arm.com if (numFragments > 0) { 52713954Sgiacomo.gabrielli@arm.com setState(LSQ::LSQRequest::InTranslation); 52813954Sgiacomo.gabrielli@arm.com numInTranslationFragments = 0; 52913954Sgiacomo.gabrielli@arm.com numTranslatedFragments = 0; 53010259SAndrew.Bardsley@arm.com 53113954Sgiacomo.gabrielli@arm.com /* @todo, just do these in sequence for now with 53213954Sgiacomo.gabrielli@arm.com * a loop of: 53313954Sgiacomo.gabrielli@arm.com * do { 53413954Sgiacomo.gabrielli@arm.com * sendNextFragmentToTranslation ; translateTiming ; finish 53513954Sgiacomo.gabrielli@arm.com * } while (numTranslatedFragments != numFragments); 53613954Sgiacomo.gabrielli@arm.com */ 53710259SAndrew.Bardsley@arm.com 53813954Sgiacomo.gabrielli@arm.com /* Do first translation */ 53913954Sgiacomo.gabrielli@arm.com sendNextFragmentToTranslation(); 54013954Sgiacomo.gabrielli@arm.com } else { 54113954Sgiacomo.gabrielli@arm.com disableMemAccess(); 54213954Sgiacomo.gabrielli@arm.com setState(LSQ::LSQRequest::Complete); 54313954Sgiacomo.gabrielli@arm.com } 54410259SAndrew.Bardsley@arm.com} 54510259SAndrew.Bardsley@arm.com 54610259SAndrew.Bardsley@arm.comPacketPtr 54710259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::getHeadPacket() 54810259SAndrew.Bardsley@arm.com{ 54913954Sgiacomo.gabrielli@arm.com assert(numIssuedFragments < numTranslatedFragments); 55010259SAndrew.Bardsley@arm.com 55110259SAndrew.Bardsley@arm.com return fragmentPackets[numIssuedFragments]; 55210259SAndrew.Bardsley@arm.com} 55310259SAndrew.Bardsley@arm.com 55410259SAndrew.Bardsley@arm.comvoid 55510259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::stepToNextPacket() 55610259SAndrew.Bardsley@arm.com{ 55713954Sgiacomo.gabrielli@arm.com assert(numIssuedFragments < numTranslatedFragments); 55810259SAndrew.Bardsley@arm.com 55910259SAndrew.Bardsley@arm.com numIssuedFragments++; 56010259SAndrew.Bardsley@arm.com} 56110259SAndrew.Bardsley@arm.com 56210259SAndrew.Bardsley@arm.comvoid 56310259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::retireResponse(PacketPtr response) 56410259SAndrew.Bardsley@arm.com{ 56513954Sgiacomo.gabrielli@arm.com assert(numRetiredFragments < numTranslatedFragments); 56610259SAndrew.Bardsley@arm.com 56710259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Retiring fragment addr: 0x%x size: %d" 56813954Sgiacomo.gabrielli@arm.com " offset: 0x%x (retired fragment num: %d)\n", 56910259SAndrew.Bardsley@arm.com response->req->getVaddr(), response->req->getSize(), 57012749Sgiacomo.travaglini@arm.com request->getVaddr() - response->req->getVaddr(), 57113954Sgiacomo.gabrielli@arm.com numRetiredFragments); 57210259SAndrew.Bardsley@arm.com 57310259SAndrew.Bardsley@arm.com numRetiredFragments++; 57410259SAndrew.Bardsley@arm.com 57510259SAndrew.Bardsley@arm.com if (skipped) { 57610259SAndrew.Bardsley@arm.com /* Skip because we already knew the request had faulted or been 57710259SAndrew.Bardsley@arm.com * skipped */ 57810259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Skipping this fragment\n"); 57910259SAndrew.Bardsley@arm.com } else if (response->isError()) { 58010259SAndrew.Bardsley@arm.com /* Mark up the error and leave to execute to handle it */ 58110259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Fragment has an error, skipping\n"); 58210259SAndrew.Bardsley@arm.com setSkipped(); 58310259SAndrew.Bardsley@arm.com packet->copyError(response); 58410259SAndrew.Bardsley@arm.com } else { 58510259SAndrew.Bardsley@arm.com if (isLoad) { 58610259SAndrew.Bardsley@arm.com if (!data) { 58710259SAndrew.Bardsley@arm.com /* For a split transfer, a Packet must be constructed 58810259SAndrew.Bardsley@arm.com * to contain all returning data. This is that packet's 58910259SAndrew.Bardsley@arm.com * data */ 59012749Sgiacomo.travaglini@arm.com data = new uint8_t[request->getSize()]; 59110259SAndrew.Bardsley@arm.com } 59210259SAndrew.Bardsley@arm.com 59310259SAndrew.Bardsley@arm.com /* Populate the portion of the overall response data represented 59410259SAndrew.Bardsley@arm.com * by the response fragment */ 59510259SAndrew.Bardsley@arm.com std::memcpy( 59612749Sgiacomo.travaglini@arm.com data + (response->req->getVaddr() - request->getVaddr()), 59710563Sandreas.hansson@arm.com response->getConstPtr<uint8_t>(), 59810259SAndrew.Bardsley@arm.com response->req->getSize()); 59910259SAndrew.Bardsley@arm.com } 60010259SAndrew.Bardsley@arm.com } 60110259SAndrew.Bardsley@arm.com 60210259SAndrew.Bardsley@arm.com /* Complete early if we're skipping are no more in-flight accesses */ 60310259SAndrew.Bardsley@arm.com if (skipped && !hasPacketsInMemSystem()) { 60410259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Completed skipped burst\n"); 60510259SAndrew.Bardsley@arm.com setState(Complete); 60610259SAndrew.Bardsley@arm.com if (packet->needsResponse()) 60710259SAndrew.Bardsley@arm.com packet->makeResponse(); 60810259SAndrew.Bardsley@arm.com } 60910259SAndrew.Bardsley@arm.com 61013954Sgiacomo.gabrielli@arm.com if (numRetiredFragments == numTranslatedFragments) 61110259SAndrew.Bardsley@arm.com setState(Complete); 61210259SAndrew.Bardsley@arm.com 61310259SAndrew.Bardsley@arm.com if (!skipped && isComplete()) { 61410259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Completed burst %d\n", packet != NULL); 61510259SAndrew.Bardsley@arm.com 61610259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Retired packet isRead: %d isWrite: %d" 61710259SAndrew.Bardsley@arm.com " needsResponse: %d packetSize: %s requestSize: %s responseSize:" 61810259SAndrew.Bardsley@arm.com " %s\n", packet->isRead(), packet->isWrite(), 61912749Sgiacomo.travaglini@arm.com packet->needsResponse(), packet->getSize(), request->getSize(), 62010259SAndrew.Bardsley@arm.com response->getSize()); 62110259SAndrew.Bardsley@arm.com 62210259SAndrew.Bardsley@arm.com /* A request can become complete by several paths, this is a sanity 62310259SAndrew.Bardsley@arm.com * check to make sure the packet's data is created */ 62410259SAndrew.Bardsley@arm.com if (!data) { 62512749Sgiacomo.travaglini@arm.com data = new uint8_t[request->getSize()]; 62610259SAndrew.Bardsley@arm.com } 62710259SAndrew.Bardsley@arm.com 62810259SAndrew.Bardsley@arm.com if (isLoad) { 62910259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Copying read data\n"); 63012749Sgiacomo.travaglini@arm.com std::memcpy(packet->getPtr<uint8_t>(), data, request->getSize()); 63110259SAndrew.Bardsley@arm.com } 63210259SAndrew.Bardsley@arm.com packet->makeResponse(); 63310259SAndrew.Bardsley@arm.com } 63410259SAndrew.Bardsley@arm.com 63510259SAndrew.Bardsley@arm.com /* Packets are all deallocated together in ~SplitLSQRequest */ 63610259SAndrew.Bardsley@arm.com} 63710259SAndrew.Bardsley@arm.com 63810259SAndrew.Bardsley@arm.comvoid 63910259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::sendNextFragmentToTranslation() 64010259SAndrew.Bardsley@arm.com{ 64110259SAndrew.Bardsley@arm.com unsigned int fragment_index = numTranslatedFragments; 64210259SAndrew.Bardsley@arm.com 64310259SAndrew.Bardsley@arm.com ThreadContext *thread = port.cpu.getContext( 64410259SAndrew.Bardsley@arm.com inst->id.threadId); 64510259SAndrew.Bardsley@arm.com 64610259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Submitting DTLB request for fragment: %d\n", 64710259SAndrew.Bardsley@arm.com fragment_index); 64810259SAndrew.Bardsley@arm.com 64910259SAndrew.Bardsley@arm.com port.numAccessesInDTLB++; 65010259SAndrew.Bardsley@arm.com numInTranslationFragments++; 65110259SAndrew.Bardsley@arm.com 65210259SAndrew.Bardsley@arm.com thread->getDTBPtr()->translateTiming( 65310259SAndrew.Bardsley@arm.com fragmentRequests[fragment_index], thread, this, (isLoad ? 65410259SAndrew.Bardsley@arm.com BaseTLB::Read : BaseTLB::Write)); 65510259SAndrew.Bardsley@arm.com} 65610259SAndrew.Bardsley@arm.com 65710259SAndrew.Bardsley@arm.combool 65810259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::canInsert() const 65910259SAndrew.Bardsley@arm.com{ 66010259SAndrew.Bardsley@arm.com /* @todo, support store amalgamation */ 66110259SAndrew.Bardsley@arm.com return slots.size() < numSlots; 66210259SAndrew.Bardsley@arm.com} 66310259SAndrew.Bardsley@arm.com 66410259SAndrew.Bardsley@arm.comvoid 66510259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::deleteRequest(LSQRequestPtr request) 66610259SAndrew.Bardsley@arm.com{ 66710259SAndrew.Bardsley@arm.com auto found = std::find(slots.begin(), slots.end(), request); 66810259SAndrew.Bardsley@arm.com 66910259SAndrew.Bardsley@arm.com if (found != slots.end()) { 67010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Deleting request: %s %s %s from StoreBuffer\n", 67110259SAndrew.Bardsley@arm.com request, *found, *(request->inst)); 67210259SAndrew.Bardsley@arm.com slots.erase(found); 67310259SAndrew.Bardsley@arm.com 67410259SAndrew.Bardsley@arm.com delete request; 67510259SAndrew.Bardsley@arm.com } 67610259SAndrew.Bardsley@arm.com} 67710259SAndrew.Bardsley@arm.com 67810259SAndrew.Bardsley@arm.comvoid 67910259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::insert(LSQRequestPtr request) 68010259SAndrew.Bardsley@arm.com{ 68110259SAndrew.Bardsley@arm.com if (!canInsert()) { 68210259SAndrew.Bardsley@arm.com warn("%s: store buffer insertion without space to insert from" 68310259SAndrew.Bardsley@arm.com " inst: %s\n", name(), *(request->inst)); 68410259SAndrew.Bardsley@arm.com } 68510259SAndrew.Bardsley@arm.com 68610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Pushing store: %s into store buffer\n", request); 68710259SAndrew.Bardsley@arm.com 68810259SAndrew.Bardsley@arm.com numUnissuedAccesses++; 68910259SAndrew.Bardsley@arm.com 69010259SAndrew.Bardsley@arm.com if (request->state != LSQRequest::Complete) 69110259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreInStoreBuffer); 69210259SAndrew.Bardsley@arm.com 69310259SAndrew.Bardsley@arm.com slots.push_back(request); 69410259SAndrew.Bardsley@arm.com 69510259SAndrew.Bardsley@arm.com /* Let's try and wake up the processor for the next cycle to step 69610259SAndrew.Bardsley@arm.com * the store buffer */ 69710259SAndrew.Bardsley@arm.com lsq.cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 69810259SAndrew.Bardsley@arm.com} 69910259SAndrew.Bardsley@arm.com 70010259SAndrew.Bardsley@arm.comLSQ::AddrRangeCoverage 70110259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::canForwardDataToLoad(LSQRequestPtr request, 70210259SAndrew.Bardsley@arm.com unsigned int &found_slot) 70310259SAndrew.Bardsley@arm.com{ 70410259SAndrew.Bardsley@arm.com unsigned int slot_index = slots.size() - 1; 70510259SAndrew.Bardsley@arm.com auto i = slots.rbegin(); 70610259SAndrew.Bardsley@arm.com AddrRangeCoverage ret = NoAddrRangeCoverage; 70710259SAndrew.Bardsley@arm.com 70810259SAndrew.Bardsley@arm.com /* Traverse the store buffer in reverse order (most to least recent) 70910259SAndrew.Bardsley@arm.com * and try to find a slot whose address range overlaps this request */ 71010259SAndrew.Bardsley@arm.com while (ret == NoAddrRangeCoverage && i != slots.rend()) { 71110259SAndrew.Bardsley@arm.com LSQRequestPtr slot = *i; 71210259SAndrew.Bardsley@arm.com 71313652Sqtt2@cornell.edu /* Cache maintenance instructions go down via the store path but 71413652Sqtt2@cornell.edu * they carry no data and they shouldn't be considered 71513652Sqtt2@cornell.edu * for forwarding */ 71611567Smitch.hayenga@arm.com if (slot->packet && 71712355Snikos.nikoleris@arm.com slot->inst->id.threadId == request->inst->id.threadId && 71812355Snikos.nikoleris@arm.com !slot->packet->req->isCacheMaintenance()) { 71910259SAndrew.Bardsley@arm.com AddrRangeCoverage coverage = slot->containsAddrRangeOf(request); 72010259SAndrew.Bardsley@arm.com 72110259SAndrew.Bardsley@arm.com if (coverage != NoAddrRangeCoverage) { 72210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Forwarding: slot: %d result: %s thisAddr:" 72310259SAndrew.Bardsley@arm.com " 0x%x thisSize: %d slotAddr: 0x%x slotSize: %d\n", 72410259SAndrew.Bardsley@arm.com slot_index, coverage, 72512749Sgiacomo.travaglini@arm.com request->request->getPaddr(), request->request->getSize(), 72612749Sgiacomo.travaglini@arm.com slot->request->getPaddr(), slot->request->getSize()); 72710259SAndrew.Bardsley@arm.com 72810259SAndrew.Bardsley@arm.com found_slot = slot_index; 72910259SAndrew.Bardsley@arm.com ret = coverage; 73010259SAndrew.Bardsley@arm.com } 73110259SAndrew.Bardsley@arm.com } 73210259SAndrew.Bardsley@arm.com 73310259SAndrew.Bardsley@arm.com i++; 73410259SAndrew.Bardsley@arm.com slot_index--; 73510259SAndrew.Bardsley@arm.com } 73610259SAndrew.Bardsley@arm.com 73710259SAndrew.Bardsley@arm.com return ret; 73810259SAndrew.Bardsley@arm.com} 73910259SAndrew.Bardsley@arm.com 74010259SAndrew.Bardsley@arm.com/** Fill the given packet with appropriate date from slot slot_number */ 74110259SAndrew.Bardsley@arm.comvoid 74210259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::forwardStoreData(LSQRequestPtr load, 74310259SAndrew.Bardsley@arm.com unsigned int slot_number) 74410259SAndrew.Bardsley@arm.com{ 74510259SAndrew.Bardsley@arm.com assert(slot_number < slots.size()); 74610259SAndrew.Bardsley@arm.com assert(load->packet); 74710259SAndrew.Bardsley@arm.com assert(load->isLoad); 74810259SAndrew.Bardsley@arm.com 74910259SAndrew.Bardsley@arm.com LSQRequestPtr store = slots[slot_number]; 75010259SAndrew.Bardsley@arm.com 75110259SAndrew.Bardsley@arm.com assert(store->packet); 75210259SAndrew.Bardsley@arm.com assert(store->containsAddrRangeOf(load) == FullAddrRangeCoverage); 75310259SAndrew.Bardsley@arm.com 75412749Sgiacomo.travaglini@arm.com Addr load_addr = load->request->getPaddr(); 75512749Sgiacomo.travaglini@arm.com Addr store_addr = store->request->getPaddr(); 75610259SAndrew.Bardsley@arm.com Addr addr_offset = load_addr - store_addr; 75710259SAndrew.Bardsley@arm.com 75812749Sgiacomo.travaglini@arm.com unsigned int load_size = load->request->getSize(); 75910259SAndrew.Bardsley@arm.com 76010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Forwarding %d bytes for addr: 0x%x from store buffer" 76110259SAndrew.Bardsley@arm.com " slot: %d addr: 0x%x addressOffset: 0x%x\n", 76210259SAndrew.Bardsley@arm.com load_size, load_addr, slot_number, 76310259SAndrew.Bardsley@arm.com store_addr, addr_offset); 76410259SAndrew.Bardsley@arm.com 76510259SAndrew.Bardsley@arm.com void *load_packet_data = load->packet->getPtr<void>(); 76610259SAndrew.Bardsley@arm.com void *store_packet_data = store->packet->getPtr<uint8_t>() + addr_offset; 76710259SAndrew.Bardsley@arm.com 76810259SAndrew.Bardsley@arm.com std::memcpy(load_packet_data, store_packet_data, load_size); 76910259SAndrew.Bardsley@arm.com} 77010259SAndrew.Bardsley@arm.com 77110259SAndrew.Bardsley@arm.comvoid 77210581SAndrew.Bardsley@arm.comLSQ::StoreBuffer::countIssuedStore(LSQRequestPtr request) 77310581SAndrew.Bardsley@arm.com{ 77410581SAndrew.Bardsley@arm.com /* Barriers are accounted for as they are cleared from 77510581SAndrew.Bardsley@arm.com * the queue, not after their transfers are complete */ 77610581SAndrew.Bardsley@arm.com if (!request->isBarrier()) 77710581SAndrew.Bardsley@arm.com numUnissuedAccesses--; 77810581SAndrew.Bardsley@arm.com} 77910581SAndrew.Bardsley@arm.com 78010581SAndrew.Bardsley@arm.comvoid 78110259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::step() 78210259SAndrew.Bardsley@arm.com{ 78310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "StoreBuffer step numUnissuedAccesses: %d\n", 78410259SAndrew.Bardsley@arm.com numUnissuedAccesses); 78510259SAndrew.Bardsley@arm.com 78610259SAndrew.Bardsley@arm.com if (numUnissuedAccesses != 0 && lsq.state == LSQ::MemoryRunning) { 78710259SAndrew.Bardsley@arm.com /* Clear all the leading barriers */ 78810259SAndrew.Bardsley@arm.com while (!slots.empty() && 78910259SAndrew.Bardsley@arm.com slots.front()->isComplete() && slots.front()->isBarrier()) 79010259SAndrew.Bardsley@arm.com { 79110259SAndrew.Bardsley@arm.com LSQRequestPtr barrier = slots.front(); 79210259SAndrew.Bardsley@arm.com 79310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Clearing barrier for inst: %s\n", 79410259SAndrew.Bardsley@arm.com *(barrier->inst)); 79510259SAndrew.Bardsley@arm.com 79610259SAndrew.Bardsley@arm.com numUnissuedAccesses--; 79710259SAndrew.Bardsley@arm.com lsq.clearMemBarrier(barrier->inst); 79810259SAndrew.Bardsley@arm.com slots.pop_front(); 79910259SAndrew.Bardsley@arm.com 80010259SAndrew.Bardsley@arm.com delete barrier; 80110259SAndrew.Bardsley@arm.com } 80210259SAndrew.Bardsley@arm.com 80310259SAndrew.Bardsley@arm.com auto i = slots.begin(); 80410259SAndrew.Bardsley@arm.com bool issued = true; 80510259SAndrew.Bardsley@arm.com unsigned int issue_count = 0; 80610259SAndrew.Bardsley@arm.com 80710259SAndrew.Bardsley@arm.com /* Skip trying if the memory system is busy */ 80810259SAndrew.Bardsley@arm.com if (lsq.state == LSQ::MemoryNeedsRetry) 80910259SAndrew.Bardsley@arm.com issued = false; 81010259SAndrew.Bardsley@arm.com 81110259SAndrew.Bardsley@arm.com /* Try to issue all stores in order starting from the head 81210259SAndrew.Bardsley@arm.com * of the queue. Responses are allowed to be retired 81310259SAndrew.Bardsley@arm.com * out of order */ 81410259SAndrew.Bardsley@arm.com while (issued && 81510259SAndrew.Bardsley@arm.com issue_count < storeLimitPerCycle && 81610259SAndrew.Bardsley@arm.com lsq.canSendToMemorySystem() && 81710259SAndrew.Bardsley@arm.com i != slots.end()) 81810259SAndrew.Bardsley@arm.com { 81910259SAndrew.Bardsley@arm.com LSQRequestPtr request = *i; 82010259SAndrew.Bardsley@arm.com 82110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Considering request: %s, sentAllPackets: %d" 82210259SAndrew.Bardsley@arm.com " state: %s\n", 82310259SAndrew.Bardsley@arm.com *(request->inst), request->sentAllPackets(), 82410259SAndrew.Bardsley@arm.com request->state); 82510259SAndrew.Bardsley@arm.com 82610259SAndrew.Bardsley@arm.com if (request->isBarrier() && request->isComplete()) { 82710259SAndrew.Bardsley@arm.com /* Give up at barriers */ 82810259SAndrew.Bardsley@arm.com issued = false; 82910259SAndrew.Bardsley@arm.com } else if (!(request->state == LSQRequest::StoreBufferIssuing && 83010259SAndrew.Bardsley@arm.com request->sentAllPackets())) 83110259SAndrew.Bardsley@arm.com { 83210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Trying to send request: %s to memory" 83310259SAndrew.Bardsley@arm.com " system\n", *(request->inst)); 83410259SAndrew.Bardsley@arm.com 83510259SAndrew.Bardsley@arm.com if (lsq.tryToSend(request)) { 83610581SAndrew.Bardsley@arm.com countIssuedStore(request); 83710259SAndrew.Bardsley@arm.com issue_count++; 83810259SAndrew.Bardsley@arm.com } else { 83910259SAndrew.Bardsley@arm.com /* Don't step on to the next store buffer entry if this 84010259SAndrew.Bardsley@arm.com * one hasn't issued all its packets as the store 84110259SAndrew.Bardsley@arm.com * buffer must still enforce ordering */ 84210259SAndrew.Bardsley@arm.com issued = false; 84310259SAndrew.Bardsley@arm.com } 84410259SAndrew.Bardsley@arm.com } 84510259SAndrew.Bardsley@arm.com i++; 84610259SAndrew.Bardsley@arm.com } 84710259SAndrew.Bardsley@arm.com } 84810259SAndrew.Bardsley@arm.com} 84910259SAndrew.Bardsley@arm.com 85010259SAndrew.Bardsley@arm.comvoid 85110259SAndrew.Bardsley@arm.comLSQ::completeMemBarrierInst(MinorDynInstPtr inst, 85210259SAndrew.Bardsley@arm.com bool committed) 85310259SAndrew.Bardsley@arm.com{ 85410259SAndrew.Bardsley@arm.com if (committed) { 85510259SAndrew.Bardsley@arm.com /* Not already sent to the store buffer as a store request? */ 85610259SAndrew.Bardsley@arm.com if (!inst->inStoreBuffer) { 85710259SAndrew.Bardsley@arm.com /* Insert an entry into the store buffer to tick off barriers 85810259SAndrew.Bardsley@arm.com * until there are none in flight */ 85910259SAndrew.Bardsley@arm.com storeBuffer.insert(new BarrierDataRequest(*this, inst)); 86010259SAndrew.Bardsley@arm.com } 86110259SAndrew.Bardsley@arm.com } else { 86210259SAndrew.Bardsley@arm.com /* Clear the barrier anyway if it wasn't actually committed */ 86310259SAndrew.Bardsley@arm.com clearMemBarrier(inst); 86410259SAndrew.Bardsley@arm.com } 86510259SAndrew.Bardsley@arm.com} 86610259SAndrew.Bardsley@arm.com 86710259SAndrew.Bardsley@arm.comvoid 86810259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::minorTrace() const 86910259SAndrew.Bardsley@arm.com{ 87010259SAndrew.Bardsley@arm.com unsigned int size = slots.size(); 87110259SAndrew.Bardsley@arm.com unsigned int i = 0; 87210259SAndrew.Bardsley@arm.com std::ostringstream os; 87310259SAndrew.Bardsley@arm.com 87410259SAndrew.Bardsley@arm.com while (i < size) { 87510259SAndrew.Bardsley@arm.com LSQRequestPtr request = slots[i]; 87610259SAndrew.Bardsley@arm.com 87710259SAndrew.Bardsley@arm.com request->reportData(os); 87810259SAndrew.Bardsley@arm.com 87910259SAndrew.Bardsley@arm.com i++; 88010259SAndrew.Bardsley@arm.com if (i < numSlots) 88110259SAndrew.Bardsley@arm.com os << ','; 88210259SAndrew.Bardsley@arm.com } 88310259SAndrew.Bardsley@arm.com 88410259SAndrew.Bardsley@arm.com while (i < numSlots) { 88510259SAndrew.Bardsley@arm.com os << '-'; 88610259SAndrew.Bardsley@arm.com 88710259SAndrew.Bardsley@arm.com i++; 88810259SAndrew.Bardsley@arm.com if (i < numSlots) 88910259SAndrew.Bardsley@arm.com os << ','; 89010259SAndrew.Bardsley@arm.com } 89110259SAndrew.Bardsley@arm.com 89210259SAndrew.Bardsley@arm.com MINORTRACE("addr=%s num_unissued_stores=%d\n", os.str(), 89310259SAndrew.Bardsley@arm.com numUnissuedAccesses); 89410259SAndrew.Bardsley@arm.com} 89510259SAndrew.Bardsley@arm.com 89610259SAndrew.Bardsley@arm.comvoid 89710259SAndrew.Bardsley@arm.comLSQ::tryToSendToTransfers(LSQRequestPtr request) 89810259SAndrew.Bardsley@arm.com{ 89910259SAndrew.Bardsley@arm.com if (state == MemoryNeedsRetry) { 90010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request needs retry, not issuing to" 90110259SAndrew.Bardsley@arm.com " memory until retry arrives\n"); 90210259SAndrew.Bardsley@arm.com return; 90310259SAndrew.Bardsley@arm.com } 90410259SAndrew.Bardsley@arm.com 90510259SAndrew.Bardsley@arm.com if (request->state == LSQRequest::InTranslation) { 90610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request still in translation, not issuing to" 90710259SAndrew.Bardsley@arm.com " memory\n"); 90810259SAndrew.Bardsley@arm.com return; 90910259SAndrew.Bardsley@arm.com } 91010259SAndrew.Bardsley@arm.com 91110259SAndrew.Bardsley@arm.com assert(request->state == LSQRequest::Translated || 91210259SAndrew.Bardsley@arm.com request->state == LSQRequest::RequestIssuing || 91310259SAndrew.Bardsley@arm.com request->state == LSQRequest::Failed || 91410259SAndrew.Bardsley@arm.com request->state == LSQRequest::Complete); 91510259SAndrew.Bardsley@arm.com 91610259SAndrew.Bardsley@arm.com if (requests.empty() || requests.front() != request) { 91710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request not at front of requests queue, can't" 91810259SAndrew.Bardsley@arm.com " issue to memory\n"); 91910259SAndrew.Bardsley@arm.com return; 92010259SAndrew.Bardsley@arm.com } 92110259SAndrew.Bardsley@arm.com 92210259SAndrew.Bardsley@arm.com if (transfers.unreservedRemainingSpace() == 0) { 92310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "No space to insert request into transfers" 92410259SAndrew.Bardsley@arm.com " queue\n"); 92510259SAndrew.Bardsley@arm.com return; 92610259SAndrew.Bardsley@arm.com } 92710259SAndrew.Bardsley@arm.com 92810259SAndrew.Bardsley@arm.com if (request->isComplete() || request->state == LSQRequest::Failed) { 92910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Passing a %s transfer on to transfers" 93010259SAndrew.Bardsley@arm.com " queue\n", (request->isComplete() ? "completed" : "failed")); 93110259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 93210259SAndrew.Bardsley@arm.com request->setSkipped(); 93310259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 93410259SAndrew.Bardsley@arm.com return; 93510259SAndrew.Bardsley@arm.com } 93610259SAndrew.Bardsley@arm.com 93710259SAndrew.Bardsley@arm.com if (!execute.instIsRightStream(request->inst)) { 93810259SAndrew.Bardsley@arm.com /* Wrong stream, try to abort the transfer but only do so if 93910259SAndrew.Bardsley@arm.com * there are no packets in flight */ 94010259SAndrew.Bardsley@arm.com if (request->hasPacketsInMemSystem()) { 94110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request's inst. is from the wrong stream," 94210259SAndrew.Bardsley@arm.com " waiting for responses before aborting request\n"); 94310259SAndrew.Bardsley@arm.com } else { 94410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request's inst. is from the wrong stream," 94510259SAndrew.Bardsley@arm.com " aborting request\n"); 94610259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 94710259SAndrew.Bardsley@arm.com request->setSkipped(); 94810259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 94910259SAndrew.Bardsley@arm.com } 95010259SAndrew.Bardsley@arm.com return; 95110259SAndrew.Bardsley@arm.com } 95210259SAndrew.Bardsley@arm.com 95310259SAndrew.Bardsley@arm.com if (request->fault != NoFault) { 95410259SAndrew.Bardsley@arm.com if (request->inst->staticInst->isPrefetch()) { 95510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Not signalling fault for faulting prefetch\n"); 95610259SAndrew.Bardsley@arm.com } 95710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Moving faulting request into the transfers" 95810259SAndrew.Bardsley@arm.com " queue\n"); 95910259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 96010259SAndrew.Bardsley@arm.com request->setSkipped(); 96110259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 96210259SAndrew.Bardsley@arm.com return; 96310259SAndrew.Bardsley@arm.com } 96410259SAndrew.Bardsley@arm.com 96510259SAndrew.Bardsley@arm.com bool is_load = request->isLoad; 96612749Sgiacomo.travaglini@arm.com bool is_llsc = request->request->isLLSC(); 96712749Sgiacomo.travaglini@arm.com bool is_swap = request->request->isSwap(); 96813652Sqtt2@cornell.edu bool is_atomic = request->request->isAtomic(); 96912749Sgiacomo.travaglini@arm.com bool bufferable = !(request->request->isStrictlyOrdered() || 97013652Sqtt2@cornell.edu is_llsc || is_swap || is_atomic); 97110259SAndrew.Bardsley@arm.com 97210259SAndrew.Bardsley@arm.com if (is_load) { 97310259SAndrew.Bardsley@arm.com if (numStoresInTransfers != 0) { 97410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Load request with stores still in transfers" 97510259SAndrew.Bardsley@arm.com " queue, stalling\n"); 97610259SAndrew.Bardsley@arm.com return; 97710259SAndrew.Bardsley@arm.com } 97810259SAndrew.Bardsley@arm.com } else { 97910259SAndrew.Bardsley@arm.com /* Store. Can it be sent to the store buffer? */ 98012749Sgiacomo.travaglini@arm.com if (bufferable && !request->request->isMmappedIpr()) { 98110259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreToStoreBuffer); 98210259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 98310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Moving store into transfers queue\n"); 98410259SAndrew.Bardsley@arm.com return; 98510259SAndrew.Bardsley@arm.com } 98610259SAndrew.Bardsley@arm.com } 98710259SAndrew.Bardsley@arm.com 98810259SAndrew.Bardsley@arm.com /* Check if this is the head instruction (and so must be executable as 98910259SAndrew.Bardsley@arm.com * its stream sequence number was checked above) for loads which must 99010259SAndrew.Bardsley@arm.com * not be speculatively issued and stores which must be issued here */ 99110259SAndrew.Bardsley@arm.com if (!bufferable) { 99210259SAndrew.Bardsley@arm.com if (!execute.instIsHeadInst(request->inst)) { 99310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Memory access not the head inst., can't be" 99410259SAndrew.Bardsley@arm.com " sure it can be performed, not issuing\n"); 99510259SAndrew.Bardsley@arm.com return; 99610259SAndrew.Bardsley@arm.com } 99710259SAndrew.Bardsley@arm.com 99810259SAndrew.Bardsley@arm.com unsigned int forwarding_slot = 0; 99910259SAndrew.Bardsley@arm.com 100010259SAndrew.Bardsley@arm.com if (storeBuffer.canForwardDataToLoad(request, forwarding_slot) != 100110259SAndrew.Bardsley@arm.com NoAddrRangeCoverage) 100210259SAndrew.Bardsley@arm.com { 100313652Sqtt2@cornell.edu // There's at least another request that targets the same 100413652Sqtt2@cornell.edu // address and is staying in the storeBuffer. Since our 100513652Sqtt2@cornell.edu // request is non-bufferable (e.g., strictly ordered or atomic), 100613652Sqtt2@cornell.edu // we must wait for the other request in the storeBuffer to 100713652Sqtt2@cornell.edu // complete before we can issue this non-bufferable request. 100813652Sqtt2@cornell.edu // This is to make sure that the order they access the cache is 100913652Sqtt2@cornell.edu // correct. 101010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Memory access can receive forwarded data" 101113652Sqtt2@cornell.edu " from the store buffer, but need to wait for store buffer" 101213652Sqtt2@cornell.edu " to drain\n"); 101310259SAndrew.Bardsley@arm.com return; 101410259SAndrew.Bardsley@arm.com } 101510259SAndrew.Bardsley@arm.com } 101610259SAndrew.Bardsley@arm.com 101710259SAndrew.Bardsley@arm.com /* True: submit this packet to the transfers queue to be sent to the 101810259SAndrew.Bardsley@arm.com * memory system. 101910259SAndrew.Bardsley@arm.com * False: skip the memory and push a packet for this request onto 102010259SAndrew.Bardsley@arm.com * requests */ 102110259SAndrew.Bardsley@arm.com bool do_access = true; 102210259SAndrew.Bardsley@arm.com 102310259SAndrew.Bardsley@arm.com if (!is_llsc) { 102410259SAndrew.Bardsley@arm.com /* Check for match in the store buffer */ 102510259SAndrew.Bardsley@arm.com if (is_load) { 102610259SAndrew.Bardsley@arm.com unsigned int forwarding_slot = 0; 102710259SAndrew.Bardsley@arm.com AddrRangeCoverage forwarding_result = 102810259SAndrew.Bardsley@arm.com storeBuffer.canForwardDataToLoad(request, 102910259SAndrew.Bardsley@arm.com forwarding_slot); 103010259SAndrew.Bardsley@arm.com 103110259SAndrew.Bardsley@arm.com switch (forwarding_result) { 103210259SAndrew.Bardsley@arm.com case FullAddrRangeCoverage: 103310259SAndrew.Bardsley@arm.com /* Forward data from the store buffer into this request and 103410259SAndrew.Bardsley@arm.com * repurpose this request's packet into a response packet */ 103510259SAndrew.Bardsley@arm.com storeBuffer.forwardStoreData(request, forwarding_slot); 103610259SAndrew.Bardsley@arm.com request->packet->makeResponse(); 103710259SAndrew.Bardsley@arm.com 103810259SAndrew.Bardsley@arm.com /* Just move between queues, no access */ 103910259SAndrew.Bardsley@arm.com do_access = false; 104010259SAndrew.Bardsley@arm.com break; 104110259SAndrew.Bardsley@arm.com case PartialAddrRangeCoverage: 104210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Load partly satisfied by store buffer" 104310259SAndrew.Bardsley@arm.com " data. Must wait for the store to complete\n"); 104410259SAndrew.Bardsley@arm.com return; 104510259SAndrew.Bardsley@arm.com break; 104610259SAndrew.Bardsley@arm.com case NoAddrRangeCoverage: 104710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "No forwardable data from store buffer\n"); 104810259SAndrew.Bardsley@arm.com /* Fall through to try access */ 104910259SAndrew.Bardsley@arm.com break; 105010259SAndrew.Bardsley@arm.com } 105110259SAndrew.Bardsley@arm.com } 105210259SAndrew.Bardsley@arm.com } else { 105310259SAndrew.Bardsley@arm.com if (!canSendToMemorySystem()) { 105410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Can't send request to memory system yet\n"); 105510259SAndrew.Bardsley@arm.com return; 105610259SAndrew.Bardsley@arm.com } 105710259SAndrew.Bardsley@arm.com 105810259SAndrew.Bardsley@arm.com SimpleThread &thread = *cpu.threads[request->inst->id.threadId]; 105910259SAndrew.Bardsley@arm.com 106010259SAndrew.Bardsley@arm.com TheISA::PCState old_pc = thread.pcState(); 106110259SAndrew.Bardsley@arm.com ExecContext context(cpu, thread, execute, request->inst); 106210259SAndrew.Bardsley@arm.com 106310259SAndrew.Bardsley@arm.com /* Handle LLSC requests and tests */ 106410259SAndrew.Bardsley@arm.com if (is_load) { 106512749Sgiacomo.travaglini@arm.com TheISA::handleLockedRead(&context, request->request); 106610259SAndrew.Bardsley@arm.com } else { 106710259SAndrew.Bardsley@arm.com do_access = TheISA::handleLockedWrite(&context, 106812749Sgiacomo.travaglini@arm.com request->request, cacheBlockMask); 106910259SAndrew.Bardsley@arm.com 107010259SAndrew.Bardsley@arm.com if (!do_access) { 107110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Not perfoming a memory " 107210259SAndrew.Bardsley@arm.com "access for store conditional\n"); 107310259SAndrew.Bardsley@arm.com } 107410259SAndrew.Bardsley@arm.com } 107510259SAndrew.Bardsley@arm.com thread.pcState(old_pc); 107610259SAndrew.Bardsley@arm.com } 107710259SAndrew.Bardsley@arm.com 107810259SAndrew.Bardsley@arm.com /* See the do_access comment above */ 107910259SAndrew.Bardsley@arm.com if (do_access) { 108010259SAndrew.Bardsley@arm.com if (!canSendToMemorySystem()) { 108110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Can't send request to memory system yet\n"); 108210259SAndrew.Bardsley@arm.com return; 108310259SAndrew.Bardsley@arm.com } 108410259SAndrew.Bardsley@arm.com 108510259SAndrew.Bardsley@arm.com /* Remember if this is an access which can't be idly 108610259SAndrew.Bardsley@arm.com * discarded by an interrupt */ 108710368SAndrew.Bardsley@arm.com if (!bufferable && !request->issuedToMemory) { 108810259SAndrew.Bardsley@arm.com numAccessesIssuedToMemory++; 108910259SAndrew.Bardsley@arm.com request->issuedToMemory = true; 109010259SAndrew.Bardsley@arm.com } 109110259SAndrew.Bardsley@arm.com 109211567Smitch.hayenga@arm.com if (tryToSend(request)) { 109310259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 109411567Smitch.hayenga@arm.com } 109510259SAndrew.Bardsley@arm.com } else { 109610259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 109710259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 109810259SAndrew.Bardsley@arm.com } 109910259SAndrew.Bardsley@arm.com} 110010259SAndrew.Bardsley@arm.com 110110259SAndrew.Bardsley@arm.combool 110210259SAndrew.Bardsley@arm.comLSQ::tryToSend(LSQRequestPtr request) 110310259SAndrew.Bardsley@arm.com{ 110410259SAndrew.Bardsley@arm.com bool ret = false; 110510259SAndrew.Bardsley@arm.com 110610259SAndrew.Bardsley@arm.com if (!canSendToMemorySystem()) { 110710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Can't send request: %s yet, no space in memory\n", 110810259SAndrew.Bardsley@arm.com *(request->inst)); 110910259SAndrew.Bardsley@arm.com } else { 111010259SAndrew.Bardsley@arm.com PacketPtr packet = request->getHeadPacket(); 111110259SAndrew.Bardsley@arm.com 111210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Trying to send request: %s addr: 0x%x\n", 111310259SAndrew.Bardsley@arm.com *(request->inst), packet->req->getVaddr()); 111410259SAndrew.Bardsley@arm.com 111510259SAndrew.Bardsley@arm.com /* The sender state of the packet *must* be an LSQRequest 111610259SAndrew.Bardsley@arm.com * so the response can be correctly handled */ 111710259SAndrew.Bardsley@arm.com assert(packet->findNextSenderState<LSQRequest>()); 111810259SAndrew.Bardsley@arm.com 111912749Sgiacomo.travaglini@arm.com if (request->request->isMmappedIpr()) { 112010259SAndrew.Bardsley@arm.com ThreadContext *thread = 112111435Smitch.hayenga@arm.com cpu.getContext(cpu.contextToThread( 112212749Sgiacomo.travaglini@arm.com request->request->contextId())); 112310259SAndrew.Bardsley@arm.com 112410259SAndrew.Bardsley@arm.com if (request->isLoad) { 112510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "IPR read inst: %s\n", *(request->inst)); 112610259SAndrew.Bardsley@arm.com TheISA::handleIprRead(thread, packet); 112710259SAndrew.Bardsley@arm.com } else { 112810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "IPR write inst: %s\n", *(request->inst)); 112910259SAndrew.Bardsley@arm.com TheISA::handleIprWrite(thread, packet); 113010259SAndrew.Bardsley@arm.com } 113110259SAndrew.Bardsley@arm.com 113210259SAndrew.Bardsley@arm.com request->stepToNextPacket(); 113310259SAndrew.Bardsley@arm.com ret = request->sentAllPackets(); 113410259SAndrew.Bardsley@arm.com 113510259SAndrew.Bardsley@arm.com if (!ret) { 113610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "IPR access has another packet: %s\n", 113710259SAndrew.Bardsley@arm.com *(request->inst)); 113810259SAndrew.Bardsley@arm.com } 113910259SAndrew.Bardsley@arm.com 114010259SAndrew.Bardsley@arm.com if (ret) 114110259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 114210259SAndrew.Bardsley@arm.com else 114310259SAndrew.Bardsley@arm.com request->setState(LSQRequest::RequestIssuing); 114410259SAndrew.Bardsley@arm.com } else if (dcachePort.sendTimingReq(packet)) { 114510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Sent data memory request\n"); 114610259SAndrew.Bardsley@arm.com 114710259SAndrew.Bardsley@arm.com numAccessesInMemorySystem++; 114810259SAndrew.Bardsley@arm.com 114910259SAndrew.Bardsley@arm.com request->stepToNextPacket(); 115010259SAndrew.Bardsley@arm.com 115110259SAndrew.Bardsley@arm.com ret = request->sentAllPackets(); 115210259SAndrew.Bardsley@arm.com 115310259SAndrew.Bardsley@arm.com switch (request->state) { 115410259SAndrew.Bardsley@arm.com case LSQRequest::Translated: 115510259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 115610259SAndrew.Bardsley@arm.com /* Fully or partially issued a request in the transfers 115710259SAndrew.Bardsley@arm.com * queue */ 115810259SAndrew.Bardsley@arm.com request->setState(LSQRequest::RequestIssuing); 115910259SAndrew.Bardsley@arm.com break; 116010259SAndrew.Bardsley@arm.com case LSQRequest::StoreInStoreBuffer: 116110259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 116210259SAndrew.Bardsley@arm.com /* Fully or partially issued a request in the store 116310259SAndrew.Bardsley@arm.com * buffer */ 116410259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreBufferIssuing); 116510259SAndrew.Bardsley@arm.com break; 116610259SAndrew.Bardsley@arm.com default: 116713449Sgabeblack@google.com panic("Unrecognized LSQ request state %d.", request->state); 116810259SAndrew.Bardsley@arm.com } 116910259SAndrew.Bardsley@arm.com 117010259SAndrew.Bardsley@arm.com state = MemoryRunning; 117110259SAndrew.Bardsley@arm.com } else { 117210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, 117310259SAndrew.Bardsley@arm.com "Sending data memory request - needs retry\n"); 117410259SAndrew.Bardsley@arm.com 117510259SAndrew.Bardsley@arm.com /* Needs to be resent, wait for that */ 117610259SAndrew.Bardsley@arm.com state = MemoryNeedsRetry; 117710259SAndrew.Bardsley@arm.com retryRequest = request; 117810259SAndrew.Bardsley@arm.com 117910259SAndrew.Bardsley@arm.com switch (request->state) { 118010259SAndrew.Bardsley@arm.com case LSQRequest::Translated: 118110259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 118210259SAndrew.Bardsley@arm.com request->setState(LSQRequest::RequestNeedsRetry); 118310259SAndrew.Bardsley@arm.com break; 118410259SAndrew.Bardsley@arm.com case LSQRequest::StoreInStoreBuffer: 118510259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 118610259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreBufferNeedsRetry); 118710259SAndrew.Bardsley@arm.com break; 118810259SAndrew.Bardsley@arm.com default: 118913449Sgabeblack@google.com panic("Unrecognized LSQ request state %d.", request->state); 119010259SAndrew.Bardsley@arm.com } 119110259SAndrew.Bardsley@arm.com } 119210259SAndrew.Bardsley@arm.com } 119310259SAndrew.Bardsley@arm.com 119411567Smitch.hayenga@arm.com if (ret) 119511567Smitch.hayenga@arm.com threadSnoop(request); 119611567Smitch.hayenga@arm.com 119710259SAndrew.Bardsley@arm.com return ret; 119810259SAndrew.Bardsley@arm.com} 119910259SAndrew.Bardsley@arm.com 120010259SAndrew.Bardsley@arm.comvoid 120110259SAndrew.Bardsley@arm.comLSQ::moveFromRequestsToTransfers(LSQRequestPtr request) 120210259SAndrew.Bardsley@arm.com{ 120310259SAndrew.Bardsley@arm.com assert(!requests.empty() && requests.front() == request); 120410259SAndrew.Bardsley@arm.com assert(transfers.unreservedRemainingSpace() != 0); 120510259SAndrew.Bardsley@arm.com 120610259SAndrew.Bardsley@arm.com /* Need to count the number of stores in the transfers 120710259SAndrew.Bardsley@arm.com * queue so that loads know when their store buffer forwarding 120810259SAndrew.Bardsley@arm.com * results will be correct (only when all those stores 120910259SAndrew.Bardsley@arm.com * have reached the store buffer) */ 121010259SAndrew.Bardsley@arm.com if (!request->isLoad) 121110259SAndrew.Bardsley@arm.com numStoresInTransfers++; 121210259SAndrew.Bardsley@arm.com 121310259SAndrew.Bardsley@arm.com requests.pop(); 121410259SAndrew.Bardsley@arm.com transfers.push(request); 121510259SAndrew.Bardsley@arm.com} 121610259SAndrew.Bardsley@arm.com 121710259SAndrew.Bardsley@arm.combool 121810259SAndrew.Bardsley@arm.comLSQ::canSendToMemorySystem() 121910259SAndrew.Bardsley@arm.com{ 122010259SAndrew.Bardsley@arm.com return state == MemoryRunning && 122110259SAndrew.Bardsley@arm.com numAccessesInMemorySystem < inMemorySystemLimit; 122210259SAndrew.Bardsley@arm.com} 122310259SAndrew.Bardsley@arm.com 122410259SAndrew.Bardsley@arm.combool 122510259SAndrew.Bardsley@arm.comLSQ::recvTimingResp(PacketPtr response) 122610259SAndrew.Bardsley@arm.com{ 122710259SAndrew.Bardsley@arm.com LSQRequestPtr request = 122810259SAndrew.Bardsley@arm.com safe_cast<LSQRequestPtr>(response->popSenderState()); 122910259SAndrew.Bardsley@arm.com 123010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Received response packet inst: %s" 123110259SAndrew.Bardsley@arm.com " addr: 0x%x cmd: %s\n", 123210259SAndrew.Bardsley@arm.com *(request->inst), response->getAddr(), 123310259SAndrew.Bardsley@arm.com response->cmd.toString()); 123410259SAndrew.Bardsley@arm.com 123510259SAndrew.Bardsley@arm.com numAccessesInMemorySystem--; 123610259SAndrew.Bardsley@arm.com 123710259SAndrew.Bardsley@arm.com if (response->isError()) { 123810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Received error response packet: %s\n", 123910259SAndrew.Bardsley@arm.com *request->inst); 124010259SAndrew.Bardsley@arm.com } 124110259SAndrew.Bardsley@arm.com 124210259SAndrew.Bardsley@arm.com switch (request->state) { 124310259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 124410259SAndrew.Bardsley@arm.com case LSQRequest::RequestNeedsRetry: 124510259SAndrew.Bardsley@arm.com /* Response to a request from the transfers queue */ 124610259SAndrew.Bardsley@arm.com request->retireResponse(response); 124710259SAndrew.Bardsley@arm.com 124810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Has outstanding packets?: %d %d\n", 124910259SAndrew.Bardsley@arm.com request->hasPacketsInMemSystem(), request->isComplete()); 125010259SAndrew.Bardsley@arm.com 125110259SAndrew.Bardsley@arm.com break; 125210259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 125310259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferNeedsRetry: 125410259SAndrew.Bardsley@arm.com /* Response to a request from the store buffer */ 125510259SAndrew.Bardsley@arm.com request->retireResponse(response); 125610259SAndrew.Bardsley@arm.com 125710581SAndrew.Bardsley@arm.com /* Remove completed requests unless they are barriers (which will 125810259SAndrew.Bardsley@arm.com * need to be removed in order */ 125910259SAndrew.Bardsley@arm.com if (request->isComplete()) { 126010259SAndrew.Bardsley@arm.com if (!request->isBarrier()) { 126110259SAndrew.Bardsley@arm.com storeBuffer.deleteRequest(request); 126210259SAndrew.Bardsley@arm.com } else { 126310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Completed transfer for barrier: %s" 126410259SAndrew.Bardsley@arm.com " leaving the request as it is also a barrier\n", 126510259SAndrew.Bardsley@arm.com *(request->inst)); 126610259SAndrew.Bardsley@arm.com } 126710259SAndrew.Bardsley@arm.com } 126810259SAndrew.Bardsley@arm.com break; 126910259SAndrew.Bardsley@arm.com default: 127013449Sgabeblack@google.com panic("Shouldn't be allowed to receive a response from another state"); 127110259SAndrew.Bardsley@arm.com } 127210259SAndrew.Bardsley@arm.com 127310259SAndrew.Bardsley@arm.com /* We go to idle even if there are more things in the requests queue 127410259SAndrew.Bardsley@arm.com * as it's the job of step to actually step us on to the next 127510259SAndrew.Bardsley@arm.com * transaction */ 127610259SAndrew.Bardsley@arm.com 127710259SAndrew.Bardsley@arm.com /* Let's try and wake up the processor for the next cycle */ 127810259SAndrew.Bardsley@arm.com cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 127910259SAndrew.Bardsley@arm.com 128010259SAndrew.Bardsley@arm.com /* Never busy */ 128110259SAndrew.Bardsley@arm.com return true; 128210259SAndrew.Bardsley@arm.com} 128310259SAndrew.Bardsley@arm.com 128410259SAndrew.Bardsley@arm.comvoid 128510713Sandreas.hansson@arm.comLSQ::recvReqRetry() 128610259SAndrew.Bardsley@arm.com{ 128710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Received retry request\n"); 128810259SAndrew.Bardsley@arm.com 128910259SAndrew.Bardsley@arm.com assert(state == MemoryNeedsRetry); 129010259SAndrew.Bardsley@arm.com 129110259SAndrew.Bardsley@arm.com switch (retryRequest->state) { 129210259SAndrew.Bardsley@arm.com case LSQRequest::RequestNeedsRetry: 129310259SAndrew.Bardsley@arm.com /* Retry in the requests queue */ 129410259SAndrew.Bardsley@arm.com retryRequest->setState(LSQRequest::Translated); 129510259SAndrew.Bardsley@arm.com break; 129610259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferNeedsRetry: 129710259SAndrew.Bardsley@arm.com /* Retry in the store buffer */ 129810259SAndrew.Bardsley@arm.com retryRequest->setState(LSQRequest::StoreInStoreBuffer); 129910259SAndrew.Bardsley@arm.com break; 130010259SAndrew.Bardsley@arm.com default: 130113449Sgabeblack@google.com panic("Unrecognized retry request state %d.", retryRequest->state); 130210259SAndrew.Bardsley@arm.com } 130310259SAndrew.Bardsley@arm.com 130410259SAndrew.Bardsley@arm.com /* Set state back to MemoryRunning so that the following 130510259SAndrew.Bardsley@arm.com * tryToSend can actually send. Note that this won't 130610259SAndrew.Bardsley@arm.com * allow another transfer in as tryToSend should 130710259SAndrew.Bardsley@arm.com * issue a memory request and either succeed for this 130810259SAndrew.Bardsley@arm.com * request or return the LSQ back to MemoryNeedsRetry */ 130910259SAndrew.Bardsley@arm.com state = MemoryRunning; 131010259SAndrew.Bardsley@arm.com 131110259SAndrew.Bardsley@arm.com /* Try to resend the request */ 131210259SAndrew.Bardsley@arm.com if (tryToSend(retryRequest)) { 131310259SAndrew.Bardsley@arm.com /* Successfully sent, need to move the request */ 131410259SAndrew.Bardsley@arm.com switch (retryRequest->state) { 131510259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 131610259SAndrew.Bardsley@arm.com /* In the requests queue */ 131710259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(retryRequest); 131810259SAndrew.Bardsley@arm.com break; 131910259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 132010259SAndrew.Bardsley@arm.com /* In the store buffer */ 132110581SAndrew.Bardsley@arm.com storeBuffer.countIssuedStore(retryRequest); 132210259SAndrew.Bardsley@arm.com break; 132310259SAndrew.Bardsley@arm.com default: 132413449Sgabeblack@google.com panic("Unrecognized retry request state %d.", retryRequest->state); 132510259SAndrew.Bardsley@arm.com } 132610647Sandreas.hansson@arm.com 132710647Sandreas.hansson@arm.com retryRequest = NULL; 132810259SAndrew.Bardsley@arm.com } 132910259SAndrew.Bardsley@arm.com} 133010259SAndrew.Bardsley@arm.com 133110259SAndrew.Bardsley@arm.comLSQ::LSQ(std::string name_, std::string dcache_port_name_, 133210259SAndrew.Bardsley@arm.com MinorCPU &cpu_, Execute &execute_, 133310259SAndrew.Bardsley@arm.com unsigned int in_memory_system_limit, unsigned int line_width, 133410259SAndrew.Bardsley@arm.com unsigned int requests_queue_size, unsigned int transfers_queue_size, 133510259SAndrew.Bardsley@arm.com unsigned int store_buffer_size, 133610259SAndrew.Bardsley@arm.com unsigned int store_buffer_cycle_store_limit) : 133710259SAndrew.Bardsley@arm.com Named(name_), 133810259SAndrew.Bardsley@arm.com cpu(cpu_), 133910259SAndrew.Bardsley@arm.com execute(execute_), 134010259SAndrew.Bardsley@arm.com dcachePort(dcache_port_name_, *this, cpu_), 134111567Smitch.hayenga@arm.com lastMemBarrier(cpu.numThreads, 0), 134210259SAndrew.Bardsley@arm.com state(MemoryRunning), 134310259SAndrew.Bardsley@arm.com inMemorySystemLimit(in_memory_system_limit), 134410259SAndrew.Bardsley@arm.com lineWidth((line_width == 0 ? cpu.cacheLineSize() : line_width)), 134510259SAndrew.Bardsley@arm.com requests(name_ + ".requests", "addr", requests_queue_size), 134610259SAndrew.Bardsley@arm.com transfers(name_ + ".transfers", "addr", transfers_queue_size), 134710259SAndrew.Bardsley@arm.com storeBuffer(name_ + ".storeBuffer", 134810259SAndrew.Bardsley@arm.com *this, store_buffer_size, store_buffer_cycle_store_limit), 134910259SAndrew.Bardsley@arm.com numAccessesInMemorySystem(0), 135010259SAndrew.Bardsley@arm.com numAccessesInDTLB(0), 135110259SAndrew.Bardsley@arm.com numStoresInTransfers(0), 135210259SAndrew.Bardsley@arm.com numAccessesIssuedToMemory(0), 135310259SAndrew.Bardsley@arm.com retryRequest(NULL), 135410259SAndrew.Bardsley@arm.com cacheBlockMask(~(cpu_.cacheLineSize() - 1)) 135510259SAndrew.Bardsley@arm.com{ 135610259SAndrew.Bardsley@arm.com if (in_memory_system_limit < 1) { 135710259SAndrew.Bardsley@arm.com fatal("%s: executeMaxAccessesInMemory must be >= 1 (%d)\n", name_, 135810259SAndrew.Bardsley@arm.com in_memory_system_limit); 135910259SAndrew.Bardsley@arm.com } 136010259SAndrew.Bardsley@arm.com 136110259SAndrew.Bardsley@arm.com if (store_buffer_cycle_store_limit < 1) { 136210259SAndrew.Bardsley@arm.com fatal("%s: executeLSQMaxStoreBufferStoresPerCycle must be" 136310259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, store_buffer_cycle_store_limit); 136410259SAndrew.Bardsley@arm.com } 136510259SAndrew.Bardsley@arm.com 136610259SAndrew.Bardsley@arm.com if (requests_queue_size < 1) { 136710259SAndrew.Bardsley@arm.com fatal("%s: executeLSQRequestsQueueSize must be" 136810259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, requests_queue_size); 136910259SAndrew.Bardsley@arm.com } 137010259SAndrew.Bardsley@arm.com 137110259SAndrew.Bardsley@arm.com if (transfers_queue_size < 1) { 137210259SAndrew.Bardsley@arm.com fatal("%s: executeLSQTransfersQueueSize must be" 137310259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, transfers_queue_size); 137410259SAndrew.Bardsley@arm.com } 137510259SAndrew.Bardsley@arm.com 137610259SAndrew.Bardsley@arm.com if (store_buffer_size < 1) { 137710259SAndrew.Bardsley@arm.com fatal("%s: executeLSQStoreBufferSize must be" 137810259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, store_buffer_size); 137910259SAndrew.Bardsley@arm.com } 138010259SAndrew.Bardsley@arm.com 138110259SAndrew.Bardsley@arm.com if ((lineWidth & (lineWidth - 1)) != 0) { 138210259SAndrew.Bardsley@arm.com fatal("%s: lineWidth: %d must be a power of 2\n", name(), lineWidth); 138310259SAndrew.Bardsley@arm.com } 138410259SAndrew.Bardsley@arm.com} 138510259SAndrew.Bardsley@arm.com 138610259SAndrew.Bardsley@arm.comLSQ::~LSQ() 138710259SAndrew.Bardsley@arm.com{ } 138810259SAndrew.Bardsley@arm.com 138910259SAndrew.Bardsley@arm.comLSQ::LSQRequest::~LSQRequest() 139010259SAndrew.Bardsley@arm.com{ 139110259SAndrew.Bardsley@arm.com if (packet) 139210259SAndrew.Bardsley@arm.com delete packet; 139310259SAndrew.Bardsley@arm.com if (data) 139410259SAndrew.Bardsley@arm.com delete [] data; 139510259SAndrew.Bardsley@arm.com} 139610259SAndrew.Bardsley@arm.com 139710259SAndrew.Bardsley@arm.com/** 139810259SAndrew.Bardsley@arm.com * Step the memory access mechanism on to its next state. In reality, most 139910259SAndrew.Bardsley@arm.com * of the stepping is done by the callbacks on the LSQ but this 140010259SAndrew.Bardsley@arm.com * function is responsible for issuing memory requests lodged in the 140110259SAndrew.Bardsley@arm.com * requests queue. 140210259SAndrew.Bardsley@arm.com */ 140310259SAndrew.Bardsley@arm.comvoid 140410259SAndrew.Bardsley@arm.comLSQ::step() 140510259SAndrew.Bardsley@arm.com{ 140610259SAndrew.Bardsley@arm.com /* Try to move address-translated requests between queues and issue 140710259SAndrew.Bardsley@arm.com * them */ 140810259SAndrew.Bardsley@arm.com if (!requests.empty()) 140910259SAndrew.Bardsley@arm.com tryToSendToTransfers(requests.front()); 141010259SAndrew.Bardsley@arm.com 141110259SAndrew.Bardsley@arm.com storeBuffer.step(); 141210259SAndrew.Bardsley@arm.com} 141310259SAndrew.Bardsley@arm.com 141410259SAndrew.Bardsley@arm.comLSQ::LSQRequestPtr 141510259SAndrew.Bardsley@arm.comLSQ::findResponse(MinorDynInstPtr inst) 141610259SAndrew.Bardsley@arm.com{ 141710259SAndrew.Bardsley@arm.com LSQ::LSQRequestPtr ret = NULL; 141810259SAndrew.Bardsley@arm.com 141910259SAndrew.Bardsley@arm.com if (!transfers.empty()) { 142010259SAndrew.Bardsley@arm.com LSQRequestPtr request = transfers.front(); 142110259SAndrew.Bardsley@arm.com 142210259SAndrew.Bardsley@arm.com /* Same instruction and complete access or a store that's 142310259SAndrew.Bardsley@arm.com * capable of being moved to the store buffer */ 142410259SAndrew.Bardsley@arm.com if (request->inst->id == inst->id) { 142510504SAndrew.Bardsley@arm.com bool complete = request->isComplete(); 142610504SAndrew.Bardsley@arm.com bool can_store = storeBuffer.canInsert(); 142710504SAndrew.Bardsley@arm.com bool to_store_buffer = request->state == 142810504SAndrew.Bardsley@arm.com LSQRequest::StoreToStoreBuffer; 142910504SAndrew.Bardsley@arm.com 143010504SAndrew.Bardsley@arm.com if ((complete && !(request->isBarrier() && !can_store)) || 143110504SAndrew.Bardsley@arm.com (to_store_buffer && can_store)) 143210259SAndrew.Bardsley@arm.com { 143310259SAndrew.Bardsley@arm.com ret = request; 143410259SAndrew.Bardsley@arm.com } 143510259SAndrew.Bardsley@arm.com } 143610259SAndrew.Bardsley@arm.com } 143710259SAndrew.Bardsley@arm.com 143810259SAndrew.Bardsley@arm.com if (ret) { 143910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Found matching memory response for inst: %s\n", 144010259SAndrew.Bardsley@arm.com *inst); 144110259SAndrew.Bardsley@arm.com } else { 144210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "No matching memory response for inst: %s\n", 144310259SAndrew.Bardsley@arm.com *inst); 144410259SAndrew.Bardsley@arm.com } 144510259SAndrew.Bardsley@arm.com 144610259SAndrew.Bardsley@arm.com return ret; 144710259SAndrew.Bardsley@arm.com} 144810259SAndrew.Bardsley@arm.com 144910259SAndrew.Bardsley@arm.comvoid 145010259SAndrew.Bardsley@arm.comLSQ::popResponse(LSQ::LSQRequestPtr response) 145110259SAndrew.Bardsley@arm.com{ 145210259SAndrew.Bardsley@arm.com assert(!transfers.empty() && transfers.front() == response); 145310259SAndrew.Bardsley@arm.com 145410259SAndrew.Bardsley@arm.com transfers.pop(); 145510259SAndrew.Bardsley@arm.com 145610259SAndrew.Bardsley@arm.com if (!response->isLoad) 145710259SAndrew.Bardsley@arm.com numStoresInTransfers--; 145810259SAndrew.Bardsley@arm.com 145910259SAndrew.Bardsley@arm.com if (response->issuedToMemory) 146010259SAndrew.Bardsley@arm.com numAccessesIssuedToMemory--; 146110259SAndrew.Bardsley@arm.com 146210259SAndrew.Bardsley@arm.com if (response->state != LSQRequest::StoreInStoreBuffer) { 146310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Deleting %s request: %s\n", 146410259SAndrew.Bardsley@arm.com (response->isLoad ? "load" : "store"), 146510259SAndrew.Bardsley@arm.com *(response->inst)); 146610259SAndrew.Bardsley@arm.com 146710259SAndrew.Bardsley@arm.com delete response; 146810259SAndrew.Bardsley@arm.com } 146910259SAndrew.Bardsley@arm.com} 147010259SAndrew.Bardsley@arm.com 147110259SAndrew.Bardsley@arm.comvoid 147210259SAndrew.Bardsley@arm.comLSQ::sendStoreToStoreBuffer(LSQRequestPtr request) 147310259SAndrew.Bardsley@arm.com{ 147410259SAndrew.Bardsley@arm.com assert(request->state == LSQRequest::StoreToStoreBuffer); 147510259SAndrew.Bardsley@arm.com 147610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Sending store: %s to store buffer\n", 147710259SAndrew.Bardsley@arm.com *(request->inst)); 147810259SAndrew.Bardsley@arm.com 147910259SAndrew.Bardsley@arm.com request->inst->inStoreBuffer = true; 148010259SAndrew.Bardsley@arm.com 148110259SAndrew.Bardsley@arm.com storeBuffer.insert(request); 148210259SAndrew.Bardsley@arm.com} 148310259SAndrew.Bardsley@arm.com 148410259SAndrew.Bardsley@arm.combool 148510259SAndrew.Bardsley@arm.comLSQ::isDrained() 148610259SAndrew.Bardsley@arm.com{ 148710259SAndrew.Bardsley@arm.com return requests.empty() && transfers.empty() && 148810259SAndrew.Bardsley@arm.com storeBuffer.isDrained(); 148910259SAndrew.Bardsley@arm.com} 149010259SAndrew.Bardsley@arm.com 149110259SAndrew.Bardsley@arm.combool 149210259SAndrew.Bardsley@arm.comLSQ::needsToTick() 149310259SAndrew.Bardsley@arm.com{ 149410259SAndrew.Bardsley@arm.com bool ret = false; 149510259SAndrew.Bardsley@arm.com 149610259SAndrew.Bardsley@arm.com if (canSendToMemorySystem()) { 149710259SAndrew.Bardsley@arm.com bool have_translated_requests = !requests.empty() && 149810259SAndrew.Bardsley@arm.com requests.front()->state != LSQRequest::InTranslation && 149910259SAndrew.Bardsley@arm.com transfers.unreservedRemainingSpace() != 0; 150010259SAndrew.Bardsley@arm.com 150110259SAndrew.Bardsley@arm.com ret = have_translated_requests || 150210259SAndrew.Bardsley@arm.com storeBuffer.numUnissuedStores() != 0; 150310259SAndrew.Bardsley@arm.com } 150410259SAndrew.Bardsley@arm.com 150510259SAndrew.Bardsley@arm.com if (ret) 150610259SAndrew.Bardsley@arm.com DPRINTF(Activity, "Need to tick\n"); 150710259SAndrew.Bardsley@arm.com 150810259SAndrew.Bardsley@arm.com return ret; 150910259SAndrew.Bardsley@arm.com} 151010259SAndrew.Bardsley@arm.com 151110259SAndrew.Bardsley@arm.comvoid 151210259SAndrew.Bardsley@arm.comLSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, 151311608Snikos.nikoleris@arm.com unsigned int size, Addr addr, Request::Flags flags, 151413954Sgiacomo.gabrielli@arm.com uint64_t *res, AtomicOpFunctor *amo_op, 151513954Sgiacomo.gabrielli@arm.com const std::vector<bool>& byteEnable) 151610259SAndrew.Bardsley@arm.com{ 151710259SAndrew.Bardsley@arm.com bool needs_burst = transferNeedsBurst(addr, size, lineWidth); 151813652Sqtt2@cornell.edu 151913652Sqtt2@cornell.edu if (needs_burst && inst->staticInst->isAtomic()) { 152013652Sqtt2@cornell.edu // AMO requests that access across a cache line boundary are not 152113652Sqtt2@cornell.edu // allowed since the cache does not guarantee AMO ops to be executed 152213652Sqtt2@cornell.edu // atomically in two cache lines 152313652Sqtt2@cornell.edu // For ISAs such as x86 that requires AMO operations to work on 152413652Sqtt2@cornell.edu // accesses that cross cache-line boundaries, the cache needs to be 152513652Sqtt2@cornell.edu // modified to support locking both cache lines to guarantee the 152613652Sqtt2@cornell.edu // atomicity. 152713652Sqtt2@cornell.edu panic("Do not expect cross-cache-line atomic memory request\n"); 152813652Sqtt2@cornell.edu } 152913652Sqtt2@cornell.edu 153010259SAndrew.Bardsley@arm.com LSQRequestPtr request; 153110259SAndrew.Bardsley@arm.com 153210259SAndrew.Bardsley@arm.com /* Copy given data into the request. The request will pass this to the 153310259SAndrew.Bardsley@arm.com * packet and then it will own the data */ 153410259SAndrew.Bardsley@arm.com uint8_t *request_data = NULL; 153510259SAndrew.Bardsley@arm.com 153610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Pushing request (%s) addr: 0x%x size: %d flags:" 153710259SAndrew.Bardsley@arm.com " 0x%x%s lineWidth : 0x%x\n", 153813652Sqtt2@cornell.edu (isLoad ? "load" : "store/atomic"), addr, size, flags, 153910259SAndrew.Bardsley@arm.com (needs_burst ? " (needs burst)" : ""), lineWidth); 154010259SAndrew.Bardsley@arm.com 154110259SAndrew.Bardsley@arm.com if (!isLoad) { 154213652Sqtt2@cornell.edu /* Request_data becomes the property of a ...DataRequest (see below) 154310259SAndrew.Bardsley@arm.com * and destroyed by its destructor */ 154410259SAndrew.Bardsley@arm.com request_data = new uint8_t[size]; 154513652Sqtt2@cornell.edu if (inst->staticInst->isAtomic() || 154613652Sqtt2@cornell.edu (flags & Request::STORE_NO_DATA)) { 154713652Sqtt2@cornell.edu /* For atomic or store-no-data, just use zeroed data */ 154810259SAndrew.Bardsley@arm.com std::memset(request_data, 0, size); 154910259SAndrew.Bardsley@arm.com } else { 155010259SAndrew.Bardsley@arm.com std::memcpy(request_data, data, size); 155110259SAndrew.Bardsley@arm.com } 155210259SAndrew.Bardsley@arm.com } 155310259SAndrew.Bardsley@arm.com 155410259SAndrew.Bardsley@arm.com if (needs_burst) { 155510259SAndrew.Bardsley@arm.com request = new SplitDataRequest( 155610259SAndrew.Bardsley@arm.com *this, inst, isLoad, request_data, res); 155710259SAndrew.Bardsley@arm.com } else { 155810259SAndrew.Bardsley@arm.com request = new SingleDataRequest( 155910259SAndrew.Bardsley@arm.com *this, inst, isLoad, request_data, res); 156010259SAndrew.Bardsley@arm.com } 156110259SAndrew.Bardsley@arm.com 156210259SAndrew.Bardsley@arm.com if (inst->traceData) 156310665SAli.Saidi@ARM.com inst->traceData->setMem(addr, size, flags); 156410259SAndrew.Bardsley@arm.com 156511148Smitch.hayenga@arm.com int cid = cpu.threads[inst->id.threadId]->getTC()->contextId(); 156612749Sgiacomo.travaglini@arm.com request->request->setContext(cid); 156712749Sgiacomo.travaglini@arm.com request->request->setVirt(0 /* asid */, 156810634Slukefahr@umich.edu addr, size, flags, cpu.dataMasterId(), 156910259SAndrew.Bardsley@arm.com /* I've no idea why we need the PC, but give it */ 157013652Sqtt2@cornell.edu inst->pc.instAddr(), amo_op); 157113954Sgiacomo.gabrielli@arm.com if (!byteEnable.empty()) { 157213954Sgiacomo.gabrielli@arm.com request->request->setByteEnable(byteEnable); 157313954Sgiacomo.gabrielli@arm.com } 157410259SAndrew.Bardsley@arm.com 157510259SAndrew.Bardsley@arm.com requests.push(request); 157610259SAndrew.Bardsley@arm.com request->startAddrTranslation(); 157710259SAndrew.Bardsley@arm.com} 157810259SAndrew.Bardsley@arm.com 157910259SAndrew.Bardsley@arm.comvoid 158010259SAndrew.Bardsley@arm.comLSQ::pushFailedRequest(MinorDynInstPtr inst) 158110259SAndrew.Bardsley@arm.com{ 158210259SAndrew.Bardsley@arm.com LSQRequestPtr request = new FailedDataRequest(*this, inst); 158310259SAndrew.Bardsley@arm.com requests.push(request); 158410259SAndrew.Bardsley@arm.com} 158510259SAndrew.Bardsley@arm.com 158610259SAndrew.Bardsley@arm.comvoid 158710259SAndrew.Bardsley@arm.comLSQ::minorTrace() const 158810259SAndrew.Bardsley@arm.com{ 158910259SAndrew.Bardsley@arm.com MINORTRACE("state=%s in_tlb_mem=%d/%d stores_in_transfers=%d" 159010259SAndrew.Bardsley@arm.com " lastMemBarrier=%d\n", 159110259SAndrew.Bardsley@arm.com state, numAccessesInDTLB, numAccessesInMemorySystem, 159211567Smitch.hayenga@arm.com numStoresInTransfers, lastMemBarrier[0]); 159310259SAndrew.Bardsley@arm.com requests.minorTrace(); 159410259SAndrew.Bardsley@arm.com transfers.minorTrace(); 159510259SAndrew.Bardsley@arm.com storeBuffer.minorTrace(); 159610259SAndrew.Bardsley@arm.com} 159710259SAndrew.Bardsley@arm.com 159810259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::StoreBuffer(std::string name_, LSQ &lsq_, 159910259SAndrew.Bardsley@arm.com unsigned int store_buffer_size, 160010259SAndrew.Bardsley@arm.com unsigned int store_limit_per_cycle) : 160110259SAndrew.Bardsley@arm.com Named(name_), lsq(lsq_), 160210259SAndrew.Bardsley@arm.com numSlots(store_buffer_size), 160310259SAndrew.Bardsley@arm.com storeLimitPerCycle(store_limit_per_cycle), 160410259SAndrew.Bardsley@arm.com slots(), 160510259SAndrew.Bardsley@arm.com numUnissuedAccesses(0) 160610259SAndrew.Bardsley@arm.com{ 160710259SAndrew.Bardsley@arm.com} 160810259SAndrew.Bardsley@arm.com 160910259SAndrew.Bardsley@arm.comPacketPtr 161012749Sgiacomo.travaglini@arm.commakePacketForRequest(const RequestPtr &request, bool isLoad, 161110259SAndrew.Bardsley@arm.com Packet::SenderState *sender_state, PacketDataPtr data) 161210259SAndrew.Bardsley@arm.com{ 161312749Sgiacomo.travaglini@arm.com PacketPtr ret = isLoad ? Packet::createRead(request) 161412749Sgiacomo.travaglini@arm.com : Packet::createWrite(request); 161510259SAndrew.Bardsley@arm.com 161610259SAndrew.Bardsley@arm.com if (sender_state) 161710259SAndrew.Bardsley@arm.com ret->pushSenderState(sender_state); 161810259SAndrew.Bardsley@arm.com 161912355Snikos.nikoleris@arm.com if (isLoad) { 162010259SAndrew.Bardsley@arm.com ret->allocate(); 162112749Sgiacomo.travaglini@arm.com } else if (!request->isCacheMaintenance()) { 162212355Snikos.nikoleris@arm.com // CMOs are treated as stores but they don't have data. All 162312355Snikos.nikoleris@arm.com // stores otherwise need to allocate for data. 162410566Sandreas.hansson@arm.com ret->dataDynamic(data); 162512355Snikos.nikoleris@arm.com } 162610259SAndrew.Bardsley@arm.com 162710259SAndrew.Bardsley@arm.com return ret; 162810259SAndrew.Bardsley@arm.com} 162910259SAndrew.Bardsley@arm.com 163010259SAndrew.Bardsley@arm.comvoid 163110259SAndrew.Bardsley@arm.comLSQ::issuedMemBarrierInst(MinorDynInstPtr inst) 163210259SAndrew.Bardsley@arm.com{ 163310259SAndrew.Bardsley@arm.com assert(inst->isInst() && inst->staticInst->isMemBarrier()); 163411567Smitch.hayenga@arm.com assert(inst->id.execSeqNum > lastMemBarrier[inst->id.threadId]); 163510259SAndrew.Bardsley@arm.com 163610259SAndrew.Bardsley@arm.com /* Remember the barrier. We only have a notion of one 163710259SAndrew.Bardsley@arm.com * barrier so this may result in some mem refs being 163810259SAndrew.Bardsley@arm.com * delayed if they are between barriers */ 163911567Smitch.hayenga@arm.com lastMemBarrier[inst->id.threadId] = inst->id.execSeqNum; 164010259SAndrew.Bardsley@arm.com} 164110259SAndrew.Bardsley@arm.com 164210259SAndrew.Bardsley@arm.comvoid 164310259SAndrew.Bardsley@arm.comLSQ::LSQRequest::makePacket() 164410259SAndrew.Bardsley@arm.com{ 164510259SAndrew.Bardsley@arm.com /* Make the function idempotent */ 164610259SAndrew.Bardsley@arm.com if (packet) 164710259SAndrew.Bardsley@arm.com return; 164810259SAndrew.Bardsley@arm.com 164911056Sandreas.hansson@arm.com // if the translation faulted, do not create a packet 165011056Sandreas.hansson@arm.com if (fault != NoFault) { 165111056Sandreas.hansson@arm.com assert(packet == NULL); 165211056Sandreas.hansson@arm.com return; 165311056Sandreas.hansson@arm.com } 165411056Sandreas.hansson@arm.com 165510259SAndrew.Bardsley@arm.com packet = makePacketForRequest(request, isLoad, this, data); 165610259SAndrew.Bardsley@arm.com /* Null the ret data so we know not to deallocate it when the 165710259SAndrew.Bardsley@arm.com * ret is destroyed. The data now belongs to the ret and 165810259SAndrew.Bardsley@arm.com * the ret is responsible for its destruction */ 165910259SAndrew.Bardsley@arm.com data = NULL; 166010259SAndrew.Bardsley@arm.com} 166110259SAndrew.Bardsley@arm.com 166210259SAndrew.Bardsley@arm.comstd::ostream & 166310259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, LSQ::MemoryState state) 166410259SAndrew.Bardsley@arm.com{ 166510259SAndrew.Bardsley@arm.com switch (state) { 166610259SAndrew.Bardsley@arm.com case LSQ::MemoryRunning: 166710259SAndrew.Bardsley@arm.com os << "MemoryRunning"; 166810259SAndrew.Bardsley@arm.com break; 166910259SAndrew.Bardsley@arm.com case LSQ::MemoryNeedsRetry: 167010259SAndrew.Bardsley@arm.com os << "MemoryNeedsRetry"; 167110259SAndrew.Bardsley@arm.com break; 167210259SAndrew.Bardsley@arm.com default: 167310259SAndrew.Bardsley@arm.com os << "MemoryState-" << static_cast<int>(state); 167410259SAndrew.Bardsley@arm.com break; 167510259SAndrew.Bardsley@arm.com } 167610259SAndrew.Bardsley@arm.com return os; 167710259SAndrew.Bardsley@arm.com} 167810259SAndrew.Bardsley@arm.com 167910259SAndrew.Bardsley@arm.comvoid 168010259SAndrew.Bardsley@arm.comLSQ::recvTimingSnoopReq(PacketPtr pkt) 168110259SAndrew.Bardsley@arm.com{ 168210259SAndrew.Bardsley@arm.com /* LLSC operations in Minor can't be speculative and are executed from 168310259SAndrew.Bardsley@arm.com * the head of the requests queue. We shouldn't need to do more than 168410259SAndrew.Bardsley@arm.com * this action on snoops. */ 168511567Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 168611567Smitch.hayenga@arm.com if (cpu.getCpuAddrMonitor(tid)->doMonitor(pkt)) { 168711567Smitch.hayenga@arm.com cpu.wakeup(tid); 168811567Smitch.hayenga@arm.com } 168911567Smitch.hayenga@arm.com } 169010259SAndrew.Bardsley@arm.com 169111356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 169211567Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 169311567Smitch.hayenga@arm.com TheISA::handleLockedSnoop(cpu.getContext(tid), pkt, 169411567Smitch.hayenga@arm.com cacheBlockMask); 169511567Smitch.hayenga@arm.com } 169611567Smitch.hayenga@arm.com } 169711567Smitch.hayenga@arm.com} 169811567Smitch.hayenga@arm.com 169911567Smitch.hayenga@arm.comvoid 170011567Smitch.hayenga@arm.comLSQ::threadSnoop(LSQRequestPtr request) 170111567Smitch.hayenga@arm.com{ 170211567Smitch.hayenga@arm.com /* LLSC operations in Minor can't be speculative and are executed from 170311567Smitch.hayenga@arm.com * the head of the requests queue. We shouldn't need to do more than 170411567Smitch.hayenga@arm.com * this action on snoops. */ 170511567Smitch.hayenga@arm.com ThreadID req_tid = request->inst->id.threadId; 170611567Smitch.hayenga@arm.com PacketPtr pkt = request->packet; 170711567Smitch.hayenga@arm.com 170811567Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 170911567Smitch.hayenga@arm.com if (tid != req_tid) { 171011567Smitch.hayenga@arm.com if (cpu.getCpuAddrMonitor(tid)->doMonitor(pkt)) { 171111567Smitch.hayenga@arm.com cpu.wakeup(tid); 171211567Smitch.hayenga@arm.com } 171311567Smitch.hayenga@arm.com 171411567Smitch.hayenga@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 171511567Smitch.hayenga@arm.com TheISA::handleLockedSnoop(cpu.getContext(tid), pkt, 171611567Smitch.hayenga@arm.com cacheBlockMask); 171711567Smitch.hayenga@arm.com } 171811567Smitch.hayenga@arm.com } 171911356Skrinat01@arm.com } 172010259SAndrew.Bardsley@arm.com} 172110259SAndrew.Bardsley@arm.com 172210259SAndrew.Bardsley@arm.com} 1723