lsq.cc revision 12749
110259SAndrew.Bardsley@arm.com/* 212355Snikos.nikoleris@arm.com * Copyright (c) 2013-2014,2017 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1510259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1610259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 1710259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 1810259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1910259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2010259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2110259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2210259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2310259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2410259SAndrew.Bardsley@arm.com * 2510259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610259SAndrew.Bardsley@arm.com * 3710259SAndrew.Bardsley@arm.com * Authors: Andrew Bardsley 3810259SAndrew.Bardsley@arm.com */ 3910259SAndrew.Bardsley@arm.com 4011793Sbrandon.potter@amd.com#include "cpu/minor/lsq.hh" 4111793Sbrandon.potter@amd.com 4210259SAndrew.Bardsley@arm.com#include <iomanip> 4310259SAndrew.Bardsley@arm.com#include <sstream> 4410259SAndrew.Bardsley@arm.com 4510259SAndrew.Bardsley@arm.com#include "arch/locked_mem.hh" 4610259SAndrew.Bardsley@arm.com#include "arch/mmapped_ipr.hh" 4710259SAndrew.Bardsley@arm.com#include "cpu/minor/cpu.hh" 4810259SAndrew.Bardsley@arm.com#include "cpu/minor/exec_context.hh" 4910259SAndrew.Bardsley@arm.com#include "cpu/minor/execute.hh" 5010259SAndrew.Bardsley@arm.com#include "cpu/minor/pipeline.hh" 5110259SAndrew.Bardsley@arm.com#include "debug/Activity.hh" 5210259SAndrew.Bardsley@arm.com#include "debug/MinorMem.hh" 5310259SAndrew.Bardsley@arm.com 5410259SAndrew.Bardsley@arm.comnamespace Minor 5510259SAndrew.Bardsley@arm.com{ 5610259SAndrew.Bardsley@arm.com 5710259SAndrew.Bardsley@arm.com/** Returns the offset of addr into an aligned a block of size block_size */ 5810259SAndrew.Bardsley@arm.comstatic Addr 5910259SAndrew.Bardsley@arm.comaddrBlockOffset(Addr addr, unsigned int block_size) 6010259SAndrew.Bardsley@arm.com{ 6110259SAndrew.Bardsley@arm.com return addr & (block_size - 1); 6210259SAndrew.Bardsley@arm.com} 6310259SAndrew.Bardsley@arm.com 6410259SAndrew.Bardsley@arm.com/** Returns true if the given [addr .. addr+size-1] transfer needs to be 6510259SAndrew.Bardsley@arm.com * fragmented across a block size of block_size */ 6610259SAndrew.Bardsley@arm.comstatic bool 6710259SAndrew.Bardsley@arm.comtransferNeedsBurst(Addr addr, unsigned int size, unsigned int block_size) 6810259SAndrew.Bardsley@arm.com{ 6910259SAndrew.Bardsley@arm.com return (addrBlockOffset(addr, block_size) + size) > block_size; 7010259SAndrew.Bardsley@arm.com} 7110259SAndrew.Bardsley@arm.com 7210259SAndrew.Bardsley@arm.comLSQ::LSQRequest::LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_, 7310259SAndrew.Bardsley@arm.com PacketDataPtr data_, uint64_t *res_) : 7410259SAndrew.Bardsley@arm.com SenderState(), 7510259SAndrew.Bardsley@arm.com port(port_), 7610259SAndrew.Bardsley@arm.com inst(inst_), 7710259SAndrew.Bardsley@arm.com isLoad(isLoad_), 7810259SAndrew.Bardsley@arm.com data(data_), 7910259SAndrew.Bardsley@arm.com packet(NULL), 8010259SAndrew.Bardsley@arm.com request(), 8110259SAndrew.Bardsley@arm.com fault(NoFault), 8210259SAndrew.Bardsley@arm.com res(res_), 8310259SAndrew.Bardsley@arm.com skipped(false), 8410259SAndrew.Bardsley@arm.com issuedToMemory(false), 8510259SAndrew.Bardsley@arm.com state(NotIssued) 8612749Sgiacomo.travaglini@arm.com{ 8712749Sgiacomo.travaglini@arm.com request = std::make_shared<Request>(); 8812749Sgiacomo.travaglini@arm.com} 8910259SAndrew.Bardsley@arm.com 9010259SAndrew.Bardsley@arm.comLSQ::AddrRangeCoverage 9110259SAndrew.Bardsley@arm.comLSQ::LSQRequest::containsAddrRangeOf( 9210259SAndrew.Bardsley@arm.com Addr req1_addr, unsigned int req1_size, 9310259SAndrew.Bardsley@arm.com Addr req2_addr, unsigned int req2_size) 9410259SAndrew.Bardsley@arm.com{ 9510259SAndrew.Bardsley@arm.com /* 'end' here means the address of the byte just past the request 9610259SAndrew.Bardsley@arm.com * blocks */ 9710259SAndrew.Bardsley@arm.com Addr req2_end_addr = req2_addr + req2_size; 9810259SAndrew.Bardsley@arm.com Addr req1_end_addr = req1_addr + req1_size; 9910259SAndrew.Bardsley@arm.com 10010259SAndrew.Bardsley@arm.com AddrRangeCoverage ret; 10110259SAndrew.Bardsley@arm.com 10212179Spau.cabre@metempsy.com if (req1_addr >= req2_end_addr || req1_end_addr <= req2_addr) 10310259SAndrew.Bardsley@arm.com ret = NoAddrRangeCoverage; 10410259SAndrew.Bardsley@arm.com else if (req1_addr <= req2_addr && req1_end_addr >= req2_end_addr) 10510259SAndrew.Bardsley@arm.com ret = FullAddrRangeCoverage; 10610259SAndrew.Bardsley@arm.com else 10710259SAndrew.Bardsley@arm.com ret = PartialAddrRangeCoverage; 10810259SAndrew.Bardsley@arm.com 10910259SAndrew.Bardsley@arm.com return ret; 11010259SAndrew.Bardsley@arm.com} 11110259SAndrew.Bardsley@arm.com 11210259SAndrew.Bardsley@arm.comLSQ::AddrRangeCoverage 11310259SAndrew.Bardsley@arm.comLSQ::LSQRequest::containsAddrRangeOf(LSQRequestPtr other_request) 11410259SAndrew.Bardsley@arm.com{ 11512749Sgiacomo.travaglini@arm.com return containsAddrRangeOf(request->getPaddr(), request->getSize(), 11612749Sgiacomo.travaglini@arm.com other_request->request->getPaddr(), other_request->request->getSize()); 11710259SAndrew.Bardsley@arm.com} 11810259SAndrew.Bardsley@arm.com 11910259SAndrew.Bardsley@arm.combool 12010259SAndrew.Bardsley@arm.comLSQ::LSQRequest::isBarrier() 12110259SAndrew.Bardsley@arm.com{ 12210259SAndrew.Bardsley@arm.com return inst->isInst() && inst->staticInst->isMemBarrier(); 12310259SAndrew.Bardsley@arm.com} 12410259SAndrew.Bardsley@arm.com 12510259SAndrew.Bardsley@arm.combool 12610259SAndrew.Bardsley@arm.comLSQ::LSQRequest::needsToBeSentToStoreBuffer() 12710259SAndrew.Bardsley@arm.com{ 12810259SAndrew.Bardsley@arm.com return state == StoreToStoreBuffer; 12910259SAndrew.Bardsley@arm.com} 13010259SAndrew.Bardsley@arm.com 13110259SAndrew.Bardsley@arm.comvoid 13210259SAndrew.Bardsley@arm.comLSQ::LSQRequest::setState(LSQRequestState new_state) 13310259SAndrew.Bardsley@arm.com{ 13410259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Setting state from %d to %d for request:" 13510259SAndrew.Bardsley@arm.com " %s\n", state, new_state, *inst); 13610259SAndrew.Bardsley@arm.com state = new_state; 13710259SAndrew.Bardsley@arm.com} 13810259SAndrew.Bardsley@arm.com 13910259SAndrew.Bardsley@arm.combool 14010259SAndrew.Bardsley@arm.comLSQ::LSQRequest::isComplete() const 14110259SAndrew.Bardsley@arm.com{ 14210259SAndrew.Bardsley@arm.com /* @todo, There is currently only one 'completed' state. This 14310259SAndrew.Bardsley@arm.com * may not be a good choice */ 14410259SAndrew.Bardsley@arm.com return state == Complete; 14510259SAndrew.Bardsley@arm.com} 14610259SAndrew.Bardsley@arm.com 14710259SAndrew.Bardsley@arm.comvoid 14810259SAndrew.Bardsley@arm.comLSQ::LSQRequest::reportData(std::ostream &os) const 14910259SAndrew.Bardsley@arm.com{ 15010259SAndrew.Bardsley@arm.com os << (isLoad ? 'R' : 'W') << ';'; 15110259SAndrew.Bardsley@arm.com inst->reportData(os); 15210259SAndrew.Bardsley@arm.com os << ';' << state; 15310259SAndrew.Bardsley@arm.com} 15410259SAndrew.Bardsley@arm.com 15510259SAndrew.Bardsley@arm.comstd::ostream & 15610259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, LSQ::AddrRangeCoverage coverage) 15710259SAndrew.Bardsley@arm.com{ 15810259SAndrew.Bardsley@arm.com switch (coverage) { 15910259SAndrew.Bardsley@arm.com case LSQ::PartialAddrRangeCoverage: 16010259SAndrew.Bardsley@arm.com os << "PartialAddrRangeCoverage"; 16110259SAndrew.Bardsley@arm.com break; 16210259SAndrew.Bardsley@arm.com case LSQ::FullAddrRangeCoverage: 16310259SAndrew.Bardsley@arm.com os << "FullAddrRangeCoverage"; 16410259SAndrew.Bardsley@arm.com break; 16510259SAndrew.Bardsley@arm.com case LSQ::NoAddrRangeCoverage: 16610259SAndrew.Bardsley@arm.com os << "NoAddrRangeCoverage"; 16710259SAndrew.Bardsley@arm.com break; 16810259SAndrew.Bardsley@arm.com default: 16910259SAndrew.Bardsley@arm.com os << "AddrRangeCoverage-" << static_cast<int>(coverage); 17010259SAndrew.Bardsley@arm.com break; 17110259SAndrew.Bardsley@arm.com } 17210259SAndrew.Bardsley@arm.com return os; 17310259SAndrew.Bardsley@arm.com} 17410259SAndrew.Bardsley@arm.com 17510259SAndrew.Bardsley@arm.comstd::ostream & 17610259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, LSQ::LSQRequest::LSQRequestState state) 17710259SAndrew.Bardsley@arm.com{ 17810259SAndrew.Bardsley@arm.com switch (state) { 17910259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::NotIssued: 18010259SAndrew.Bardsley@arm.com os << "NotIssued"; 18110259SAndrew.Bardsley@arm.com break; 18210259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::InTranslation: 18310259SAndrew.Bardsley@arm.com os << "InTranslation"; 18410259SAndrew.Bardsley@arm.com break; 18510259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::Translated: 18610259SAndrew.Bardsley@arm.com os << "Translated"; 18710259SAndrew.Bardsley@arm.com break; 18810259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::Failed: 18910259SAndrew.Bardsley@arm.com os << "Failed"; 19010259SAndrew.Bardsley@arm.com break; 19110259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::RequestIssuing: 19210259SAndrew.Bardsley@arm.com os << "RequestIssuing"; 19310259SAndrew.Bardsley@arm.com break; 19410259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreToStoreBuffer: 19510259SAndrew.Bardsley@arm.com os << "StoreToStoreBuffer"; 19610259SAndrew.Bardsley@arm.com break; 19710259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreInStoreBuffer: 19810259SAndrew.Bardsley@arm.com os << "StoreInStoreBuffer"; 19910259SAndrew.Bardsley@arm.com break; 20010259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreBufferIssuing: 20110259SAndrew.Bardsley@arm.com os << "StoreBufferIssuing"; 20210259SAndrew.Bardsley@arm.com break; 20310259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::RequestNeedsRetry: 20410259SAndrew.Bardsley@arm.com os << "RequestNeedsRetry"; 20510259SAndrew.Bardsley@arm.com break; 20610259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreBufferNeedsRetry: 20710259SAndrew.Bardsley@arm.com os << "StoreBufferNeedsRetry"; 20810259SAndrew.Bardsley@arm.com break; 20910259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::Complete: 21010259SAndrew.Bardsley@arm.com os << "Complete"; 21110259SAndrew.Bardsley@arm.com break; 21210259SAndrew.Bardsley@arm.com default: 21310259SAndrew.Bardsley@arm.com os << "LSQRequestState-" << static_cast<int>(state); 21410259SAndrew.Bardsley@arm.com break; 21510259SAndrew.Bardsley@arm.com } 21610259SAndrew.Bardsley@arm.com return os; 21710259SAndrew.Bardsley@arm.com} 21810259SAndrew.Bardsley@arm.com 21910259SAndrew.Bardsley@arm.comvoid 22010259SAndrew.Bardsley@arm.comLSQ::clearMemBarrier(MinorDynInstPtr inst) 22110259SAndrew.Bardsley@arm.com{ 22211567Smitch.hayenga@arm.com bool is_last_barrier = 22311567Smitch.hayenga@arm.com inst->id.execSeqNum >= lastMemBarrier[inst->id.threadId]; 22410259SAndrew.Bardsley@arm.com 22510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Moving %s barrier out of store buffer inst: %s\n", 22610259SAndrew.Bardsley@arm.com (is_last_barrier ? "last" : "a"), *inst); 22710259SAndrew.Bardsley@arm.com 22810259SAndrew.Bardsley@arm.com if (is_last_barrier) 22911567Smitch.hayenga@arm.com lastMemBarrier[inst->id.threadId] = 0; 23010259SAndrew.Bardsley@arm.com} 23110259SAndrew.Bardsley@arm.com 23210259SAndrew.Bardsley@arm.comvoid 23312749Sgiacomo.travaglini@arm.comLSQ::SingleDataRequest::finish(const Fault &fault_, const RequestPtr &request_, 23410379Sandreas.hansson@arm.com ThreadContext *tc, BaseTLB::Mode mode) 23510259SAndrew.Bardsley@arm.com{ 23610259SAndrew.Bardsley@arm.com fault = fault_; 23710259SAndrew.Bardsley@arm.com 23810259SAndrew.Bardsley@arm.com port.numAccessesInDTLB--; 23910259SAndrew.Bardsley@arm.com 24010259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Received translation response for" 24110259SAndrew.Bardsley@arm.com " request: %s\n", *inst); 24210259SAndrew.Bardsley@arm.com 24310259SAndrew.Bardsley@arm.com makePacket(); 24410259SAndrew.Bardsley@arm.com 24510259SAndrew.Bardsley@arm.com setState(Translated); 24610259SAndrew.Bardsley@arm.com port.tryToSendToTransfers(this); 24710259SAndrew.Bardsley@arm.com 24810259SAndrew.Bardsley@arm.com /* Let's try and wake up the processor for the next cycle */ 24910259SAndrew.Bardsley@arm.com port.cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 25010259SAndrew.Bardsley@arm.com} 25110259SAndrew.Bardsley@arm.com 25210259SAndrew.Bardsley@arm.comvoid 25310259SAndrew.Bardsley@arm.comLSQ::SingleDataRequest::startAddrTranslation() 25410259SAndrew.Bardsley@arm.com{ 25510259SAndrew.Bardsley@arm.com ThreadContext *thread = port.cpu.getContext( 25610259SAndrew.Bardsley@arm.com inst->id.threadId); 25710259SAndrew.Bardsley@arm.com 25810259SAndrew.Bardsley@arm.com port.numAccessesInDTLB++; 25910259SAndrew.Bardsley@arm.com 26010259SAndrew.Bardsley@arm.com setState(LSQ::LSQRequest::InTranslation); 26110259SAndrew.Bardsley@arm.com 26210259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Submitting DTLB request\n"); 26310259SAndrew.Bardsley@arm.com /* Submit the translation request. The response will come through 26410259SAndrew.Bardsley@arm.com * finish/markDelayed on the LSQRequest as it bears the Translation 26510259SAndrew.Bardsley@arm.com * interface */ 26610259SAndrew.Bardsley@arm.com thread->getDTBPtr()->translateTiming( 26712749Sgiacomo.travaglini@arm.com request, thread, this, (isLoad ? BaseTLB::Read : BaseTLB::Write)); 26810259SAndrew.Bardsley@arm.com} 26910259SAndrew.Bardsley@arm.com 27010259SAndrew.Bardsley@arm.comvoid 27110259SAndrew.Bardsley@arm.comLSQ::SingleDataRequest::retireResponse(PacketPtr packet_) 27210259SAndrew.Bardsley@arm.com{ 27310259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Retiring packet\n"); 27410259SAndrew.Bardsley@arm.com packet = packet_; 27510259SAndrew.Bardsley@arm.com packetInFlight = false; 27610259SAndrew.Bardsley@arm.com setState(Complete); 27710259SAndrew.Bardsley@arm.com} 27810259SAndrew.Bardsley@arm.com 27910259SAndrew.Bardsley@arm.comvoid 28012749Sgiacomo.travaglini@arm.comLSQ::SplitDataRequest::finish(const Fault &fault_, const RequestPtr &request_, 28110379Sandreas.hansson@arm.com ThreadContext *tc, BaseTLB::Mode mode) 28210259SAndrew.Bardsley@arm.com{ 28310259SAndrew.Bardsley@arm.com fault = fault_; 28410259SAndrew.Bardsley@arm.com 28510259SAndrew.Bardsley@arm.com port.numAccessesInDTLB--; 28610259SAndrew.Bardsley@arm.com 28710259SAndrew.Bardsley@arm.com unsigned int M5_VAR_USED expected_fragment_index = 28810259SAndrew.Bardsley@arm.com numTranslatedFragments; 28910259SAndrew.Bardsley@arm.com 29010259SAndrew.Bardsley@arm.com numInTranslationFragments--; 29110259SAndrew.Bardsley@arm.com numTranslatedFragments++; 29210259SAndrew.Bardsley@arm.com 29310259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Received translation response for fragment" 29410259SAndrew.Bardsley@arm.com " %d of request: %s\n", expected_fragment_index, *inst); 29510259SAndrew.Bardsley@arm.com 29610259SAndrew.Bardsley@arm.com assert(request_ == fragmentRequests[expected_fragment_index]); 29710259SAndrew.Bardsley@arm.com 29810259SAndrew.Bardsley@arm.com /* Wake up next cycle to get things going again in case the 29910259SAndrew.Bardsley@arm.com * tryToSendToTransfers does take */ 30010259SAndrew.Bardsley@arm.com port.cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 30110259SAndrew.Bardsley@arm.com 30210259SAndrew.Bardsley@arm.com if (fault != NoFault) { 30310259SAndrew.Bardsley@arm.com /* tryToSendToTransfers will handle the fault */ 30410259SAndrew.Bardsley@arm.com 30510259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Faulting translation for fragment:" 30610259SAndrew.Bardsley@arm.com " %d of request: %s\n", 30710259SAndrew.Bardsley@arm.com expected_fragment_index, *inst); 30810259SAndrew.Bardsley@arm.com 30910259SAndrew.Bardsley@arm.com setState(Translated); 31010259SAndrew.Bardsley@arm.com port.tryToSendToTransfers(this); 31110259SAndrew.Bardsley@arm.com } else if (numTranslatedFragments == numFragments) { 31210259SAndrew.Bardsley@arm.com makeFragmentPackets(); 31310259SAndrew.Bardsley@arm.com 31410259SAndrew.Bardsley@arm.com setState(Translated); 31510259SAndrew.Bardsley@arm.com port.tryToSendToTransfers(this); 31610259SAndrew.Bardsley@arm.com } else { 31710259SAndrew.Bardsley@arm.com /* Avoid calling translateTiming from within ::finish */ 31810259SAndrew.Bardsley@arm.com assert(!translationEvent.scheduled()); 31910259SAndrew.Bardsley@arm.com port.cpu.schedule(translationEvent, curTick()); 32010259SAndrew.Bardsley@arm.com } 32110259SAndrew.Bardsley@arm.com} 32210259SAndrew.Bardsley@arm.com 32310259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_, 32410259SAndrew.Bardsley@arm.com bool isLoad_, PacketDataPtr data_, uint64_t *res_) : 32510259SAndrew.Bardsley@arm.com LSQRequest(port_, inst_, isLoad_, data_, res_), 32612127Sspwilson2@wisc.edu translationEvent([this]{ sendNextFragmentToTranslation(); }, 32712127Sspwilson2@wisc.edu "translationEvent"), 32810259SAndrew.Bardsley@arm.com numFragments(0), 32910259SAndrew.Bardsley@arm.com numInTranslationFragments(0), 33010259SAndrew.Bardsley@arm.com numTranslatedFragments(0), 33110259SAndrew.Bardsley@arm.com numIssuedFragments(0), 33210259SAndrew.Bardsley@arm.com numRetiredFragments(0), 33310259SAndrew.Bardsley@arm.com fragmentRequests(), 33410259SAndrew.Bardsley@arm.com fragmentPackets() 33510259SAndrew.Bardsley@arm.com{ 33610259SAndrew.Bardsley@arm.com /* Don't know how many elements are needed until the request is 33710259SAndrew.Bardsley@arm.com * populated by the caller. */ 33810259SAndrew.Bardsley@arm.com} 33910259SAndrew.Bardsley@arm.com 34010259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::~SplitDataRequest() 34110259SAndrew.Bardsley@arm.com{ 34210259SAndrew.Bardsley@arm.com for (auto i = fragmentPackets.begin(); 34310259SAndrew.Bardsley@arm.com i != fragmentPackets.end(); i++) 34410259SAndrew.Bardsley@arm.com { 34510259SAndrew.Bardsley@arm.com delete *i; 34610259SAndrew.Bardsley@arm.com } 34710259SAndrew.Bardsley@arm.com} 34810259SAndrew.Bardsley@arm.com 34910259SAndrew.Bardsley@arm.comvoid 35010259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::makeFragmentRequests() 35110259SAndrew.Bardsley@arm.com{ 35212749Sgiacomo.travaglini@arm.com Addr base_addr = request->getVaddr(); 35312749Sgiacomo.travaglini@arm.com unsigned int whole_size = request->getSize(); 35410259SAndrew.Bardsley@arm.com unsigned int line_width = port.lineWidth; 35510259SAndrew.Bardsley@arm.com 35610259SAndrew.Bardsley@arm.com unsigned int fragment_size; 35710259SAndrew.Bardsley@arm.com Addr fragment_addr; 35810259SAndrew.Bardsley@arm.com 35910259SAndrew.Bardsley@arm.com /* Assume that this transfer is across potentially many block snap 36010259SAndrew.Bardsley@arm.com * boundaries: 36110259SAndrew.Bardsley@arm.com * 36210259SAndrew.Bardsley@arm.com * | _|________|________|________|___ | 36310259SAndrew.Bardsley@arm.com * | |0| 1 | 2 | 3 | 4 | | 36410259SAndrew.Bardsley@arm.com * | |_|________|________|________|___| | 36510259SAndrew.Bardsley@arm.com * | | | | | | 36610259SAndrew.Bardsley@arm.com * 36710259SAndrew.Bardsley@arm.com * The first transfer (0) can be up to lineWidth in size. 36810259SAndrew.Bardsley@arm.com * All the middle transfers (1-3) are lineWidth in size 36910259SAndrew.Bardsley@arm.com * The last transfer (4) can be from zero to lineWidth - 1 in size 37010259SAndrew.Bardsley@arm.com */ 37110259SAndrew.Bardsley@arm.com unsigned int first_fragment_offset = 37210259SAndrew.Bardsley@arm.com addrBlockOffset(base_addr, line_width); 37310259SAndrew.Bardsley@arm.com unsigned int last_fragment_size = 37410259SAndrew.Bardsley@arm.com addrBlockOffset(base_addr + whole_size, line_width); 37510259SAndrew.Bardsley@arm.com unsigned int first_fragment_size = 37610259SAndrew.Bardsley@arm.com line_width - first_fragment_offset; 37710259SAndrew.Bardsley@arm.com 37810259SAndrew.Bardsley@arm.com unsigned int middle_fragments_total_size = 37910259SAndrew.Bardsley@arm.com whole_size - (first_fragment_size + last_fragment_size); 38010259SAndrew.Bardsley@arm.com 38110259SAndrew.Bardsley@arm.com assert(addrBlockOffset(middle_fragments_total_size, line_width) == 0); 38210259SAndrew.Bardsley@arm.com 38310259SAndrew.Bardsley@arm.com unsigned int middle_fragment_count = 38410259SAndrew.Bardsley@arm.com middle_fragments_total_size / line_width; 38510259SAndrew.Bardsley@arm.com 38610259SAndrew.Bardsley@arm.com numFragments = 1 /* first */ + middle_fragment_count + 38710259SAndrew.Bardsley@arm.com (last_fragment_size == 0 ? 0 : 1); 38810259SAndrew.Bardsley@arm.com 38910259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Dividing transfer into %d fragmentRequests." 39010259SAndrew.Bardsley@arm.com " First fragment size: %d Last fragment size: %d\n", 39110259SAndrew.Bardsley@arm.com numFragments, first_fragment_size, 39210259SAndrew.Bardsley@arm.com (last_fragment_size == 0 ? line_width : last_fragment_size)); 39310259SAndrew.Bardsley@arm.com 39410259SAndrew.Bardsley@arm.com assert(((middle_fragment_count * line_width) + 39510259SAndrew.Bardsley@arm.com first_fragment_size + last_fragment_size) == whole_size); 39610259SAndrew.Bardsley@arm.com 39710259SAndrew.Bardsley@arm.com fragment_addr = base_addr; 39810259SAndrew.Bardsley@arm.com fragment_size = first_fragment_size; 39910259SAndrew.Bardsley@arm.com 40010259SAndrew.Bardsley@arm.com /* Just past the last address in the request */ 40110259SAndrew.Bardsley@arm.com Addr end_addr = base_addr + whole_size; 40210259SAndrew.Bardsley@arm.com 40310259SAndrew.Bardsley@arm.com for (unsigned int fragment_index = 0; fragment_index < numFragments; 40410259SAndrew.Bardsley@arm.com fragment_index++) 40510259SAndrew.Bardsley@arm.com { 40610259SAndrew.Bardsley@arm.com bool M5_VAR_USED is_last_fragment = false; 40710259SAndrew.Bardsley@arm.com 40810259SAndrew.Bardsley@arm.com if (fragment_addr == base_addr) { 40910259SAndrew.Bardsley@arm.com /* First fragment */ 41010259SAndrew.Bardsley@arm.com fragment_size = first_fragment_size; 41110259SAndrew.Bardsley@arm.com } else { 41210259SAndrew.Bardsley@arm.com if ((fragment_addr + line_width) > end_addr) { 41310259SAndrew.Bardsley@arm.com /* Adjust size of last fragment */ 41410259SAndrew.Bardsley@arm.com fragment_size = end_addr - fragment_addr; 41510259SAndrew.Bardsley@arm.com is_last_fragment = true; 41610259SAndrew.Bardsley@arm.com } else { 41710259SAndrew.Bardsley@arm.com /* Middle fragments */ 41810259SAndrew.Bardsley@arm.com fragment_size = line_width; 41910259SAndrew.Bardsley@arm.com } 42010259SAndrew.Bardsley@arm.com } 42110259SAndrew.Bardsley@arm.com 42212749Sgiacomo.travaglini@arm.com RequestPtr fragment = std::make_shared<Request>(); 42310259SAndrew.Bardsley@arm.com 42412749Sgiacomo.travaglini@arm.com fragment->setContext(request->contextId()); 42510259SAndrew.Bardsley@arm.com fragment->setVirt(0 /* asid */, 42612749Sgiacomo.travaglini@arm.com fragment_addr, fragment_size, request->getFlags(), 42712749Sgiacomo.travaglini@arm.com request->masterId(), 42812749Sgiacomo.travaglini@arm.com request->getPC()); 42910259SAndrew.Bardsley@arm.com 43010259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Generating fragment addr: 0x%x size: %d" 43110259SAndrew.Bardsley@arm.com " (whole request addr: 0x%x size: %d) %s\n", 43210259SAndrew.Bardsley@arm.com fragment_addr, fragment_size, base_addr, whole_size, 43310259SAndrew.Bardsley@arm.com (is_last_fragment ? "last fragment" : "")); 43410259SAndrew.Bardsley@arm.com 43510259SAndrew.Bardsley@arm.com fragment_addr += fragment_size; 43610259SAndrew.Bardsley@arm.com 43710259SAndrew.Bardsley@arm.com fragmentRequests.push_back(fragment); 43810259SAndrew.Bardsley@arm.com } 43910259SAndrew.Bardsley@arm.com} 44010259SAndrew.Bardsley@arm.com 44110259SAndrew.Bardsley@arm.comvoid 44210259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::makeFragmentPackets() 44310259SAndrew.Bardsley@arm.com{ 44412749Sgiacomo.travaglini@arm.com Addr base_addr = request->getVaddr(); 44510259SAndrew.Bardsley@arm.com 44610259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Making packets for request: %s\n", *inst); 44710259SAndrew.Bardsley@arm.com 44810259SAndrew.Bardsley@arm.com for (unsigned int fragment_index = 0; fragment_index < numFragments; 44910259SAndrew.Bardsley@arm.com fragment_index++) 45010259SAndrew.Bardsley@arm.com { 45112748Sgiacomo.travaglini@arm.com RequestPtr fragment = fragmentRequests[fragment_index]; 45210259SAndrew.Bardsley@arm.com 45310259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Making packet %d for request: %s" 45410259SAndrew.Bardsley@arm.com " (%d, 0x%x)\n", 45510259SAndrew.Bardsley@arm.com fragment_index, *inst, 45610259SAndrew.Bardsley@arm.com (fragment->hasPaddr() ? "has paddr" : "no paddr"), 45710259SAndrew.Bardsley@arm.com (fragment->hasPaddr() ? fragment->getPaddr() : 0)); 45810259SAndrew.Bardsley@arm.com 45910259SAndrew.Bardsley@arm.com Addr fragment_addr = fragment->getVaddr(); 46010259SAndrew.Bardsley@arm.com unsigned int fragment_size = fragment->getSize(); 46110259SAndrew.Bardsley@arm.com 46210259SAndrew.Bardsley@arm.com uint8_t *request_data = NULL; 46310259SAndrew.Bardsley@arm.com 46410259SAndrew.Bardsley@arm.com if (!isLoad) { 46510259SAndrew.Bardsley@arm.com /* Split data for Packets. Will become the property of the 46610259SAndrew.Bardsley@arm.com * outgoing Packets */ 46710259SAndrew.Bardsley@arm.com request_data = new uint8_t[fragment_size]; 46810259SAndrew.Bardsley@arm.com std::memcpy(request_data, data + (fragment_addr - base_addr), 46910259SAndrew.Bardsley@arm.com fragment_size); 47010259SAndrew.Bardsley@arm.com } 47110259SAndrew.Bardsley@arm.com 47210259SAndrew.Bardsley@arm.com assert(fragment->hasPaddr()); 47310259SAndrew.Bardsley@arm.com 47410259SAndrew.Bardsley@arm.com PacketPtr fragment_packet = 47512749Sgiacomo.travaglini@arm.com makePacketForRequest(fragment, isLoad, this, request_data); 47610259SAndrew.Bardsley@arm.com 47710259SAndrew.Bardsley@arm.com fragmentPackets.push_back(fragment_packet); 47810368SAndrew.Bardsley@arm.com /* Accumulate flags in parent request */ 47912749Sgiacomo.travaglini@arm.com request->setFlags(fragment->getFlags()); 48010259SAndrew.Bardsley@arm.com } 48110259SAndrew.Bardsley@arm.com 48210259SAndrew.Bardsley@arm.com /* Might as well make the overall/response packet here */ 48310259SAndrew.Bardsley@arm.com /* Get the physical address for the whole request/packet from the first 48410259SAndrew.Bardsley@arm.com * fragment */ 48512749Sgiacomo.travaglini@arm.com request->setPaddr(fragmentRequests[0]->getPaddr()); 48610259SAndrew.Bardsley@arm.com makePacket(); 48710259SAndrew.Bardsley@arm.com} 48810259SAndrew.Bardsley@arm.com 48910259SAndrew.Bardsley@arm.comvoid 49010259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::startAddrTranslation() 49110259SAndrew.Bardsley@arm.com{ 49210259SAndrew.Bardsley@arm.com setState(LSQ::LSQRequest::InTranslation); 49310259SAndrew.Bardsley@arm.com 49410259SAndrew.Bardsley@arm.com makeFragmentRequests(); 49510259SAndrew.Bardsley@arm.com 49610259SAndrew.Bardsley@arm.com numInTranslationFragments = 0; 49710259SAndrew.Bardsley@arm.com numTranslatedFragments = 0; 49810259SAndrew.Bardsley@arm.com 49910259SAndrew.Bardsley@arm.com /* @todo, just do these in sequence for now with 50010259SAndrew.Bardsley@arm.com * a loop of: 50110259SAndrew.Bardsley@arm.com * do { 50210259SAndrew.Bardsley@arm.com * sendNextFragmentToTranslation ; translateTiming ; finish 50310259SAndrew.Bardsley@arm.com * } while (numTranslatedFragments != numFragments); 50410259SAndrew.Bardsley@arm.com */ 50510259SAndrew.Bardsley@arm.com 50610259SAndrew.Bardsley@arm.com /* Do first translation */ 50710259SAndrew.Bardsley@arm.com sendNextFragmentToTranslation(); 50810259SAndrew.Bardsley@arm.com} 50910259SAndrew.Bardsley@arm.com 51010259SAndrew.Bardsley@arm.comPacketPtr 51110259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::getHeadPacket() 51210259SAndrew.Bardsley@arm.com{ 51310259SAndrew.Bardsley@arm.com assert(numIssuedFragments < numFragments); 51410259SAndrew.Bardsley@arm.com 51510259SAndrew.Bardsley@arm.com return fragmentPackets[numIssuedFragments]; 51610259SAndrew.Bardsley@arm.com} 51710259SAndrew.Bardsley@arm.com 51810259SAndrew.Bardsley@arm.comvoid 51910259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::stepToNextPacket() 52010259SAndrew.Bardsley@arm.com{ 52110259SAndrew.Bardsley@arm.com assert(numIssuedFragments < numFragments); 52210259SAndrew.Bardsley@arm.com 52310259SAndrew.Bardsley@arm.com numIssuedFragments++; 52410259SAndrew.Bardsley@arm.com} 52510259SAndrew.Bardsley@arm.com 52610259SAndrew.Bardsley@arm.comvoid 52710259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::retireResponse(PacketPtr response) 52810259SAndrew.Bardsley@arm.com{ 52910259SAndrew.Bardsley@arm.com assert(numRetiredFragments < numFragments); 53010259SAndrew.Bardsley@arm.com 53110259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Retiring fragment addr: 0x%x size: %d" 53210259SAndrew.Bardsley@arm.com " offset: 0x%x (retired fragment num: %d) %s\n", 53310259SAndrew.Bardsley@arm.com response->req->getVaddr(), response->req->getSize(), 53412749Sgiacomo.travaglini@arm.com request->getVaddr() - response->req->getVaddr(), 53510259SAndrew.Bardsley@arm.com numRetiredFragments, 53610259SAndrew.Bardsley@arm.com (fault == NoFault ? "" : fault->name())); 53710259SAndrew.Bardsley@arm.com 53810259SAndrew.Bardsley@arm.com numRetiredFragments++; 53910259SAndrew.Bardsley@arm.com 54010259SAndrew.Bardsley@arm.com if (skipped) { 54110259SAndrew.Bardsley@arm.com /* Skip because we already knew the request had faulted or been 54210259SAndrew.Bardsley@arm.com * skipped */ 54310259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Skipping this fragment\n"); 54410259SAndrew.Bardsley@arm.com } else if (response->isError()) { 54510259SAndrew.Bardsley@arm.com /* Mark up the error and leave to execute to handle it */ 54610259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Fragment has an error, skipping\n"); 54710259SAndrew.Bardsley@arm.com setSkipped(); 54810259SAndrew.Bardsley@arm.com packet->copyError(response); 54910259SAndrew.Bardsley@arm.com } else { 55010259SAndrew.Bardsley@arm.com if (isLoad) { 55110259SAndrew.Bardsley@arm.com if (!data) { 55210259SAndrew.Bardsley@arm.com /* For a split transfer, a Packet must be constructed 55310259SAndrew.Bardsley@arm.com * to contain all returning data. This is that packet's 55410259SAndrew.Bardsley@arm.com * data */ 55512749Sgiacomo.travaglini@arm.com data = new uint8_t[request->getSize()]; 55610259SAndrew.Bardsley@arm.com } 55710259SAndrew.Bardsley@arm.com 55810259SAndrew.Bardsley@arm.com /* Populate the portion of the overall response data represented 55910259SAndrew.Bardsley@arm.com * by the response fragment */ 56010259SAndrew.Bardsley@arm.com std::memcpy( 56112749Sgiacomo.travaglini@arm.com data + (response->req->getVaddr() - request->getVaddr()), 56210563Sandreas.hansson@arm.com response->getConstPtr<uint8_t>(), 56310259SAndrew.Bardsley@arm.com response->req->getSize()); 56410259SAndrew.Bardsley@arm.com } 56510259SAndrew.Bardsley@arm.com } 56610259SAndrew.Bardsley@arm.com 56710259SAndrew.Bardsley@arm.com /* Complete early if we're skipping are no more in-flight accesses */ 56810259SAndrew.Bardsley@arm.com if (skipped && !hasPacketsInMemSystem()) { 56910259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Completed skipped burst\n"); 57010259SAndrew.Bardsley@arm.com setState(Complete); 57110259SAndrew.Bardsley@arm.com if (packet->needsResponse()) 57210259SAndrew.Bardsley@arm.com packet->makeResponse(); 57310259SAndrew.Bardsley@arm.com } 57410259SAndrew.Bardsley@arm.com 57510259SAndrew.Bardsley@arm.com if (numRetiredFragments == numFragments) 57610259SAndrew.Bardsley@arm.com setState(Complete); 57710259SAndrew.Bardsley@arm.com 57810259SAndrew.Bardsley@arm.com if (!skipped && isComplete()) { 57910259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Completed burst %d\n", packet != NULL); 58010259SAndrew.Bardsley@arm.com 58110259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Retired packet isRead: %d isWrite: %d" 58210259SAndrew.Bardsley@arm.com " needsResponse: %d packetSize: %s requestSize: %s responseSize:" 58310259SAndrew.Bardsley@arm.com " %s\n", packet->isRead(), packet->isWrite(), 58412749Sgiacomo.travaglini@arm.com packet->needsResponse(), packet->getSize(), request->getSize(), 58510259SAndrew.Bardsley@arm.com response->getSize()); 58610259SAndrew.Bardsley@arm.com 58710259SAndrew.Bardsley@arm.com /* A request can become complete by several paths, this is a sanity 58810259SAndrew.Bardsley@arm.com * check to make sure the packet's data is created */ 58910259SAndrew.Bardsley@arm.com if (!data) { 59012749Sgiacomo.travaglini@arm.com data = new uint8_t[request->getSize()]; 59110259SAndrew.Bardsley@arm.com } 59210259SAndrew.Bardsley@arm.com 59310259SAndrew.Bardsley@arm.com if (isLoad) { 59410259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Copying read data\n"); 59512749Sgiacomo.travaglini@arm.com std::memcpy(packet->getPtr<uint8_t>(), data, request->getSize()); 59610259SAndrew.Bardsley@arm.com } 59710259SAndrew.Bardsley@arm.com packet->makeResponse(); 59810259SAndrew.Bardsley@arm.com } 59910259SAndrew.Bardsley@arm.com 60010259SAndrew.Bardsley@arm.com /* Packets are all deallocated together in ~SplitLSQRequest */ 60110259SAndrew.Bardsley@arm.com} 60210259SAndrew.Bardsley@arm.com 60310259SAndrew.Bardsley@arm.comvoid 60410259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::sendNextFragmentToTranslation() 60510259SAndrew.Bardsley@arm.com{ 60610259SAndrew.Bardsley@arm.com unsigned int fragment_index = numTranslatedFragments; 60710259SAndrew.Bardsley@arm.com 60810259SAndrew.Bardsley@arm.com ThreadContext *thread = port.cpu.getContext( 60910259SAndrew.Bardsley@arm.com inst->id.threadId); 61010259SAndrew.Bardsley@arm.com 61110259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Submitting DTLB request for fragment: %d\n", 61210259SAndrew.Bardsley@arm.com fragment_index); 61310259SAndrew.Bardsley@arm.com 61410259SAndrew.Bardsley@arm.com port.numAccessesInDTLB++; 61510259SAndrew.Bardsley@arm.com numInTranslationFragments++; 61610259SAndrew.Bardsley@arm.com 61710259SAndrew.Bardsley@arm.com thread->getDTBPtr()->translateTiming( 61810259SAndrew.Bardsley@arm.com fragmentRequests[fragment_index], thread, this, (isLoad ? 61910259SAndrew.Bardsley@arm.com BaseTLB::Read : BaseTLB::Write)); 62010259SAndrew.Bardsley@arm.com} 62110259SAndrew.Bardsley@arm.com 62210259SAndrew.Bardsley@arm.combool 62310259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::canInsert() const 62410259SAndrew.Bardsley@arm.com{ 62510259SAndrew.Bardsley@arm.com /* @todo, support store amalgamation */ 62610259SAndrew.Bardsley@arm.com return slots.size() < numSlots; 62710259SAndrew.Bardsley@arm.com} 62810259SAndrew.Bardsley@arm.com 62910259SAndrew.Bardsley@arm.comvoid 63010259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::deleteRequest(LSQRequestPtr request) 63110259SAndrew.Bardsley@arm.com{ 63210259SAndrew.Bardsley@arm.com auto found = std::find(slots.begin(), slots.end(), request); 63310259SAndrew.Bardsley@arm.com 63410259SAndrew.Bardsley@arm.com if (found != slots.end()) { 63510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Deleting request: %s %s %s from StoreBuffer\n", 63610259SAndrew.Bardsley@arm.com request, *found, *(request->inst)); 63710259SAndrew.Bardsley@arm.com slots.erase(found); 63810259SAndrew.Bardsley@arm.com 63910259SAndrew.Bardsley@arm.com delete request; 64010259SAndrew.Bardsley@arm.com } 64110259SAndrew.Bardsley@arm.com} 64210259SAndrew.Bardsley@arm.com 64310259SAndrew.Bardsley@arm.comvoid 64410259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::insert(LSQRequestPtr request) 64510259SAndrew.Bardsley@arm.com{ 64610259SAndrew.Bardsley@arm.com if (!canInsert()) { 64710259SAndrew.Bardsley@arm.com warn("%s: store buffer insertion without space to insert from" 64810259SAndrew.Bardsley@arm.com " inst: %s\n", name(), *(request->inst)); 64910259SAndrew.Bardsley@arm.com } 65010259SAndrew.Bardsley@arm.com 65110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Pushing store: %s into store buffer\n", request); 65210259SAndrew.Bardsley@arm.com 65310259SAndrew.Bardsley@arm.com numUnissuedAccesses++; 65410259SAndrew.Bardsley@arm.com 65510259SAndrew.Bardsley@arm.com if (request->state != LSQRequest::Complete) 65610259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreInStoreBuffer); 65710259SAndrew.Bardsley@arm.com 65810259SAndrew.Bardsley@arm.com slots.push_back(request); 65910259SAndrew.Bardsley@arm.com 66010259SAndrew.Bardsley@arm.com /* Let's try and wake up the processor for the next cycle to step 66110259SAndrew.Bardsley@arm.com * the store buffer */ 66210259SAndrew.Bardsley@arm.com lsq.cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 66310259SAndrew.Bardsley@arm.com} 66410259SAndrew.Bardsley@arm.com 66510259SAndrew.Bardsley@arm.comLSQ::AddrRangeCoverage 66610259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::canForwardDataToLoad(LSQRequestPtr request, 66710259SAndrew.Bardsley@arm.com unsigned int &found_slot) 66810259SAndrew.Bardsley@arm.com{ 66910259SAndrew.Bardsley@arm.com unsigned int slot_index = slots.size() - 1; 67010259SAndrew.Bardsley@arm.com auto i = slots.rbegin(); 67110259SAndrew.Bardsley@arm.com AddrRangeCoverage ret = NoAddrRangeCoverage; 67210259SAndrew.Bardsley@arm.com 67310259SAndrew.Bardsley@arm.com /* Traverse the store buffer in reverse order (most to least recent) 67410259SAndrew.Bardsley@arm.com * and try to find a slot whose address range overlaps this request */ 67510259SAndrew.Bardsley@arm.com while (ret == NoAddrRangeCoverage && i != slots.rend()) { 67610259SAndrew.Bardsley@arm.com LSQRequestPtr slot = *i; 67710259SAndrew.Bardsley@arm.com 67812355Snikos.nikoleris@arm.com /* Cache maintenance instructions go down via the store path * 67912355Snikos.nikoleris@arm.com * but they carry no data and they shouldn't be considered for 68012355Snikos.nikoleris@arm.com * forwarding */ 68111567Smitch.hayenga@arm.com if (slot->packet && 68212355Snikos.nikoleris@arm.com slot->inst->id.threadId == request->inst->id.threadId && 68312355Snikos.nikoleris@arm.com !slot->packet->req->isCacheMaintenance()) { 68410259SAndrew.Bardsley@arm.com AddrRangeCoverage coverage = slot->containsAddrRangeOf(request); 68510259SAndrew.Bardsley@arm.com 68610259SAndrew.Bardsley@arm.com if (coverage != NoAddrRangeCoverage) { 68710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Forwarding: slot: %d result: %s thisAddr:" 68810259SAndrew.Bardsley@arm.com " 0x%x thisSize: %d slotAddr: 0x%x slotSize: %d\n", 68910259SAndrew.Bardsley@arm.com slot_index, coverage, 69012749Sgiacomo.travaglini@arm.com request->request->getPaddr(), request->request->getSize(), 69112749Sgiacomo.travaglini@arm.com slot->request->getPaddr(), slot->request->getSize()); 69210259SAndrew.Bardsley@arm.com 69310259SAndrew.Bardsley@arm.com found_slot = slot_index; 69410259SAndrew.Bardsley@arm.com ret = coverage; 69510259SAndrew.Bardsley@arm.com } 69610259SAndrew.Bardsley@arm.com } 69710259SAndrew.Bardsley@arm.com 69810259SAndrew.Bardsley@arm.com i++; 69910259SAndrew.Bardsley@arm.com slot_index--; 70010259SAndrew.Bardsley@arm.com } 70110259SAndrew.Bardsley@arm.com 70210259SAndrew.Bardsley@arm.com return ret; 70310259SAndrew.Bardsley@arm.com} 70410259SAndrew.Bardsley@arm.com 70510259SAndrew.Bardsley@arm.com/** Fill the given packet with appropriate date from slot slot_number */ 70610259SAndrew.Bardsley@arm.comvoid 70710259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::forwardStoreData(LSQRequestPtr load, 70810259SAndrew.Bardsley@arm.com unsigned int slot_number) 70910259SAndrew.Bardsley@arm.com{ 71010259SAndrew.Bardsley@arm.com assert(slot_number < slots.size()); 71110259SAndrew.Bardsley@arm.com assert(load->packet); 71210259SAndrew.Bardsley@arm.com assert(load->isLoad); 71310259SAndrew.Bardsley@arm.com 71410259SAndrew.Bardsley@arm.com LSQRequestPtr store = slots[slot_number]; 71510259SAndrew.Bardsley@arm.com 71610259SAndrew.Bardsley@arm.com assert(store->packet); 71710259SAndrew.Bardsley@arm.com assert(store->containsAddrRangeOf(load) == FullAddrRangeCoverage); 71810259SAndrew.Bardsley@arm.com 71912749Sgiacomo.travaglini@arm.com Addr load_addr = load->request->getPaddr(); 72012749Sgiacomo.travaglini@arm.com Addr store_addr = store->request->getPaddr(); 72110259SAndrew.Bardsley@arm.com Addr addr_offset = load_addr - store_addr; 72210259SAndrew.Bardsley@arm.com 72312749Sgiacomo.travaglini@arm.com unsigned int load_size = load->request->getSize(); 72410259SAndrew.Bardsley@arm.com 72510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Forwarding %d bytes for addr: 0x%x from store buffer" 72610259SAndrew.Bardsley@arm.com " slot: %d addr: 0x%x addressOffset: 0x%x\n", 72710259SAndrew.Bardsley@arm.com load_size, load_addr, slot_number, 72810259SAndrew.Bardsley@arm.com store_addr, addr_offset); 72910259SAndrew.Bardsley@arm.com 73010259SAndrew.Bardsley@arm.com void *load_packet_data = load->packet->getPtr<void>(); 73110259SAndrew.Bardsley@arm.com void *store_packet_data = store->packet->getPtr<uint8_t>() + addr_offset; 73210259SAndrew.Bardsley@arm.com 73310259SAndrew.Bardsley@arm.com std::memcpy(load_packet_data, store_packet_data, load_size); 73410259SAndrew.Bardsley@arm.com} 73510259SAndrew.Bardsley@arm.com 73610259SAndrew.Bardsley@arm.comvoid 73710581SAndrew.Bardsley@arm.comLSQ::StoreBuffer::countIssuedStore(LSQRequestPtr request) 73810581SAndrew.Bardsley@arm.com{ 73910581SAndrew.Bardsley@arm.com /* Barriers are accounted for as they are cleared from 74010581SAndrew.Bardsley@arm.com * the queue, not after their transfers are complete */ 74110581SAndrew.Bardsley@arm.com if (!request->isBarrier()) 74210581SAndrew.Bardsley@arm.com numUnissuedAccesses--; 74310581SAndrew.Bardsley@arm.com} 74410581SAndrew.Bardsley@arm.com 74510581SAndrew.Bardsley@arm.comvoid 74610259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::step() 74710259SAndrew.Bardsley@arm.com{ 74810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "StoreBuffer step numUnissuedAccesses: %d\n", 74910259SAndrew.Bardsley@arm.com numUnissuedAccesses); 75010259SAndrew.Bardsley@arm.com 75110259SAndrew.Bardsley@arm.com if (numUnissuedAccesses != 0 && lsq.state == LSQ::MemoryRunning) { 75210259SAndrew.Bardsley@arm.com /* Clear all the leading barriers */ 75310259SAndrew.Bardsley@arm.com while (!slots.empty() && 75410259SAndrew.Bardsley@arm.com slots.front()->isComplete() && slots.front()->isBarrier()) 75510259SAndrew.Bardsley@arm.com { 75610259SAndrew.Bardsley@arm.com LSQRequestPtr barrier = slots.front(); 75710259SAndrew.Bardsley@arm.com 75810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Clearing barrier for inst: %s\n", 75910259SAndrew.Bardsley@arm.com *(barrier->inst)); 76010259SAndrew.Bardsley@arm.com 76110259SAndrew.Bardsley@arm.com numUnissuedAccesses--; 76210259SAndrew.Bardsley@arm.com lsq.clearMemBarrier(barrier->inst); 76310259SAndrew.Bardsley@arm.com slots.pop_front(); 76410259SAndrew.Bardsley@arm.com 76510259SAndrew.Bardsley@arm.com delete barrier; 76610259SAndrew.Bardsley@arm.com } 76710259SAndrew.Bardsley@arm.com 76810259SAndrew.Bardsley@arm.com auto i = slots.begin(); 76910259SAndrew.Bardsley@arm.com bool issued = true; 77010259SAndrew.Bardsley@arm.com unsigned int issue_count = 0; 77110259SAndrew.Bardsley@arm.com 77210259SAndrew.Bardsley@arm.com /* Skip trying if the memory system is busy */ 77310259SAndrew.Bardsley@arm.com if (lsq.state == LSQ::MemoryNeedsRetry) 77410259SAndrew.Bardsley@arm.com issued = false; 77510259SAndrew.Bardsley@arm.com 77610259SAndrew.Bardsley@arm.com /* Try to issue all stores in order starting from the head 77710259SAndrew.Bardsley@arm.com * of the queue. Responses are allowed to be retired 77810259SAndrew.Bardsley@arm.com * out of order */ 77910259SAndrew.Bardsley@arm.com while (issued && 78010259SAndrew.Bardsley@arm.com issue_count < storeLimitPerCycle && 78110259SAndrew.Bardsley@arm.com lsq.canSendToMemorySystem() && 78210259SAndrew.Bardsley@arm.com i != slots.end()) 78310259SAndrew.Bardsley@arm.com { 78410259SAndrew.Bardsley@arm.com LSQRequestPtr request = *i; 78510259SAndrew.Bardsley@arm.com 78610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Considering request: %s, sentAllPackets: %d" 78710259SAndrew.Bardsley@arm.com " state: %s\n", 78810259SAndrew.Bardsley@arm.com *(request->inst), request->sentAllPackets(), 78910259SAndrew.Bardsley@arm.com request->state); 79010259SAndrew.Bardsley@arm.com 79110259SAndrew.Bardsley@arm.com if (request->isBarrier() && request->isComplete()) { 79210259SAndrew.Bardsley@arm.com /* Give up at barriers */ 79310259SAndrew.Bardsley@arm.com issued = false; 79410259SAndrew.Bardsley@arm.com } else if (!(request->state == LSQRequest::StoreBufferIssuing && 79510259SAndrew.Bardsley@arm.com request->sentAllPackets())) 79610259SAndrew.Bardsley@arm.com { 79710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Trying to send request: %s to memory" 79810259SAndrew.Bardsley@arm.com " system\n", *(request->inst)); 79910259SAndrew.Bardsley@arm.com 80010259SAndrew.Bardsley@arm.com if (lsq.tryToSend(request)) { 80110581SAndrew.Bardsley@arm.com countIssuedStore(request); 80210259SAndrew.Bardsley@arm.com issue_count++; 80310259SAndrew.Bardsley@arm.com } else { 80410259SAndrew.Bardsley@arm.com /* Don't step on to the next store buffer entry if this 80510259SAndrew.Bardsley@arm.com * one hasn't issued all its packets as the store 80610259SAndrew.Bardsley@arm.com * buffer must still enforce ordering */ 80710259SAndrew.Bardsley@arm.com issued = false; 80810259SAndrew.Bardsley@arm.com } 80910259SAndrew.Bardsley@arm.com } 81010259SAndrew.Bardsley@arm.com i++; 81110259SAndrew.Bardsley@arm.com } 81210259SAndrew.Bardsley@arm.com } 81310259SAndrew.Bardsley@arm.com} 81410259SAndrew.Bardsley@arm.com 81510259SAndrew.Bardsley@arm.comvoid 81610259SAndrew.Bardsley@arm.comLSQ::completeMemBarrierInst(MinorDynInstPtr inst, 81710259SAndrew.Bardsley@arm.com bool committed) 81810259SAndrew.Bardsley@arm.com{ 81910259SAndrew.Bardsley@arm.com if (committed) { 82010259SAndrew.Bardsley@arm.com /* Not already sent to the store buffer as a store request? */ 82110259SAndrew.Bardsley@arm.com if (!inst->inStoreBuffer) { 82210259SAndrew.Bardsley@arm.com /* Insert an entry into the store buffer to tick off barriers 82310259SAndrew.Bardsley@arm.com * until there are none in flight */ 82410259SAndrew.Bardsley@arm.com storeBuffer.insert(new BarrierDataRequest(*this, inst)); 82510259SAndrew.Bardsley@arm.com } 82610259SAndrew.Bardsley@arm.com } else { 82710259SAndrew.Bardsley@arm.com /* Clear the barrier anyway if it wasn't actually committed */ 82810259SAndrew.Bardsley@arm.com clearMemBarrier(inst); 82910259SAndrew.Bardsley@arm.com } 83010259SAndrew.Bardsley@arm.com} 83110259SAndrew.Bardsley@arm.com 83210259SAndrew.Bardsley@arm.comvoid 83310259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::minorTrace() const 83410259SAndrew.Bardsley@arm.com{ 83510259SAndrew.Bardsley@arm.com unsigned int size = slots.size(); 83610259SAndrew.Bardsley@arm.com unsigned int i = 0; 83710259SAndrew.Bardsley@arm.com std::ostringstream os; 83810259SAndrew.Bardsley@arm.com 83910259SAndrew.Bardsley@arm.com while (i < size) { 84010259SAndrew.Bardsley@arm.com LSQRequestPtr request = slots[i]; 84110259SAndrew.Bardsley@arm.com 84210259SAndrew.Bardsley@arm.com request->reportData(os); 84310259SAndrew.Bardsley@arm.com 84410259SAndrew.Bardsley@arm.com i++; 84510259SAndrew.Bardsley@arm.com if (i < numSlots) 84610259SAndrew.Bardsley@arm.com os << ','; 84710259SAndrew.Bardsley@arm.com } 84810259SAndrew.Bardsley@arm.com 84910259SAndrew.Bardsley@arm.com while (i < numSlots) { 85010259SAndrew.Bardsley@arm.com os << '-'; 85110259SAndrew.Bardsley@arm.com 85210259SAndrew.Bardsley@arm.com i++; 85310259SAndrew.Bardsley@arm.com if (i < numSlots) 85410259SAndrew.Bardsley@arm.com os << ','; 85510259SAndrew.Bardsley@arm.com } 85610259SAndrew.Bardsley@arm.com 85710259SAndrew.Bardsley@arm.com MINORTRACE("addr=%s num_unissued_stores=%d\n", os.str(), 85810259SAndrew.Bardsley@arm.com numUnissuedAccesses); 85910259SAndrew.Bardsley@arm.com} 86010259SAndrew.Bardsley@arm.com 86110259SAndrew.Bardsley@arm.comvoid 86210259SAndrew.Bardsley@arm.comLSQ::tryToSendToTransfers(LSQRequestPtr request) 86310259SAndrew.Bardsley@arm.com{ 86410259SAndrew.Bardsley@arm.com if (state == MemoryNeedsRetry) { 86510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request needs retry, not issuing to" 86610259SAndrew.Bardsley@arm.com " memory until retry arrives\n"); 86710259SAndrew.Bardsley@arm.com return; 86810259SAndrew.Bardsley@arm.com } 86910259SAndrew.Bardsley@arm.com 87010259SAndrew.Bardsley@arm.com if (request->state == LSQRequest::InTranslation) { 87110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request still in translation, not issuing to" 87210259SAndrew.Bardsley@arm.com " memory\n"); 87310259SAndrew.Bardsley@arm.com return; 87410259SAndrew.Bardsley@arm.com } 87510259SAndrew.Bardsley@arm.com 87610259SAndrew.Bardsley@arm.com assert(request->state == LSQRequest::Translated || 87710259SAndrew.Bardsley@arm.com request->state == LSQRequest::RequestIssuing || 87810259SAndrew.Bardsley@arm.com request->state == LSQRequest::Failed || 87910259SAndrew.Bardsley@arm.com request->state == LSQRequest::Complete); 88010259SAndrew.Bardsley@arm.com 88110259SAndrew.Bardsley@arm.com if (requests.empty() || requests.front() != request) { 88210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request not at front of requests queue, can't" 88310259SAndrew.Bardsley@arm.com " issue to memory\n"); 88410259SAndrew.Bardsley@arm.com return; 88510259SAndrew.Bardsley@arm.com } 88610259SAndrew.Bardsley@arm.com 88710259SAndrew.Bardsley@arm.com if (transfers.unreservedRemainingSpace() == 0) { 88810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "No space to insert request into transfers" 88910259SAndrew.Bardsley@arm.com " queue\n"); 89010259SAndrew.Bardsley@arm.com return; 89110259SAndrew.Bardsley@arm.com } 89210259SAndrew.Bardsley@arm.com 89310259SAndrew.Bardsley@arm.com if (request->isComplete() || request->state == LSQRequest::Failed) { 89410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Passing a %s transfer on to transfers" 89510259SAndrew.Bardsley@arm.com " queue\n", (request->isComplete() ? "completed" : "failed")); 89610259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 89710259SAndrew.Bardsley@arm.com request->setSkipped(); 89810259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 89910259SAndrew.Bardsley@arm.com return; 90010259SAndrew.Bardsley@arm.com } 90110259SAndrew.Bardsley@arm.com 90210259SAndrew.Bardsley@arm.com if (!execute.instIsRightStream(request->inst)) { 90310259SAndrew.Bardsley@arm.com /* Wrong stream, try to abort the transfer but only do so if 90410259SAndrew.Bardsley@arm.com * there are no packets in flight */ 90510259SAndrew.Bardsley@arm.com if (request->hasPacketsInMemSystem()) { 90610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request's inst. is from the wrong stream," 90710259SAndrew.Bardsley@arm.com " waiting for responses before aborting request\n"); 90810259SAndrew.Bardsley@arm.com } else { 90910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request's inst. is from the wrong stream," 91010259SAndrew.Bardsley@arm.com " aborting request\n"); 91110259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 91210259SAndrew.Bardsley@arm.com request->setSkipped(); 91310259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 91410259SAndrew.Bardsley@arm.com } 91510259SAndrew.Bardsley@arm.com return; 91610259SAndrew.Bardsley@arm.com } 91710259SAndrew.Bardsley@arm.com 91810259SAndrew.Bardsley@arm.com if (request->fault != NoFault) { 91910259SAndrew.Bardsley@arm.com if (request->inst->staticInst->isPrefetch()) { 92010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Not signalling fault for faulting prefetch\n"); 92110259SAndrew.Bardsley@arm.com } 92210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Moving faulting request into the transfers" 92310259SAndrew.Bardsley@arm.com " queue\n"); 92410259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 92510259SAndrew.Bardsley@arm.com request->setSkipped(); 92610259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 92710259SAndrew.Bardsley@arm.com return; 92810259SAndrew.Bardsley@arm.com } 92910259SAndrew.Bardsley@arm.com 93010259SAndrew.Bardsley@arm.com bool is_load = request->isLoad; 93112749Sgiacomo.travaglini@arm.com bool is_llsc = request->request->isLLSC(); 93212749Sgiacomo.travaglini@arm.com bool is_swap = request->request->isSwap(); 93312749Sgiacomo.travaglini@arm.com bool bufferable = !(request->request->isStrictlyOrdered() || 93410259SAndrew.Bardsley@arm.com is_llsc || is_swap); 93510259SAndrew.Bardsley@arm.com 93610259SAndrew.Bardsley@arm.com if (is_load) { 93710259SAndrew.Bardsley@arm.com if (numStoresInTransfers != 0) { 93810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Load request with stores still in transfers" 93910259SAndrew.Bardsley@arm.com " queue, stalling\n"); 94010259SAndrew.Bardsley@arm.com return; 94110259SAndrew.Bardsley@arm.com } 94210259SAndrew.Bardsley@arm.com } else { 94310259SAndrew.Bardsley@arm.com /* Store. Can it be sent to the store buffer? */ 94412749Sgiacomo.travaglini@arm.com if (bufferable && !request->request->isMmappedIpr()) { 94510259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreToStoreBuffer); 94610259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 94710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Moving store into transfers queue\n"); 94810259SAndrew.Bardsley@arm.com return; 94910259SAndrew.Bardsley@arm.com } 95010259SAndrew.Bardsley@arm.com } 95110259SAndrew.Bardsley@arm.com 95210259SAndrew.Bardsley@arm.com /* Check if this is the head instruction (and so must be executable as 95310259SAndrew.Bardsley@arm.com * its stream sequence number was checked above) for loads which must 95410259SAndrew.Bardsley@arm.com * not be speculatively issued and stores which must be issued here */ 95510259SAndrew.Bardsley@arm.com if (!bufferable) { 95610259SAndrew.Bardsley@arm.com if (!execute.instIsHeadInst(request->inst)) { 95710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Memory access not the head inst., can't be" 95810259SAndrew.Bardsley@arm.com " sure it can be performed, not issuing\n"); 95910259SAndrew.Bardsley@arm.com return; 96010259SAndrew.Bardsley@arm.com } 96110259SAndrew.Bardsley@arm.com 96210259SAndrew.Bardsley@arm.com unsigned int forwarding_slot = 0; 96310259SAndrew.Bardsley@arm.com 96410259SAndrew.Bardsley@arm.com if (storeBuffer.canForwardDataToLoad(request, forwarding_slot) != 96510259SAndrew.Bardsley@arm.com NoAddrRangeCoverage) 96610259SAndrew.Bardsley@arm.com { 96710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Memory access can receive forwarded data" 96810259SAndrew.Bardsley@arm.com " from the store buffer, need to wait for store buffer to" 96910259SAndrew.Bardsley@arm.com " drain\n"); 97010259SAndrew.Bardsley@arm.com return; 97110259SAndrew.Bardsley@arm.com } 97210259SAndrew.Bardsley@arm.com } 97310259SAndrew.Bardsley@arm.com 97410259SAndrew.Bardsley@arm.com /* True: submit this packet to the transfers queue to be sent to the 97510259SAndrew.Bardsley@arm.com * memory system. 97610259SAndrew.Bardsley@arm.com * False: skip the memory and push a packet for this request onto 97710259SAndrew.Bardsley@arm.com * requests */ 97810259SAndrew.Bardsley@arm.com bool do_access = true; 97910259SAndrew.Bardsley@arm.com 98010259SAndrew.Bardsley@arm.com if (!is_llsc) { 98110259SAndrew.Bardsley@arm.com /* Check for match in the store buffer */ 98210259SAndrew.Bardsley@arm.com if (is_load) { 98310259SAndrew.Bardsley@arm.com unsigned int forwarding_slot = 0; 98410259SAndrew.Bardsley@arm.com AddrRangeCoverage forwarding_result = 98510259SAndrew.Bardsley@arm.com storeBuffer.canForwardDataToLoad(request, 98610259SAndrew.Bardsley@arm.com forwarding_slot); 98710259SAndrew.Bardsley@arm.com 98810259SAndrew.Bardsley@arm.com switch (forwarding_result) { 98910259SAndrew.Bardsley@arm.com case FullAddrRangeCoverage: 99010259SAndrew.Bardsley@arm.com /* Forward data from the store buffer into this request and 99110259SAndrew.Bardsley@arm.com * repurpose this request's packet into a response packet */ 99210259SAndrew.Bardsley@arm.com storeBuffer.forwardStoreData(request, forwarding_slot); 99310259SAndrew.Bardsley@arm.com request->packet->makeResponse(); 99410259SAndrew.Bardsley@arm.com 99510259SAndrew.Bardsley@arm.com /* Just move between queues, no access */ 99610259SAndrew.Bardsley@arm.com do_access = false; 99710259SAndrew.Bardsley@arm.com break; 99810259SAndrew.Bardsley@arm.com case PartialAddrRangeCoverage: 99910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Load partly satisfied by store buffer" 100010259SAndrew.Bardsley@arm.com " data. Must wait for the store to complete\n"); 100110259SAndrew.Bardsley@arm.com return; 100210259SAndrew.Bardsley@arm.com break; 100310259SAndrew.Bardsley@arm.com case NoAddrRangeCoverage: 100410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "No forwardable data from store buffer\n"); 100510259SAndrew.Bardsley@arm.com /* Fall through to try access */ 100610259SAndrew.Bardsley@arm.com break; 100710259SAndrew.Bardsley@arm.com } 100810259SAndrew.Bardsley@arm.com } 100910259SAndrew.Bardsley@arm.com } else { 101010259SAndrew.Bardsley@arm.com if (!canSendToMemorySystem()) { 101110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Can't send request to memory system yet\n"); 101210259SAndrew.Bardsley@arm.com return; 101310259SAndrew.Bardsley@arm.com } 101410259SAndrew.Bardsley@arm.com 101510259SAndrew.Bardsley@arm.com SimpleThread &thread = *cpu.threads[request->inst->id.threadId]; 101610259SAndrew.Bardsley@arm.com 101710259SAndrew.Bardsley@arm.com TheISA::PCState old_pc = thread.pcState(); 101810259SAndrew.Bardsley@arm.com ExecContext context(cpu, thread, execute, request->inst); 101910259SAndrew.Bardsley@arm.com 102010259SAndrew.Bardsley@arm.com /* Handle LLSC requests and tests */ 102110259SAndrew.Bardsley@arm.com if (is_load) { 102212749Sgiacomo.travaglini@arm.com TheISA::handleLockedRead(&context, request->request); 102310259SAndrew.Bardsley@arm.com } else { 102410259SAndrew.Bardsley@arm.com do_access = TheISA::handleLockedWrite(&context, 102512749Sgiacomo.travaglini@arm.com request->request, cacheBlockMask); 102610259SAndrew.Bardsley@arm.com 102710259SAndrew.Bardsley@arm.com if (!do_access) { 102810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Not perfoming a memory " 102910259SAndrew.Bardsley@arm.com "access for store conditional\n"); 103010259SAndrew.Bardsley@arm.com } 103110259SAndrew.Bardsley@arm.com } 103210259SAndrew.Bardsley@arm.com thread.pcState(old_pc); 103310259SAndrew.Bardsley@arm.com } 103410259SAndrew.Bardsley@arm.com 103510259SAndrew.Bardsley@arm.com /* See the do_access comment above */ 103610259SAndrew.Bardsley@arm.com if (do_access) { 103710259SAndrew.Bardsley@arm.com if (!canSendToMemorySystem()) { 103810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Can't send request to memory system yet\n"); 103910259SAndrew.Bardsley@arm.com return; 104010259SAndrew.Bardsley@arm.com } 104110259SAndrew.Bardsley@arm.com 104210259SAndrew.Bardsley@arm.com /* Remember if this is an access which can't be idly 104310259SAndrew.Bardsley@arm.com * discarded by an interrupt */ 104410368SAndrew.Bardsley@arm.com if (!bufferable && !request->issuedToMemory) { 104510259SAndrew.Bardsley@arm.com numAccessesIssuedToMemory++; 104610259SAndrew.Bardsley@arm.com request->issuedToMemory = true; 104710259SAndrew.Bardsley@arm.com } 104810259SAndrew.Bardsley@arm.com 104911567Smitch.hayenga@arm.com if (tryToSend(request)) { 105010259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 105111567Smitch.hayenga@arm.com } 105210259SAndrew.Bardsley@arm.com } else { 105310259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 105410259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 105510259SAndrew.Bardsley@arm.com } 105610259SAndrew.Bardsley@arm.com} 105710259SAndrew.Bardsley@arm.com 105810259SAndrew.Bardsley@arm.combool 105910259SAndrew.Bardsley@arm.comLSQ::tryToSend(LSQRequestPtr request) 106010259SAndrew.Bardsley@arm.com{ 106110259SAndrew.Bardsley@arm.com bool ret = false; 106210259SAndrew.Bardsley@arm.com 106310259SAndrew.Bardsley@arm.com if (!canSendToMemorySystem()) { 106410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Can't send request: %s yet, no space in memory\n", 106510259SAndrew.Bardsley@arm.com *(request->inst)); 106610259SAndrew.Bardsley@arm.com } else { 106710259SAndrew.Bardsley@arm.com PacketPtr packet = request->getHeadPacket(); 106810259SAndrew.Bardsley@arm.com 106910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Trying to send request: %s addr: 0x%x\n", 107010259SAndrew.Bardsley@arm.com *(request->inst), packet->req->getVaddr()); 107110259SAndrew.Bardsley@arm.com 107210259SAndrew.Bardsley@arm.com /* The sender state of the packet *must* be an LSQRequest 107310259SAndrew.Bardsley@arm.com * so the response can be correctly handled */ 107410259SAndrew.Bardsley@arm.com assert(packet->findNextSenderState<LSQRequest>()); 107510259SAndrew.Bardsley@arm.com 107612749Sgiacomo.travaglini@arm.com if (request->request->isMmappedIpr()) { 107710259SAndrew.Bardsley@arm.com ThreadContext *thread = 107811435Smitch.hayenga@arm.com cpu.getContext(cpu.contextToThread( 107912749Sgiacomo.travaglini@arm.com request->request->contextId())); 108010259SAndrew.Bardsley@arm.com 108110259SAndrew.Bardsley@arm.com if (request->isLoad) { 108210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "IPR read inst: %s\n", *(request->inst)); 108310259SAndrew.Bardsley@arm.com TheISA::handleIprRead(thread, packet); 108410259SAndrew.Bardsley@arm.com } else { 108510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "IPR write inst: %s\n", *(request->inst)); 108610259SAndrew.Bardsley@arm.com TheISA::handleIprWrite(thread, packet); 108710259SAndrew.Bardsley@arm.com } 108810259SAndrew.Bardsley@arm.com 108910259SAndrew.Bardsley@arm.com request->stepToNextPacket(); 109010259SAndrew.Bardsley@arm.com ret = request->sentAllPackets(); 109110259SAndrew.Bardsley@arm.com 109210259SAndrew.Bardsley@arm.com if (!ret) { 109310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "IPR access has another packet: %s\n", 109410259SAndrew.Bardsley@arm.com *(request->inst)); 109510259SAndrew.Bardsley@arm.com } 109610259SAndrew.Bardsley@arm.com 109710259SAndrew.Bardsley@arm.com if (ret) 109810259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 109910259SAndrew.Bardsley@arm.com else 110010259SAndrew.Bardsley@arm.com request->setState(LSQRequest::RequestIssuing); 110110259SAndrew.Bardsley@arm.com } else if (dcachePort.sendTimingReq(packet)) { 110210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Sent data memory request\n"); 110310259SAndrew.Bardsley@arm.com 110410259SAndrew.Bardsley@arm.com numAccessesInMemorySystem++; 110510259SAndrew.Bardsley@arm.com 110610259SAndrew.Bardsley@arm.com request->stepToNextPacket(); 110710259SAndrew.Bardsley@arm.com 110810259SAndrew.Bardsley@arm.com ret = request->sentAllPackets(); 110910259SAndrew.Bardsley@arm.com 111010259SAndrew.Bardsley@arm.com switch (request->state) { 111110259SAndrew.Bardsley@arm.com case LSQRequest::Translated: 111210259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 111310259SAndrew.Bardsley@arm.com /* Fully or partially issued a request in the transfers 111410259SAndrew.Bardsley@arm.com * queue */ 111510259SAndrew.Bardsley@arm.com request->setState(LSQRequest::RequestIssuing); 111610259SAndrew.Bardsley@arm.com break; 111710259SAndrew.Bardsley@arm.com case LSQRequest::StoreInStoreBuffer: 111810259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 111910259SAndrew.Bardsley@arm.com /* Fully or partially issued a request in the store 112010259SAndrew.Bardsley@arm.com * buffer */ 112110259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreBufferIssuing); 112210259SAndrew.Bardsley@arm.com break; 112310259SAndrew.Bardsley@arm.com default: 112410259SAndrew.Bardsley@arm.com assert(false); 112510259SAndrew.Bardsley@arm.com break; 112610259SAndrew.Bardsley@arm.com } 112710259SAndrew.Bardsley@arm.com 112810259SAndrew.Bardsley@arm.com state = MemoryRunning; 112910259SAndrew.Bardsley@arm.com } else { 113010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, 113110259SAndrew.Bardsley@arm.com "Sending data memory request - needs retry\n"); 113210259SAndrew.Bardsley@arm.com 113310259SAndrew.Bardsley@arm.com /* Needs to be resent, wait for that */ 113410259SAndrew.Bardsley@arm.com state = MemoryNeedsRetry; 113510259SAndrew.Bardsley@arm.com retryRequest = request; 113610259SAndrew.Bardsley@arm.com 113710259SAndrew.Bardsley@arm.com switch (request->state) { 113810259SAndrew.Bardsley@arm.com case LSQRequest::Translated: 113910259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 114010259SAndrew.Bardsley@arm.com request->setState(LSQRequest::RequestNeedsRetry); 114110259SAndrew.Bardsley@arm.com break; 114210259SAndrew.Bardsley@arm.com case LSQRequest::StoreInStoreBuffer: 114310259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 114410259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreBufferNeedsRetry); 114510259SAndrew.Bardsley@arm.com break; 114610259SAndrew.Bardsley@arm.com default: 114710259SAndrew.Bardsley@arm.com assert(false); 114810259SAndrew.Bardsley@arm.com break; 114910259SAndrew.Bardsley@arm.com } 115010259SAndrew.Bardsley@arm.com } 115110259SAndrew.Bardsley@arm.com } 115210259SAndrew.Bardsley@arm.com 115311567Smitch.hayenga@arm.com if (ret) 115411567Smitch.hayenga@arm.com threadSnoop(request); 115511567Smitch.hayenga@arm.com 115610259SAndrew.Bardsley@arm.com return ret; 115710259SAndrew.Bardsley@arm.com} 115810259SAndrew.Bardsley@arm.com 115910259SAndrew.Bardsley@arm.comvoid 116010259SAndrew.Bardsley@arm.comLSQ::moveFromRequestsToTransfers(LSQRequestPtr request) 116110259SAndrew.Bardsley@arm.com{ 116210259SAndrew.Bardsley@arm.com assert(!requests.empty() && requests.front() == request); 116310259SAndrew.Bardsley@arm.com assert(transfers.unreservedRemainingSpace() != 0); 116410259SAndrew.Bardsley@arm.com 116510259SAndrew.Bardsley@arm.com /* Need to count the number of stores in the transfers 116610259SAndrew.Bardsley@arm.com * queue so that loads know when their store buffer forwarding 116710259SAndrew.Bardsley@arm.com * results will be correct (only when all those stores 116810259SAndrew.Bardsley@arm.com * have reached the store buffer) */ 116910259SAndrew.Bardsley@arm.com if (!request->isLoad) 117010259SAndrew.Bardsley@arm.com numStoresInTransfers++; 117110259SAndrew.Bardsley@arm.com 117210259SAndrew.Bardsley@arm.com requests.pop(); 117310259SAndrew.Bardsley@arm.com transfers.push(request); 117410259SAndrew.Bardsley@arm.com} 117510259SAndrew.Bardsley@arm.com 117610259SAndrew.Bardsley@arm.combool 117710259SAndrew.Bardsley@arm.comLSQ::canSendToMemorySystem() 117810259SAndrew.Bardsley@arm.com{ 117910259SAndrew.Bardsley@arm.com return state == MemoryRunning && 118010259SAndrew.Bardsley@arm.com numAccessesInMemorySystem < inMemorySystemLimit; 118110259SAndrew.Bardsley@arm.com} 118210259SAndrew.Bardsley@arm.com 118310259SAndrew.Bardsley@arm.combool 118410259SAndrew.Bardsley@arm.comLSQ::recvTimingResp(PacketPtr response) 118510259SAndrew.Bardsley@arm.com{ 118610259SAndrew.Bardsley@arm.com LSQRequestPtr request = 118710259SAndrew.Bardsley@arm.com safe_cast<LSQRequestPtr>(response->popSenderState()); 118810259SAndrew.Bardsley@arm.com 118910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Received response packet inst: %s" 119010259SAndrew.Bardsley@arm.com " addr: 0x%x cmd: %s\n", 119110259SAndrew.Bardsley@arm.com *(request->inst), response->getAddr(), 119210259SAndrew.Bardsley@arm.com response->cmd.toString()); 119310259SAndrew.Bardsley@arm.com 119410259SAndrew.Bardsley@arm.com numAccessesInMemorySystem--; 119510259SAndrew.Bardsley@arm.com 119610259SAndrew.Bardsley@arm.com if (response->isError()) { 119710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Received error response packet: %s\n", 119810259SAndrew.Bardsley@arm.com *request->inst); 119910259SAndrew.Bardsley@arm.com } 120010259SAndrew.Bardsley@arm.com 120110259SAndrew.Bardsley@arm.com switch (request->state) { 120210259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 120310259SAndrew.Bardsley@arm.com case LSQRequest::RequestNeedsRetry: 120410259SAndrew.Bardsley@arm.com /* Response to a request from the transfers queue */ 120510259SAndrew.Bardsley@arm.com request->retireResponse(response); 120610259SAndrew.Bardsley@arm.com 120710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Has outstanding packets?: %d %d\n", 120810259SAndrew.Bardsley@arm.com request->hasPacketsInMemSystem(), request->isComplete()); 120910259SAndrew.Bardsley@arm.com 121010259SAndrew.Bardsley@arm.com break; 121110259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 121210259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferNeedsRetry: 121310259SAndrew.Bardsley@arm.com /* Response to a request from the store buffer */ 121410259SAndrew.Bardsley@arm.com request->retireResponse(response); 121510259SAndrew.Bardsley@arm.com 121610581SAndrew.Bardsley@arm.com /* Remove completed requests unless they are barriers (which will 121710259SAndrew.Bardsley@arm.com * need to be removed in order */ 121810259SAndrew.Bardsley@arm.com if (request->isComplete()) { 121910259SAndrew.Bardsley@arm.com if (!request->isBarrier()) { 122010259SAndrew.Bardsley@arm.com storeBuffer.deleteRequest(request); 122110259SAndrew.Bardsley@arm.com } else { 122210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Completed transfer for barrier: %s" 122310259SAndrew.Bardsley@arm.com " leaving the request as it is also a barrier\n", 122410259SAndrew.Bardsley@arm.com *(request->inst)); 122510259SAndrew.Bardsley@arm.com } 122610259SAndrew.Bardsley@arm.com } 122710259SAndrew.Bardsley@arm.com break; 122810259SAndrew.Bardsley@arm.com default: 122910259SAndrew.Bardsley@arm.com /* Shouldn't be allowed to receive a response from another 123010259SAndrew.Bardsley@arm.com * state */ 123110259SAndrew.Bardsley@arm.com assert(false); 123210259SAndrew.Bardsley@arm.com break; 123310259SAndrew.Bardsley@arm.com } 123410259SAndrew.Bardsley@arm.com 123510259SAndrew.Bardsley@arm.com /* We go to idle even if there are more things in the requests queue 123610259SAndrew.Bardsley@arm.com * as it's the job of step to actually step us on to the next 123710259SAndrew.Bardsley@arm.com * transaction */ 123810259SAndrew.Bardsley@arm.com 123910259SAndrew.Bardsley@arm.com /* Let's try and wake up the processor for the next cycle */ 124010259SAndrew.Bardsley@arm.com cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 124110259SAndrew.Bardsley@arm.com 124210259SAndrew.Bardsley@arm.com /* Never busy */ 124310259SAndrew.Bardsley@arm.com return true; 124410259SAndrew.Bardsley@arm.com} 124510259SAndrew.Bardsley@arm.com 124610259SAndrew.Bardsley@arm.comvoid 124710713Sandreas.hansson@arm.comLSQ::recvReqRetry() 124810259SAndrew.Bardsley@arm.com{ 124910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Received retry request\n"); 125010259SAndrew.Bardsley@arm.com 125110259SAndrew.Bardsley@arm.com assert(state == MemoryNeedsRetry); 125210259SAndrew.Bardsley@arm.com 125310259SAndrew.Bardsley@arm.com switch (retryRequest->state) { 125410259SAndrew.Bardsley@arm.com case LSQRequest::RequestNeedsRetry: 125510259SAndrew.Bardsley@arm.com /* Retry in the requests queue */ 125610259SAndrew.Bardsley@arm.com retryRequest->setState(LSQRequest::Translated); 125710259SAndrew.Bardsley@arm.com break; 125810259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferNeedsRetry: 125910259SAndrew.Bardsley@arm.com /* Retry in the store buffer */ 126010259SAndrew.Bardsley@arm.com retryRequest->setState(LSQRequest::StoreInStoreBuffer); 126110259SAndrew.Bardsley@arm.com break; 126210259SAndrew.Bardsley@arm.com default: 126310259SAndrew.Bardsley@arm.com assert(false); 126410259SAndrew.Bardsley@arm.com } 126510259SAndrew.Bardsley@arm.com 126610259SAndrew.Bardsley@arm.com /* Set state back to MemoryRunning so that the following 126710259SAndrew.Bardsley@arm.com * tryToSend can actually send. Note that this won't 126810259SAndrew.Bardsley@arm.com * allow another transfer in as tryToSend should 126910259SAndrew.Bardsley@arm.com * issue a memory request and either succeed for this 127010259SAndrew.Bardsley@arm.com * request or return the LSQ back to MemoryNeedsRetry */ 127110259SAndrew.Bardsley@arm.com state = MemoryRunning; 127210259SAndrew.Bardsley@arm.com 127310259SAndrew.Bardsley@arm.com /* Try to resend the request */ 127410259SAndrew.Bardsley@arm.com if (tryToSend(retryRequest)) { 127510259SAndrew.Bardsley@arm.com /* Successfully sent, need to move the request */ 127610259SAndrew.Bardsley@arm.com switch (retryRequest->state) { 127710259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 127810259SAndrew.Bardsley@arm.com /* In the requests queue */ 127910259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(retryRequest); 128010259SAndrew.Bardsley@arm.com break; 128110259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 128210259SAndrew.Bardsley@arm.com /* In the store buffer */ 128310581SAndrew.Bardsley@arm.com storeBuffer.countIssuedStore(retryRequest); 128410259SAndrew.Bardsley@arm.com break; 128510259SAndrew.Bardsley@arm.com default: 128610259SAndrew.Bardsley@arm.com assert(false); 128710259SAndrew.Bardsley@arm.com break; 128810259SAndrew.Bardsley@arm.com } 128910647Sandreas.hansson@arm.com 129010647Sandreas.hansson@arm.com retryRequest = NULL; 129110259SAndrew.Bardsley@arm.com } 129210259SAndrew.Bardsley@arm.com} 129310259SAndrew.Bardsley@arm.com 129410259SAndrew.Bardsley@arm.comLSQ::LSQ(std::string name_, std::string dcache_port_name_, 129510259SAndrew.Bardsley@arm.com MinorCPU &cpu_, Execute &execute_, 129610259SAndrew.Bardsley@arm.com unsigned int in_memory_system_limit, unsigned int line_width, 129710259SAndrew.Bardsley@arm.com unsigned int requests_queue_size, unsigned int transfers_queue_size, 129810259SAndrew.Bardsley@arm.com unsigned int store_buffer_size, 129910259SAndrew.Bardsley@arm.com unsigned int store_buffer_cycle_store_limit) : 130010259SAndrew.Bardsley@arm.com Named(name_), 130110259SAndrew.Bardsley@arm.com cpu(cpu_), 130210259SAndrew.Bardsley@arm.com execute(execute_), 130310259SAndrew.Bardsley@arm.com dcachePort(dcache_port_name_, *this, cpu_), 130411567Smitch.hayenga@arm.com lastMemBarrier(cpu.numThreads, 0), 130510259SAndrew.Bardsley@arm.com state(MemoryRunning), 130610259SAndrew.Bardsley@arm.com inMemorySystemLimit(in_memory_system_limit), 130710259SAndrew.Bardsley@arm.com lineWidth((line_width == 0 ? cpu.cacheLineSize() : line_width)), 130810259SAndrew.Bardsley@arm.com requests(name_ + ".requests", "addr", requests_queue_size), 130910259SAndrew.Bardsley@arm.com transfers(name_ + ".transfers", "addr", transfers_queue_size), 131010259SAndrew.Bardsley@arm.com storeBuffer(name_ + ".storeBuffer", 131110259SAndrew.Bardsley@arm.com *this, store_buffer_size, store_buffer_cycle_store_limit), 131210259SAndrew.Bardsley@arm.com numAccessesInMemorySystem(0), 131310259SAndrew.Bardsley@arm.com numAccessesInDTLB(0), 131410259SAndrew.Bardsley@arm.com numStoresInTransfers(0), 131510259SAndrew.Bardsley@arm.com numAccessesIssuedToMemory(0), 131610259SAndrew.Bardsley@arm.com retryRequest(NULL), 131710259SAndrew.Bardsley@arm.com cacheBlockMask(~(cpu_.cacheLineSize() - 1)) 131810259SAndrew.Bardsley@arm.com{ 131910259SAndrew.Bardsley@arm.com if (in_memory_system_limit < 1) { 132010259SAndrew.Bardsley@arm.com fatal("%s: executeMaxAccessesInMemory must be >= 1 (%d)\n", name_, 132110259SAndrew.Bardsley@arm.com in_memory_system_limit); 132210259SAndrew.Bardsley@arm.com } 132310259SAndrew.Bardsley@arm.com 132410259SAndrew.Bardsley@arm.com if (store_buffer_cycle_store_limit < 1) { 132510259SAndrew.Bardsley@arm.com fatal("%s: executeLSQMaxStoreBufferStoresPerCycle must be" 132610259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, store_buffer_cycle_store_limit); 132710259SAndrew.Bardsley@arm.com } 132810259SAndrew.Bardsley@arm.com 132910259SAndrew.Bardsley@arm.com if (requests_queue_size < 1) { 133010259SAndrew.Bardsley@arm.com fatal("%s: executeLSQRequestsQueueSize must be" 133110259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, requests_queue_size); 133210259SAndrew.Bardsley@arm.com } 133310259SAndrew.Bardsley@arm.com 133410259SAndrew.Bardsley@arm.com if (transfers_queue_size < 1) { 133510259SAndrew.Bardsley@arm.com fatal("%s: executeLSQTransfersQueueSize must be" 133610259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, transfers_queue_size); 133710259SAndrew.Bardsley@arm.com } 133810259SAndrew.Bardsley@arm.com 133910259SAndrew.Bardsley@arm.com if (store_buffer_size < 1) { 134010259SAndrew.Bardsley@arm.com fatal("%s: executeLSQStoreBufferSize must be" 134110259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, store_buffer_size); 134210259SAndrew.Bardsley@arm.com } 134310259SAndrew.Bardsley@arm.com 134410259SAndrew.Bardsley@arm.com if ((lineWidth & (lineWidth - 1)) != 0) { 134510259SAndrew.Bardsley@arm.com fatal("%s: lineWidth: %d must be a power of 2\n", name(), lineWidth); 134610259SAndrew.Bardsley@arm.com } 134710259SAndrew.Bardsley@arm.com} 134810259SAndrew.Bardsley@arm.com 134910259SAndrew.Bardsley@arm.comLSQ::~LSQ() 135010259SAndrew.Bardsley@arm.com{ } 135110259SAndrew.Bardsley@arm.com 135210259SAndrew.Bardsley@arm.comLSQ::LSQRequest::~LSQRequest() 135310259SAndrew.Bardsley@arm.com{ 135410259SAndrew.Bardsley@arm.com if (packet) 135510259SAndrew.Bardsley@arm.com delete packet; 135610259SAndrew.Bardsley@arm.com if (data) 135710259SAndrew.Bardsley@arm.com delete [] data; 135810259SAndrew.Bardsley@arm.com} 135910259SAndrew.Bardsley@arm.com 136010259SAndrew.Bardsley@arm.com/** 136110259SAndrew.Bardsley@arm.com * Step the memory access mechanism on to its next state. In reality, most 136210259SAndrew.Bardsley@arm.com * of the stepping is done by the callbacks on the LSQ but this 136310259SAndrew.Bardsley@arm.com * function is responsible for issuing memory requests lodged in the 136410259SAndrew.Bardsley@arm.com * requests queue. 136510259SAndrew.Bardsley@arm.com */ 136610259SAndrew.Bardsley@arm.comvoid 136710259SAndrew.Bardsley@arm.comLSQ::step() 136810259SAndrew.Bardsley@arm.com{ 136910259SAndrew.Bardsley@arm.com /* Try to move address-translated requests between queues and issue 137010259SAndrew.Bardsley@arm.com * them */ 137110259SAndrew.Bardsley@arm.com if (!requests.empty()) 137210259SAndrew.Bardsley@arm.com tryToSendToTransfers(requests.front()); 137310259SAndrew.Bardsley@arm.com 137410259SAndrew.Bardsley@arm.com storeBuffer.step(); 137510259SAndrew.Bardsley@arm.com} 137610259SAndrew.Bardsley@arm.com 137710259SAndrew.Bardsley@arm.comLSQ::LSQRequestPtr 137810259SAndrew.Bardsley@arm.comLSQ::findResponse(MinorDynInstPtr inst) 137910259SAndrew.Bardsley@arm.com{ 138010259SAndrew.Bardsley@arm.com LSQ::LSQRequestPtr ret = NULL; 138110259SAndrew.Bardsley@arm.com 138210259SAndrew.Bardsley@arm.com if (!transfers.empty()) { 138310259SAndrew.Bardsley@arm.com LSQRequestPtr request = transfers.front(); 138410259SAndrew.Bardsley@arm.com 138510259SAndrew.Bardsley@arm.com /* Same instruction and complete access or a store that's 138610259SAndrew.Bardsley@arm.com * capable of being moved to the store buffer */ 138710259SAndrew.Bardsley@arm.com if (request->inst->id == inst->id) { 138810504SAndrew.Bardsley@arm.com bool complete = request->isComplete(); 138910504SAndrew.Bardsley@arm.com bool can_store = storeBuffer.canInsert(); 139010504SAndrew.Bardsley@arm.com bool to_store_buffer = request->state == 139110504SAndrew.Bardsley@arm.com LSQRequest::StoreToStoreBuffer; 139210504SAndrew.Bardsley@arm.com 139310504SAndrew.Bardsley@arm.com if ((complete && !(request->isBarrier() && !can_store)) || 139410504SAndrew.Bardsley@arm.com (to_store_buffer && can_store)) 139510259SAndrew.Bardsley@arm.com { 139610259SAndrew.Bardsley@arm.com ret = request; 139710259SAndrew.Bardsley@arm.com } 139810259SAndrew.Bardsley@arm.com } 139910259SAndrew.Bardsley@arm.com } 140010259SAndrew.Bardsley@arm.com 140110259SAndrew.Bardsley@arm.com if (ret) { 140210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Found matching memory response for inst: %s\n", 140310259SAndrew.Bardsley@arm.com *inst); 140410259SAndrew.Bardsley@arm.com } else { 140510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "No matching memory response for inst: %s\n", 140610259SAndrew.Bardsley@arm.com *inst); 140710259SAndrew.Bardsley@arm.com } 140810259SAndrew.Bardsley@arm.com 140910259SAndrew.Bardsley@arm.com return ret; 141010259SAndrew.Bardsley@arm.com} 141110259SAndrew.Bardsley@arm.com 141210259SAndrew.Bardsley@arm.comvoid 141310259SAndrew.Bardsley@arm.comLSQ::popResponse(LSQ::LSQRequestPtr response) 141410259SAndrew.Bardsley@arm.com{ 141510259SAndrew.Bardsley@arm.com assert(!transfers.empty() && transfers.front() == response); 141610259SAndrew.Bardsley@arm.com 141710259SAndrew.Bardsley@arm.com transfers.pop(); 141810259SAndrew.Bardsley@arm.com 141910259SAndrew.Bardsley@arm.com if (!response->isLoad) 142010259SAndrew.Bardsley@arm.com numStoresInTransfers--; 142110259SAndrew.Bardsley@arm.com 142210259SAndrew.Bardsley@arm.com if (response->issuedToMemory) 142310259SAndrew.Bardsley@arm.com numAccessesIssuedToMemory--; 142410259SAndrew.Bardsley@arm.com 142510259SAndrew.Bardsley@arm.com if (response->state != LSQRequest::StoreInStoreBuffer) { 142610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Deleting %s request: %s\n", 142710259SAndrew.Bardsley@arm.com (response->isLoad ? "load" : "store"), 142810259SAndrew.Bardsley@arm.com *(response->inst)); 142910259SAndrew.Bardsley@arm.com 143010259SAndrew.Bardsley@arm.com delete response; 143110259SAndrew.Bardsley@arm.com } 143210259SAndrew.Bardsley@arm.com} 143310259SAndrew.Bardsley@arm.com 143410259SAndrew.Bardsley@arm.comvoid 143510259SAndrew.Bardsley@arm.comLSQ::sendStoreToStoreBuffer(LSQRequestPtr request) 143610259SAndrew.Bardsley@arm.com{ 143710259SAndrew.Bardsley@arm.com assert(request->state == LSQRequest::StoreToStoreBuffer); 143810259SAndrew.Bardsley@arm.com 143910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Sending store: %s to store buffer\n", 144010259SAndrew.Bardsley@arm.com *(request->inst)); 144110259SAndrew.Bardsley@arm.com 144210259SAndrew.Bardsley@arm.com request->inst->inStoreBuffer = true; 144310259SAndrew.Bardsley@arm.com 144410259SAndrew.Bardsley@arm.com storeBuffer.insert(request); 144510259SAndrew.Bardsley@arm.com} 144610259SAndrew.Bardsley@arm.com 144710259SAndrew.Bardsley@arm.combool 144810259SAndrew.Bardsley@arm.comLSQ::isDrained() 144910259SAndrew.Bardsley@arm.com{ 145010259SAndrew.Bardsley@arm.com return requests.empty() && transfers.empty() && 145110259SAndrew.Bardsley@arm.com storeBuffer.isDrained(); 145210259SAndrew.Bardsley@arm.com} 145310259SAndrew.Bardsley@arm.com 145410259SAndrew.Bardsley@arm.combool 145510259SAndrew.Bardsley@arm.comLSQ::needsToTick() 145610259SAndrew.Bardsley@arm.com{ 145710259SAndrew.Bardsley@arm.com bool ret = false; 145810259SAndrew.Bardsley@arm.com 145910259SAndrew.Bardsley@arm.com if (canSendToMemorySystem()) { 146010259SAndrew.Bardsley@arm.com bool have_translated_requests = !requests.empty() && 146110259SAndrew.Bardsley@arm.com requests.front()->state != LSQRequest::InTranslation && 146210259SAndrew.Bardsley@arm.com transfers.unreservedRemainingSpace() != 0; 146310259SAndrew.Bardsley@arm.com 146410259SAndrew.Bardsley@arm.com ret = have_translated_requests || 146510259SAndrew.Bardsley@arm.com storeBuffer.numUnissuedStores() != 0; 146610259SAndrew.Bardsley@arm.com } 146710259SAndrew.Bardsley@arm.com 146810259SAndrew.Bardsley@arm.com if (ret) 146910259SAndrew.Bardsley@arm.com DPRINTF(Activity, "Need to tick\n"); 147010259SAndrew.Bardsley@arm.com 147110259SAndrew.Bardsley@arm.com return ret; 147210259SAndrew.Bardsley@arm.com} 147310259SAndrew.Bardsley@arm.com 147410259SAndrew.Bardsley@arm.comvoid 147510259SAndrew.Bardsley@arm.comLSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, 147611608Snikos.nikoleris@arm.com unsigned int size, Addr addr, Request::Flags flags, 147711608Snikos.nikoleris@arm.com uint64_t *res) 147810259SAndrew.Bardsley@arm.com{ 147910259SAndrew.Bardsley@arm.com bool needs_burst = transferNeedsBurst(addr, size, lineWidth); 148010259SAndrew.Bardsley@arm.com LSQRequestPtr request; 148110259SAndrew.Bardsley@arm.com 148210259SAndrew.Bardsley@arm.com /* Copy given data into the request. The request will pass this to the 148310259SAndrew.Bardsley@arm.com * packet and then it will own the data */ 148410259SAndrew.Bardsley@arm.com uint8_t *request_data = NULL; 148510259SAndrew.Bardsley@arm.com 148610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Pushing request (%s) addr: 0x%x size: %d flags:" 148710259SAndrew.Bardsley@arm.com " 0x%x%s lineWidth : 0x%x\n", 148810259SAndrew.Bardsley@arm.com (isLoad ? "load" : "store"), addr, size, flags, 148910259SAndrew.Bardsley@arm.com (needs_burst ? " (needs burst)" : ""), lineWidth); 149010259SAndrew.Bardsley@arm.com 149110259SAndrew.Bardsley@arm.com if (!isLoad) { 149210259SAndrew.Bardsley@arm.com /* request_data becomes the property of a ...DataRequest (see below) 149310259SAndrew.Bardsley@arm.com * and destroyed by its destructor */ 149410259SAndrew.Bardsley@arm.com request_data = new uint8_t[size]; 149512355Snikos.nikoleris@arm.com if (flags & Request::STORE_NO_DATA) { 149610259SAndrew.Bardsley@arm.com /* For cache zeroing, just use zeroed data */ 149710259SAndrew.Bardsley@arm.com std::memset(request_data, 0, size); 149810259SAndrew.Bardsley@arm.com } else { 149910259SAndrew.Bardsley@arm.com std::memcpy(request_data, data, size); 150010259SAndrew.Bardsley@arm.com } 150110259SAndrew.Bardsley@arm.com } 150210259SAndrew.Bardsley@arm.com 150310259SAndrew.Bardsley@arm.com if (needs_burst) { 150410259SAndrew.Bardsley@arm.com request = new SplitDataRequest( 150510259SAndrew.Bardsley@arm.com *this, inst, isLoad, request_data, res); 150610259SAndrew.Bardsley@arm.com } else { 150710259SAndrew.Bardsley@arm.com request = new SingleDataRequest( 150810259SAndrew.Bardsley@arm.com *this, inst, isLoad, request_data, res); 150910259SAndrew.Bardsley@arm.com } 151010259SAndrew.Bardsley@arm.com 151110259SAndrew.Bardsley@arm.com if (inst->traceData) 151210665SAli.Saidi@ARM.com inst->traceData->setMem(addr, size, flags); 151310259SAndrew.Bardsley@arm.com 151411148Smitch.hayenga@arm.com int cid = cpu.threads[inst->id.threadId]->getTC()->contextId(); 151512749Sgiacomo.travaglini@arm.com request->request->setContext(cid); 151612749Sgiacomo.travaglini@arm.com request->request->setVirt(0 /* asid */, 151710634Slukefahr@umich.edu addr, size, flags, cpu.dataMasterId(), 151810259SAndrew.Bardsley@arm.com /* I've no idea why we need the PC, but give it */ 151910259SAndrew.Bardsley@arm.com inst->pc.instAddr()); 152010259SAndrew.Bardsley@arm.com 152110259SAndrew.Bardsley@arm.com requests.push(request); 152210259SAndrew.Bardsley@arm.com request->startAddrTranslation(); 152310259SAndrew.Bardsley@arm.com} 152410259SAndrew.Bardsley@arm.com 152510259SAndrew.Bardsley@arm.comvoid 152610259SAndrew.Bardsley@arm.comLSQ::pushFailedRequest(MinorDynInstPtr inst) 152710259SAndrew.Bardsley@arm.com{ 152810259SAndrew.Bardsley@arm.com LSQRequestPtr request = new FailedDataRequest(*this, inst); 152910259SAndrew.Bardsley@arm.com requests.push(request); 153010259SAndrew.Bardsley@arm.com} 153110259SAndrew.Bardsley@arm.com 153210259SAndrew.Bardsley@arm.comvoid 153310259SAndrew.Bardsley@arm.comLSQ::minorTrace() const 153410259SAndrew.Bardsley@arm.com{ 153510259SAndrew.Bardsley@arm.com MINORTRACE("state=%s in_tlb_mem=%d/%d stores_in_transfers=%d" 153610259SAndrew.Bardsley@arm.com " lastMemBarrier=%d\n", 153710259SAndrew.Bardsley@arm.com state, numAccessesInDTLB, numAccessesInMemorySystem, 153811567Smitch.hayenga@arm.com numStoresInTransfers, lastMemBarrier[0]); 153910259SAndrew.Bardsley@arm.com requests.minorTrace(); 154010259SAndrew.Bardsley@arm.com transfers.minorTrace(); 154110259SAndrew.Bardsley@arm.com storeBuffer.minorTrace(); 154210259SAndrew.Bardsley@arm.com} 154310259SAndrew.Bardsley@arm.com 154410259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::StoreBuffer(std::string name_, LSQ &lsq_, 154510259SAndrew.Bardsley@arm.com unsigned int store_buffer_size, 154610259SAndrew.Bardsley@arm.com unsigned int store_limit_per_cycle) : 154710259SAndrew.Bardsley@arm.com Named(name_), lsq(lsq_), 154810259SAndrew.Bardsley@arm.com numSlots(store_buffer_size), 154910259SAndrew.Bardsley@arm.com storeLimitPerCycle(store_limit_per_cycle), 155010259SAndrew.Bardsley@arm.com slots(), 155110259SAndrew.Bardsley@arm.com numUnissuedAccesses(0) 155210259SAndrew.Bardsley@arm.com{ 155310259SAndrew.Bardsley@arm.com} 155410259SAndrew.Bardsley@arm.com 155510259SAndrew.Bardsley@arm.comPacketPtr 155612749Sgiacomo.travaglini@arm.commakePacketForRequest(const RequestPtr &request, bool isLoad, 155710259SAndrew.Bardsley@arm.com Packet::SenderState *sender_state, PacketDataPtr data) 155810259SAndrew.Bardsley@arm.com{ 155912749Sgiacomo.travaglini@arm.com PacketPtr ret = isLoad ? Packet::createRead(request) 156012749Sgiacomo.travaglini@arm.com : Packet::createWrite(request); 156110259SAndrew.Bardsley@arm.com 156210259SAndrew.Bardsley@arm.com if (sender_state) 156310259SAndrew.Bardsley@arm.com ret->pushSenderState(sender_state); 156410259SAndrew.Bardsley@arm.com 156512355Snikos.nikoleris@arm.com if (isLoad) { 156610259SAndrew.Bardsley@arm.com ret->allocate(); 156712749Sgiacomo.travaglini@arm.com } else if (!request->isCacheMaintenance()) { 156812355Snikos.nikoleris@arm.com // CMOs are treated as stores but they don't have data. All 156912355Snikos.nikoleris@arm.com // stores otherwise need to allocate for data. 157010566Sandreas.hansson@arm.com ret->dataDynamic(data); 157112355Snikos.nikoleris@arm.com } 157210259SAndrew.Bardsley@arm.com 157310259SAndrew.Bardsley@arm.com return ret; 157410259SAndrew.Bardsley@arm.com} 157510259SAndrew.Bardsley@arm.com 157610259SAndrew.Bardsley@arm.comvoid 157710259SAndrew.Bardsley@arm.comLSQ::issuedMemBarrierInst(MinorDynInstPtr inst) 157810259SAndrew.Bardsley@arm.com{ 157910259SAndrew.Bardsley@arm.com assert(inst->isInst() && inst->staticInst->isMemBarrier()); 158011567Smitch.hayenga@arm.com assert(inst->id.execSeqNum > lastMemBarrier[inst->id.threadId]); 158110259SAndrew.Bardsley@arm.com 158210259SAndrew.Bardsley@arm.com /* Remember the barrier. We only have a notion of one 158310259SAndrew.Bardsley@arm.com * barrier so this may result in some mem refs being 158410259SAndrew.Bardsley@arm.com * delayed if they are between barriers */ 158511567Smitch.hayenga@arm.com lastMemBarrier[inst->id.threadId] = inst->id.execSeqNum; 158610259SAndrew.Bardsley@arm.com} 158710259SAndrew.Bardsley@arm.com 158810259SAndrew.Bardsley@arm.comvoid 158910259SAndrew.Bardsley@arm.comLSQ::LSQRequest::makePacket() 159010259SAndrew.Bardsley@arm.com{ 159110259SAndrew.Bardsley@arm.com /* Make the function idempotent */ 159210259SAndrew.Bardsley@arm.com if (packet) 159310259SAndrew.Bardsley@arm.com return; 159410259SAndrew.Bardsley@arm.com 159511056Sandreas.hansson@arm.com // if the translation faulted, do not create a packet 159611056Sandreas.hansson@arm.com if (fault != NoFault) { 159711056Sandreas.hansson@arm.com assert(packet == NULL); 159811056Sandreas.hansson@arm.com return; 159911056Sandreas.hansson@arm.com } 160011056Sandreas.hansson@arm.com 160110259SAndrew.Bardsley@arm.com packet = makePacketForRequest(request, isLoad, this, data); 160210259SAndrew.Bardsley@arm.com /* Null the ret data so we know not to deallocate it when the 160310259SAndrew.Bardsley@arm.com * ret is destroyed. The data now belongs to the ret and 160410259SAndrew.Bardsley@arm.com * the ret is responsible for its destruction */ 160510259SAndrew.Bardsley@arm.com data = NULL; 160610259SAndrew.Bardsley@arm.com} 160710259SAndrew.Bardsley@arm.com 160810259SAndrew.Bardsley@arm.comstd::ostream & 160910259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, LSQ::MemoryState state) 161010259SAndrew.Bardsley@arm.com{ 161110259SAndrew.Bardsley@arm.com switch (state) { 161210259SAndrew.Bardsley@arm.com case LSQ::MemoryRunning: 161310259SAndrew.Bardsley@arm.com os << "MemoryRunning"; 161410259SAndrew.Bardsley@arm.com break; 161510259SAndrew.Bardsley@arm.com case LSQ::MemoryNeedsRetry: 161610259SAndrew.Bardsley@arm.com os << "MemoryNeedsRetry"; 161710259SAndrew.Bardsley@arm.com break; 161810259SAndrew.Bardsley@arm.com default: 161910259SAndrew.Bardsley@arm.com os << "MemoryState-" << static_cast<int>(state); 162010259SAndrew.Bardsley@arm.com break; 162110259SAndrew.Bardsley@arm.com } 162210259SAndrew.Bardsley@arm.com return os; 162310259SAndrew.Bardsley@arm.com} 162410259SAndrew.Bardsley@arm.com 162510259SAndrew.Bardsley@arm.comvoid 162610259SAndrew.Bardsley@arm.comLSQ::recvTimingSnoopReq(PacketPtr pkt) 162710259SAndrew.Bardsley@arm.com{ 162810259SAndrew.Bardsley@arm.com /* LLSC operations in Minor can't be speculative and are executed from 162910259SAndrew.Bardsley@arm.com * the head of the requests queue. We shouldn't need to do more than 163010259SAndrew.Bardsley@arm.com * this action on snoops. */ 163111567Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 163211567Smitch.hayenga@arm.com if (cpu.getCpuAddrMonitor(tid)->doMonitor(pkt)) { 163311567Smitch.hayenga@arm.com cpu.wakeup(tid); 163411567Smitch.hayenga@arm.com } 163511567Smitch.hayenga@arm.com } 163610259SAndrew.Bardsley@arm.com 163711356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 163811567Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 163911567Smitch.hayenga@arm.com TheISA::handleLockedSnoop(cpu.getContext(tid), pkt, 164011567Smitch.hayenga@arm.com cacheBlockMask); 164111567Smitch.hayenga@arm.com } 164211567Smitch.hayenga@arm.com } 164311567Smitch.hayenga@arm.com} 164411567Smitch.hayenga@arm.com 164511567Smitch.hayenga@arm.comvoid 164611567Smitch.hayenga@arm.comLSQ::threadSnoop(LSQRequestPtr request) 164711567Smitch.hayenga@arm.com{ 164811567Smitch.hayenga@arm.com /* LLSC operations in Minor can't be speculative and are executed from 164911567Smitch.hayenga@arm.com * the head of the requests queue. We shouldn't need to do more than 165011567Smitch.hayenga@arm.com * this action on snoops. */ 165111567Smitch.hayenga@arm.com ThreadID req_tid = request->inst->id.threadId; 165211567Smitch.hayenga@arm.com PacketPtr pkt = request->packet; 165311567Smitch.hayenga@arm.com 165411567Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 165511567Smitch.hayenga@arm.com if (tid != req_tid) { 165611567Smitch.hayenga@arm.com if (cpu.getCpuAddrMonitor(tid)->doMonitor(pkt)) { 165711567Smitch.hayenga@arm.com cpu.wakeup(tid); 165811567Smitch.hayenga@arm.com } 165911567Smitch.hayenga@arm.com 166011567Smitch.hayenga@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 166111567Smitch.hayenga@arm.com TheISA::handleLockedSnoop(cpu.getContext(tid), pkt, 166211567Smitch.hayenga@arm.com cacheBlockMask); 166311567Smitch.hayenga@arm.com } 166411567Smitch.hayenga@arm.com } 166511356Skrinat01@arm.com } 166610259SAndrew.Bardsley@arm.com} 166710259SAndrew.Bardsley@arm.com 166810259SAndrew.Bardsley@arm.com} 1669