lsq.cc revision 12355
110259SAndrew.Bardsley@arm.com/* 212355Snikos.nikoleris@arm.com * Copyright (c) 2013-2014,2017 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1510259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1610259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 1710259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 1810259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1910259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2010259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2110259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2210259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2310259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2410259SAndrew.Bardsley@arm.com * 2510259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610259SAndrew.Bardsley@arm.com * 3710259SAndrew.Bardsley@arm.com * Authors: Andrew Bardsley 3810259SAndrew.Bardsley@arm.com */ 3910259SAndrew.Bardsley@arm.com 4011793Sbrandon.potter@amd.com#include "cpu/minor/lsq.hh" 4111793Sbrandon.potter@amd.com 4210259SAndrew.Bardsley@arm.com#include <iomanip> 4310259SAndrew.Bardsley@arm.com#include <sstream> 4410259SAndrew.Bardsley@arm.com 4510259SAndrew.Bardsley@arm.com#include "arch/locked_mem.hh" 4610259SAndrew.Bardsley@arm.com#include "arch/mmapped_ipr.hh" 4710259SAndrew.Bardsley@arm.com#include "cpu/minor/cpu.hh" 4810259SAndrew.Bardsley@arm.com#include "cpu/minor/exec_context.hh" 4910259SAndrew.Bardsley@arm.com#include "cpu/minor/execute.hh" 5010259SAndrew.Bardsley@arm.com#include "cpu/minor/pipeline.hh" 5110259SAndrew.Bardsley@arm.com#include "debug/Activity.hh" 5210259SAndrew.Bardsley@arm.com#include "debug/MinorMem.hh" 5310259SAndrew.Bardsley@arm.com 5410259SAndrew.Bardsley@arm.comnamespace Minor 5510259SAndrew.Bardsley@arm.com{ 5610259SAndrew.Bardsley@arm.com 5710259SAndrew.Bardsley@arm.com/** Returns the offset of addr into an aligned a block of size block_size */ 5810259SAndrew.Bardsley@arm.comstatic Addr 5910259SAndrew.Bardsley@arm.comaddrBlockOffset(Addr addr, unsigned int block_size) 6010259SAndrew.Bardsley@arm.com{ 6110259SAndrew.Bardsley@arm.com return addr & (block_size - 1); 6210259SAndrew.Bardsley@arm.com} 6310259SAndrew.Bardsley@arm.com 6410259SAndrew.Bardsley@arm.com/** Returns true if the given [addr .. addr+size-1] transfer needs to be 6510259SAndrew.Bardsley@arm.com * fragmented across a block size of block_size */ 6610259SAndrew.Bardsley@arm.comstatic bool 6710259SAndrew.Bardsley@arm.comtransferNeedsBurst(Addr addr, unsigned int size, unsigned int block_size) 6810259SAndrew.Bardsley@arm.com{ 6910259SAndrew.Bardsley@arm.com return (addrBlockOffset(addr, block_size) + size) > block_size; 7010259SAndrew.Bardsley@arm.com} 7110259SAndrew.Bardsley@arm.com 7210259SAndrew.Bardsley@arm.comLSQ::LSQRequest::LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_, 7310259SAndrew.Bardsley@arm.com PacketDataPtr data_, uint64_t *res_) : 7410259SAndrew.Bardsley@arm.com SenderState(), 7510259SAndrew.Bardsley@arm.com port(port_), 7610259SAndrew.Bardsley@arm.com inst(inst_), 7710259SAndrew.Bardsley@arm.com isLoad(isLoad_), 7810259SAndrew.Bardsley@arm.com data(data_), 7910259SAndrew.Bardsley@arm.com packet(NULL), 8010259SAndrew.Bardsley@arm.com request(), 8110259SAndrew.Bardsley@arm.com fault(NoFault), 8210259SAndrew.Bardsley@arm.com res(res_), 8310259SAndrew.Bardsley@arm.com skipped(false), 8410259SAndrew.Bardsley@arm.com issuedToMemory(false), 8510259SAndrew.Bardsley@arm.com state(NotIssued) 8610259SAndrew.Bardsley@arm.com{ } 8710259SAndrew.Bardsley@arm.com 8810259SAndrew.Bardsley@arm.comLSQ::AddrRangeCoverage 8910259SAndrew.Bardsley@arm.comLSQ::LSQRequest::containsAddrRangeOf( 9010259SAndrew.Bardsley@arm.com Addr req1_addr, unsigned int req1_size, 9110259SAndrew.Bardsley@arm.com Addr req2_addr, unsigned int req2_size) 9210259SAndrew.Bardsley@arm.com{ 9310259SAndrew.Bardsley@arm.com /* 'end' here means the address of the byte just past the request 9410259SAndrew.Bardsley@arm.com * blocks */ 9510259SAndrew.Bardsley@arm.com Addr req2_end_addr = req2_addr + req2_size; 9610259SAndrew.Bardsley@arm.com Addr req1_end_addr = req1_addr + req1_size; 9710259SAndrew.Bardsley@arm.com 9810259SAndrew.Bardsley@arm.com AddrRangeCoverage ret; 9910259SAndrew.Bardsley@arm.com 10012179Spau.cabre@metempsy.com if (req1_addr >= req2_end_addr || req1_end_addr <= req2_addr) 10110259SAndrew.Bardsley@arm.com ret = NoAddrRangeCoverage; 10210259SAndrew.Bardsley@arm.com else if (req1_addr <= req2_addr && req1_end_addr >= req2_end_addr) 10310259SAndrew.Bardsley@arm.com ret = FullAddrRangeCoverage; 10410259SAndrew.Bardsley@arm.com else 10510259SAndrew.Bardsley@arm.com ret = PartialAddrRangeCoverage; 10610259SAndrew.Bardsley@arm.com 10710259SAndrew.Bardsley@arm.com return ret; 10810259SAndrew.Bardsley@arm.com} 10910259SAndrew.Bardsley@arm.com 11010259SAndrew.Bardsley@arm.comLSQ::AddrRangeCoverage 11110259SAndrew.Bardsley@arm.comLSQ::LSQRequest::containsAddrRangeOf(LSQRequestPtr other_request) 11210259SAndrew.Bardsley@arm.com{ 11310259SAndrew.Bardsley@arm.com return containsAddrRangeOf(request.getPaddr(), request.getSize(), 11410259SAndrew.Bardsley@arm.com other_request->request.getPaddr(), other_request->request.getSize()); 11510259SAndrew.Bardsley@arm.com} 11610259SAndrew.Bardsley@arm.com 11710259SAndrew.Bardsley@arm.combool 11810259SAndrew.Bardsley@arm.comLSQ::LSQRequest::isBarrier() 11910259SAndrew.Bardsley@arm.com{ 12010259SAndrew.Bardsley@arm.com return inst->isInst() && inst->staticInst->isMemBarrier(); 12110259SAndrew.Bardsley@arm.com} 12210259SAndrew.Bardsley@arm.com 12310259SAndrew.Bardsley@arm.combool 12410259SAndrew.Bardsley@arm.comLSQ::LSQRequest::needsToBeSentToStoreBuffer() 12510259SAndrew.Bardsley@arm.com{ 12610259SAndrew.Bardsley@arm.com return state == StoreToStoreBuffer; 12710259SAndrew.Bardsley@arm.com} 12810259SAndrew.Bardsley@arm.com 12910259SAndrew.Bardsley@arm.comvoid 13010259SAndrew.Bardsley@arm.comLSQ::LSQRequest::setState(LSQRequestState new_state) 13110259SAndrew.Bardsley@arm.com{ 13210259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Setting state from %d to %d for request:" 13310259SAndrew.Bardsley@arm.com " %s\n", state, new_state, *inst); 13410259SAndrew.Bardsley@arm.com state = new_state; 13510259SAndrew.Bardsley@arm.com} 13610259SAndrew.Bardsley@arm.com 13710259SAndrew.Bardsley@arm.combool 13810259SAndrew.Bardsley@arm.comLSQ::LSQRequest::isComplete() const 13910259SAndrew.Bardsley@arm.com{ 14010259SAndrew.Bardsley@arm.com /* @todo, There is currently only one 'completed' state. This 14110259SAndrew.Bardsley@arm.com * may not be a good choice */ 14210259SAndrew.Bardsley@arm.com return state == Complete; 14310259SAndrew.Bardsley@arm.com} 14410259SAndrew.Bardsley@arm.com 14510259SAndrew.Bardsley@arm.comvoid 14610259SAndrew.Bardsley@arm.comLSQ::LSQRequest::reportData(std::ostream &os) const 14710259SAndrew.Bardsley@arm.com{ 14810259SAndrew.Bardsley@arm.com os << (isLoad ? 'R' : 'W') << ';'; 14910259SAndrew.Bardsley@arm.com inst->reportData(os); 15010259SAndrew.Bardsley@arm.com os << ';' << state; 15110259SAndrew.Bardsley@arm.com} 15210259SAndrew.Bardsley@arm.com 15310259SAndrew.Bardsley@arm.comstd::ostream & 15410259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, LSQ::AddrRangeCoverage coverage) 15510259SAndrew.Bardsley@arm.com{ 15610259SAndrew.Bardsley@arm.com switch (coverage) { 15710259SAndrew.Bardsley@arm.com case LSQ::PartialAddrRangeCoverage: 15810259SAndrew.Bardsley@arm.com os << "PartialAddrRangeCoverage"; 15910259SAndrew.Bardsley@arm.com break; 16010259SAndrew.Bardsley@arm.com case LSQ::FullAddrRangeCoverage: 16110259SAndrew.Bardsley@arm.com os << "FullAddrRangeCoverage"; 16210259SAndrew.Bardsley@arm.com break; 16310259SAndrew.Bardsley@arm.com case LSQ::NoAddrRangeCoverage: 16410259SAndrew.Bardsley@arm.com os << "NoAddrRangeCoverage"; 16510259SAndrew.Bardsley@arm.com break; 16610259SAndrew.Bardsley@arm.com default: 16710259SAndrew.Bardsley@arm.com os << "AddrRangeCoverage-" << static_cast<int>(coverage); 16810259SAndrew.Bardsley@arm.com break; 16910259SAndrew.Bardsley@arm.com } 17010259SAndrew.Bardsley@arm.com return os; 17110259SAndrew.Bardsley@arm.com} 17210259SAndrew.Bardsley@arm.com 17310259SAndrew.Bardsley@arm.comstd::ostream & 17410259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, LSQ::LSQRequest::LSQRequestState state) 17510259SAndrew.Bardsley@arm.com{ 17610259SAndrew.Bardsley@arm.com switch (state) { 17710259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::NotIssued: 17810259SAndrew.Bardsley@arm.com os << "NotIssued"; 17910259SAndrew.Bardsley@arm.com break; 18010259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::InTranslation: 18110259SAndrew.Bardsley@arm.com os << "InTranslation"; 18210259SAndrew.Bardsley@arm.com break; 18310259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::Translated: 18410259SAndrew.Bardsley@arm.com os << "Translated"; 18510259SAndrew.Bardsley@arm.com break; 18610259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::Failed: 18710259SAndrew.Bardsley@arm.com os << "Failed"; 18810259SAndrew.Bardsley@arm.com break; 18910259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::RequestIssuing: 19010259SAndrew.Bardsley@arm.com os << "RequestIssuing"; 19110259SAndrew.Bardsley@arm.com break; 19210259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreToStoreBuffer: 19310259SAndrew.Bardsley@arm.com os << "StoreToStoreBuffer"; 19410259SAndrew.Bardsley@arm.com break; 19510259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreInStoreBuffer: 19610259SAndrew.Bardsley@arm.com os << "StoreInStoreBuffer"; 19710259SAndrew.Bardsley@arm.com break; 19810259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreBufferIssuing: 19910259SAndrew.Bardsley@arm.com os << "StoreBufferIssuing"; 20010259SAndrew.Bardsley@arm.com break; 20110259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::RequestNeedsRetry: 20210259SAndrew.Bardsley@arm.com os << "RequestNeedsRetry"; 20310259SAndrew.Bardsley@arm.com break; 20410259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreBufferNeedsRetry: 20510259SAndrew.Bardsley@arm.com os << "StoreBufferNeedsRetry"; 20610259SAndrew.Bardsley@arm.com break; 20710259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::Complete: 20810259SAndrew.Bardsley@arm.com os << "Complete"; 20910259SAndrew.Bardsley@arm.com break; 21010259SAndrew.Bardsley@arm.com default: 21110259SAndrew.Bardsley@arm.com os << "LSQRequestState-" << static_cast<int>(state); 21210259SAndrew.Bardsley@arm.com break; 21310259SAndrew.Bardsley@arm.com } 21410259SAndrew.Bardsley@arm.com return os; 21510259SAndrew.Bardsley@arm.com} 21610259SAndrew.Bardsley@arm.com 21710259SAndrew.Bardsley@arm.comvoid 21810259SAndrew.Bardsley@arm.comLSQ::clearMemBarrier(MinorDynInstPtr inst) 21910259SAndrew.Bardsley@arm.com{ 22011567Smitch.hayenga@arm.com bool is_last_barrier = 22111567Smitch.hayenga@arm.com inst->id.execSeqNum >= lastMemBarrier[inst->id.threadId]; 22210259SAndrew.Bardsley@arm.com 22310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Moving %s barrier out of store buffer inst: %s\n", 22410259SAndrew.Bardsley@arm.com (is_last_barrier ? "last" : "a"), *inst); 22510259SAndrew.Bardsley@arm.com 22610259SAndrew.Bardsley@arm.com if (is_last_barrier) 22711567Smitch.hayenga@arm.com lastMemBarrier[inst->id.threadId] = 0; 22810259SAndrew.Bardsley@arm.com} 22910259SAndrew.Bardsley@arm.com 23010259SAndrew.Bardsley@arm.comvoid 23110379Sandreas.hansson@arm.comLSQ::SingleDataRequest::finish(const Fault &fault_, RequestPtr request_, 23210379Sandreas.hansson@arm.com ThreadContext *tc, BaseTLB::Mode mode) 23310259SAndrew.Bardsley@arm.com{ 23410259SAndrew.Bardsley@arm.com fault = fault_; 23510259SAndrew.Bardsley@arm.com 23610259SAndrew.Bardsley@arm.com port.numAccessesInDTLB--; 23710259SAndrew.Bardsley@arm.com 23810259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Received translation response for" 23910259SAndrew.Bardsley@arm.com " request: %s\n", *inst); 24010259SAndrew.Bardsley@arm.com 24110259SAndrew.Bardsley@arm.com makePacket(); 24210259SAndrew.Bardsley@arm.com 24310259SAndrew.Bardsley@arm.com setState(Translated); 24410259SAndrew.Bardsley@arm.com port.tryToSendToTransfers(this); 24510259SAndrew.Bardsley@arm.com 24610259SAndrew.Bardsley@arm.com /* Let's try and wake up the processor for the next cycle */ 24710259SAndrew.Bardsley@arm.com port.cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 24810259SAndrew.Bardsley@arm.com} 24910259SAndrew.Bardsley@arm.com 25010259SAndrew.Bardsley@arm.comvoid 25110259SAndrew.Bardsley@arm.comLSQ::SingleDataRequest::startAddrTranslation() 25210259SAndrew.Bardsley@arm.com{ 25310259SAndrew.Bardsley@arm.com ThreadContext *thread = port.cpu.getContext( 25410259SAndrew.Bardsley@arm.com inst->id.threadId); 25510259SAndrew.Bardsley@arm.com 25610259SAndrew.Bardsley@arm.com port.numAccessesInDTLB++; 25710259SAndrew.Bardsley@arm.com 25810259SAndrew.Bardsley@arm.com setState(LSQ::LSQRequest::InTranslation); 25910259SAndrew.Bardsley@arm.com 26010259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Submitting DTLB request\n"); 26110259SAndrew.Bardsley@arm.com /* Submit the translation request. The response will come through 26210259SAndrew.Bardsley@arm.com * finish/markDelayed on the LSQRequest as it bears the Translation 26310259SAndrew.Bardsley@arm.com * interface */ 26410259SAndrew.Bardsley@arm.com thread->getDTBPtr()->translateTiming( 26510259SAndrew.Bardsley@arm.com &request, thread, this, (isLoad ? BaseTLB::Read : BaseTLB::Write)); 26610259SAndrew.Bardsley@arm.com} 26710259SAndrew.Bardsley@arm.com 26810259SAndrew.Bardsley@arm.comvoid 26910259SAndrew.Bardsley@arm.comLSQ::SingleDataRequest::retireResponse(PacketPtr packet_) 27010259SAndrew.Bardsley@arm.com{ 27110259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Retiring packet\n"); 27210259SAndrew.Bardsley@arm.com packet = packet_; 27310259SAndrew.Bardsley@arm.com packetInFlight = false; 27410259SAndrew.Bardsley@arm.com setState(Complete); 27510259SAndrew.Bardsley@arm.com} 27610259SAndrew.Bardsley@arm.com 27710259SAndrew.Bardsley@arm.comvoid 27810379Sandreas.hansson@arm.comLSQ::SplitDataRequest::finish(const Fault &fault_, RequestPtr request_, 27910379Sandreas.hansson@arm.com ThreadContext *tc, BaseTLB::Mode mode) 28010259SAndrew.Bardsley@arm.com{ 28110259SAndrew.Bardsley@arm.com fault = fault_; 28210259SAndrew.Bardsley@arm.com 28310259SAndrew.Bardsley@arm.com port.numAccessesInDTLB--; 28410259SAndrew.Bardsley@arm.com 28510259SAndrew.Bardsley@arm.com unsigned int M5_VAR_USED expected_fragment_index = 28610259SAndrew.Bardsley@arm.com numTranslatedFragments; 28710259SAndrew.Bardsley@arm.com 28810259SAndrew.Bardsley@arm.com numInTranslationFragments--; 28910259SAndrew.Bardsley@arm.com numTranslatedFragments++; 29010259SAndrew.Bardsley@arm.com 29110259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Received translation response for fragment" 29210259SAndrew.Bardsley@arm.com " %d of request: %s\n", expected_fragment_index, *inst); 29310259SAndrew.Bardsley@arm.com 29410259SAndrew.Bardsley@arm.com assert(request_ == fragmentRequests[expected_fragment_index]); 29510259SAndrew.Bardsley@arm.com 29610259SAndrew.Bardsley@arm.com /* Wake up next cycle to get things going again in case the 29710259SAndrew.Bardsley@arm.com * tryToSendToTransfers does take */ 29810259SAndrew.Bardsley@arm.com port.cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 29910259SAndrew.Bardsley@arm.com 30010259SAndrew.Bardsley@arm.com if (fault != NoFault) { 30110259SAndrew.Bardsley@arm.com /* tryToSendToTransfers will handle the fault */ 30210259SAndrew.Bardsley@arm.com 30310259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Faulting translation for fragment:" 30410259SAndrew.Bardsley@arm.com " %d of request: %s\n", 30510259SAndrew.Bardsley@arm.com expected_fragment_index, *inst); 30610259SAndrew.Bardsley@arm.com 30710259SAndrew.Bardsley@arm.com setState(Translated); 30810259SAndrew.Bardsley@arm.com port.tryToSendToTransfers(this); 30910259SAndrew.Bardsley@arm.com } else if (numTranslatedFragments == numFragments) { 31010259SAndrew.Bardsley@arm.com makeFragmentPackets(); 31110259SAndrew.Bardsley@arm.com 31210259SAndrew.Bardsley@arm.com setState(Translated); 31310259SAndrew.Bardsley@arm.com port.tryToSendToTransfers(this); 31410259SAndrew.Bardsley@arm.com } else { 31510259SAndrew.Bardsley@arm.com /* Avoid calling translateTiming from within ::finish */ 31610259SAndrew.Bardsley@arm.com assert(!translationEvent.scheduled()); 31710259SAndrew.Bardsley@arm.com port.cpu.schedule(translationEvent, curTick()); 31810259SAndrew.Bardsley@arm.com } 31910259SAndrew.Bardsley@arm.com} 32010259SAndrew.Bardsley@arm.com 32110259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_, 32210259SAndrew.Bardsley@arm.com bool isLoad_, PacketDataPtr data_, uint64_t *res_) : 32310259SAndrew.Bardsley@arm.com LSQRequest(port_, inst_, isLoad_, data_, res_), 32412127Sspwilson2@wisc.edu translationEvent([this]{ sendNextFragmentToTranslation(); }, 32512127Sspwilson2@wisc.edu "translationEvent"), 32610259SAndrew.Bardsley@arm.com numFragments(0), 32710259SAndrew.Bardsley@arm.com numInTranslationFragments(0), 32810259SAndrew.Bardsley@arm.com numTranslatedFragments(0), 32910259SAndrew.Bardsley@arm.com numIssuedFragments(0), 33010259SAndrew.Bardsley@arm.com numRetiredFragments(0), 33110259SAndrew.Bardsley@arm.com fragmentRequests(), 33210259SAndrew.Bardsley@arm.com fragmentPackets() 33310259SAndrew.Bardsley@arm.com{ 33410259SAndrew.Bardsley@arm.com /* Don't know how many elements are needed until the request is 33510259SAndrew.Bardsley@arm.com * populated by the caller. */ 33610259SAndrew.Bardsley@arm.com} 33710259SAndrew.Bardsley@arm.com 33810259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::~SplitDataRequest() 33910259SAndrew.Bardsley@arm.com{ 34010259SAndrew.Bardsley@arm.com for (auto i = fragmentRequests.begin(); 34110259SAndrew.Bardsley@arm.com i != fragmentRequests.end(); i++) 34210259SAndrew.Bardsley@arm.com { 34310259SAndrew.Bardsley@arm.com delete *i; 34410259SAndrew.Bardsley@arm.com } 34510259SAndrew.Bardsley@arm.com 34610259SAndrew.Bardsley@arm.com for (auto i = fragmentPackets.begin(); 34710259SAndrew.Bardsley@arm.com i != fragmentPackets.end(); i++) 34810259SAndrew.Bardsley@arm.com { 34910259SAndrew.Bardsley@arm.com delete *i; 35010259SAndrew.Bardsley@arm.com } 35110259SAndrew.Bardsley@arm.com} 35210259SAndrew.Bardsley@arm.com 35310259SAndrew.Bardsley@arm.comvoid 35410259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::makeFragmentRequests() 35510259SAndrew.Bardsley@arm.com{ 35610259SAndrew.Bardsley@arm.com Addr base_addr = request.getVaddr(); 35710259SAndrew.Bardsley@arm.com unsigned int whole_size = request.getSize(); 35810259SAndrew.Bardsley@arm.com unsigned int line_width = port.lineWidth; 35910259SAndrew.Bardsley@arm.com 36010259SAndrew.Bardsley@arm.com unsigned int fragment_size; 36110259SAndrew.Bardsley@arm.com Addr fragment_addr; 36210259SAndrew.Bardsley@arm.com 36310259SAndrew.Bardsley@arm.com /* Assume that this transfer is across potentially many block snap 36410259SAndrew.Bardsley@arm.com * boundaries: 36510259SAndrew.Bardsley@arm.com * 36610259SAndrew.Bardsley@arm.com * | _|________|________|________|___ | 36710259SAndrew.Bardsley@arm.com * | |0| 1 | 2 | 3 | 4 | | 36810259SAndrew.Bardsley@arm.com * | |_|________|________|________|___| | 36910259SAndrew.Bardsley@arm.com * | | | | | | 37010259SAndrew.Bardsley@arm.com * 37110259SAndrew.Bardsley@arm.com * The first transfer (0) can be up to lineWidth in size. 37210259SAndrew.Bardsley@arm.com * All the middle transfers (1-3) are lineWidth in size 37310259SAndrew.Bardsley@arm.com * The last transfer (4) can be from zero to lineWidth - 1 in size 37410259SAndrew.Bardsley@arm.com */ 37510259SAndrew.Bardsley@arm.com unsigned int first_fragment_offset = 37610259SAndrew.Bardsley@arm.com addrBlockOffset(base_addr, line_width); 37710259SAndrew.Bardsley@arm.com unsigned int last_fragment_size = 37810259SAndrew.Bardsley@arm.com addrBlockOffset(base_addr + whole_size, line_width); 37910259SAndrew.Bardsley@arm.com unsigned int first_fragment_size = 38010259SAndrew.Bardsley@arm.com line_width - first_fragment_offset; 38110259SAndrew.Bardsley@arm.com 38210259SAndrew.Bardsley@arm.com unsigned int middle_fragments_total_size = 38310259SAndrew.Bardsley@arm.com whole_size - (first_fragment_size + last_fragment_size); 38410259SAndrew.Bardsley@arm.com 38510259SAndrew.Bardsley@arm.com assert(addrBlockOffset(middle_fragments_total_size, line_width) == 0); 38610259SAndrew.Bardsley@arm.com 38710259SAndrew.Bardsley@arm.com unsigned int middle_fragment_count = 38810259SAndrew.Bardsley@arm.com middle_fragments_total_size / line_width; 38910259SAndrew.Bardsley@arm.com 39010259SAndrew.Bardsley@arm.com numFragments = 1 /* first */ + middle_fragment_count + 39110259SAndrew.Bardsley@arm.com (last_fragment_size == 0 ? 0 : 1); 39210259SAndrew.Bardsley@arm.com 39310259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Dividing transfer into %d fragmentRequests." 39410259SAndrew.Bardsley@arm.com " First fragment size: %d Last fragment size: %d\n", 39510259SAndrew.Bardsley@arm.com numFragments, first_fragment_size, 39610259SAndrew.Bardsley@arm.com (last_fragment_size == 0 ? line_width : last_fragment_size)); 39710259SAndrew.Bardsley@arm.com 39810259SAndrew.Bardsley@arm.com assert(((middle_fragment_count * line_width) + 39910259SAndrew.Bardsley@arm.com first_fragment_size + last_fragment_size) == whole_size); 40010259SAndrew.Bardsley@arm.com 40110259SAndrew.Bardsley@arm.com fragment_addr = base_addr; 40210259SAndrew.Bardsley@arm.com fragment_size = first_fragment_size; 40310259SAndrew.Bardsley@arm.com 40410259SAndrew.Bardsley@arm.com /* Just past the last address in the request */ 40510259SAndrew.Bardsley@arm.com Addr end_addr = base_addr + whole_size; 40610259SAndrew.Bardsley@arm.com 40710259SAndrew.Bardsley@arm.com for (unsigned int fragment_index = 0; fragment_index < numFragments; 40810259SAndrew.Bardsley@arm.com fragment_index++) 40910259SAndrew.Bardsley@arm.com { 41010259SAndrew.Bardsley@arm.com bool M5_VAR_USED is_last_fragment = false; 41110259SAndrew.Bardsley@arm.com 41210259SAndrew.Bardsley@arm.com if (fragment_addr == base_addr) { 41310259SAndrew.Bardsley@arm.com /* First fragment */ 41410259SAndrew.Bardsley@arm.com fragment_size = first_fragment_size; 41510259SAndrew.Bardsley@arm.com } else { 41610259SAndrew.Bardsley@arm.com if ((fragment_addr + line_width) > end_addr) { 41710259SAndrew.Bardsley@arm.com /* Adjust size of last fragment */ 41810259SAndrew.Bardsley@arm.com fragment_size = end_addr - fragment_addr; 41910259SAndrew.Bardsley@arm.com is_last_fragment = true; 42010259SAndrew.Bardsley@arm.com } else { 42110259SAndrew.Bardsley@arm.com /* Middle fragments */ 42210259SAndrew.Bardsley@arm.com fragment_size = line_width; 42310259SAndrew.Bardsley@arm.com } 42410259SAndrew.Bardsley@arm.com } 42510259SAndrew.Bardsley@arm.com 42610259SAndrew.Bardsley@arm.com Request *fragment = new Request(); 42710259SAndrew.Bardsley@arm.com 42811435Smitch.hayenga@arm.com fragment->setContext(request.contextId()); 42910259SAndrew.Bardsley@arm.com fragment->setVirt(0 /* asid */, 43010259SAndrew.Bardsley@arm.com fragment_addr, fragment_size, request.getFlags(), 43110259SAndrew.Bardsley@arm.com request.masterId(), 43210259SAndrew.Bardsley@arm.com request.getPC()); 43310259SAndrew.Bardsley@arm.com 43410259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Generating fragment addr: 0x%x size: %d" 43510259SAndrew.Bardsley@arm.com " (whole request addr: 0x%x size: %d) %s\n", 43610259SAndrew.Bardsley@arm.com fragment_addr, fragment_size, base_addr, whole_size, 43710259SAndrew.Bardsley@arm.com (is_last_fragment ? "last fragment" : "")); 43810259SAndrew.Bardsley@arm.com 43910259SAndrew.Bardsley@arm.com fragment_addr += fragment_size; 44010259SAndrew.Bardsley@arm.com 44110259SAndrew.Bardsley@arm.com fragmentRequests.push_back(fragment); 44210259SAndrew.Bardsley@arm.com } 44310259SAndrew.Bardsley@arm.com} 44410259SAndrew.Bardsley@arm.com 44510259SAndrew.Bardsley@arm.comvoid 44610259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::makeFragmentPackets() 44710259SAndrew.Bardsley@arm.com{ 44810259SAndrew.Bardsley@arm.com Addr base_addr = request.getVaddr(); 44910259SAndrew.Bardsley@arm.com 45010259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Making packets for request: %s\n", *inst); 45110259SAndrew.Bardsley@arm.com 45210259SAndrew.Bardsley@arm.com for (unsigned int fragment_index = 0; fragment_index < numFragments; 45310259SAndrew.Bardsley@arm.com fragment_index++) 45410259SAndrew.Bardsley@arm.com { 45510259SAndrew.Bardsley@arm.com Request *fragment = fragmentRequests[fragment_index]; 45610259SAndrew.Bardsley@arm.com 45710259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Making packet %d for request: %s" 45810259SAndrew.Bardsley@arm.com " (%d, 0x%x)\n", 45910259SAndrew.Bardsley@arm.com fragment_index, *inst, 46010259SAndrew.Bardsley@arm.com (fragment->hasPaddr() ? "has paddr" : "no paddr"), 46110259SAndrew.Bardsley@arm.com (fragment->hasPaddr() ? fragment->getPaddr() : 0)); 46210259SAndrew.Bardsley@arm.com 46310259SAndrew.Bardsley@arm.com Addr fragment_addr = fragment->getVaddr(); 46410259SAndrew.Bardsley@arm.com unsigned int fragment_size = fragment->getSize(); 46510259SAndrew.Bardsley@arm.com 46610259SAndrew.Bardsley@arm.com uint8_t *request_data = NULL; 46710259SAndrew.Bardsley@arm.com 46810259SAndrew.Bardsley@arm.com if (!isLoad) { 46910259SAndrew.Bardsley@arm.com /* Split data for Packets. Will become the property of the 47010259SAndrew.Bardsley@arm.com * outgoing Packets */ 47110259SAndrew.Bardsley@arm.com request_data = new uint8_t[fragment_size]; 47210259SAndrew.Bardsley@arm.com std::memcpy(request_data, data + (fragment_addr - base_addr), 47310259SAndrew.Bardsley@arm.com fragment_size); 47410259SAndrew.Bardsley@arm.com } 47510259SAndrew.Bardsley@arm.com 47610259SAndrew.Bardsley@arm.com assert(fragment->hasPaddr()); 47710259SAndrew.Bardsley@arm.com 47810259SAndrew.Bardsley@arm.com PacketPtr fragment_packet = 47910259SAndrew.Bardsley@arm.com makePacketForRequest(*fragment, isLoad, this, request_data); 48010259SAndrew.Bardsley@arm.com 48110259SAndrew.Bardsley@arm.com fragmentPackets.push_back(fragment_packet); 48210368SAndrew.Bardsley@arm.com /* Accumulate flags in parent request */ 48310368SAndrew.Bardsley@arm.com request.setFlags(fragment->getFlags()); 48410259SAndrew.Bardsley@arm.com } 48510259SAndrew.Bardsley@arm.com 48610259SAndrew.Bardsley@arm.com /* Might as well make the overall/response packet here */ 48710259SAndrew.Bardsley@arm.com /* Get the physical address for the whole request/packet from the first 48810259SAndrew.Bardsley@arm.com * fragment */ 48910259SAndrew.Bardsley@arm.com request.setPaddr(fragmentRequests[0]->getPaddr()); 49010259SAndrew.Bardsley@arm.com makePacket(); 49110259SAndrew.Bardsley@arm.com} 49210259SAndrew.Bardsley@arm.com 49310259SAndrew.Bardsley@arm.comvoid 49410259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::startAddrTranslation() 49510259SAndrew.Bardsley@arm.com{ 49610259SAndrew.Bardsley@arm.com setState(LSQ::LSQRequest::InTranslation); 49710259SAndrew.Bardsley@arm.com 49810259SAndrew.Bardsley@arm.com makeFragmentRequests(); 49910259SAndrew.Bardsley@arm.com 50010259SAndrew.Bardsley@arm.com numInTranslationFragments = 0; 50110259SAndrew.Bardsley@arm.com numTranslatedFragments = 0; 50210259SAndrew.Bardsley@arm.com 50310259SAndrew.Bardsley@arm.com /* @todo, just do these in sequence for now with 50410259SAndrew.Bardsley@arm.com * a loop of: 50510259SAndrew.Bardsley@arm.com * do { 50610259SAndrew.Bardsley@arm.com * sendNextFragmentToTranslation ; translateTiming ; finish 50710259SAndrew.Bardsley@arm.com * } while (numTranslatedFragments != numFragments); 50810259SAndrew.Bardsley@arm.com */ 50910259SAndrew.Bardsley@arm.com 51010259SAndrew.Bardsley@arm.com /* Do first translation */ 51110259SAndrew.Bardsley@arm.com sendNextFragmentToTranslation(); 51210259SAndrew.Bardsley@arm.com} 51310259SAndrew.Bardsley@arm.com 51410259SAndrew.Bardsley@arm.comPacketPtr 51510259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::getHeadPacket() 51610259SAndrew.Bardsley@arm.com{ 51710259SAndrew.Bardsley@arm.com assert(numIssuedFragments < numFragments); 51810259SAndrew.Bardsley@arm.com 51910259SAndrew.Bardsley@arm.com return fragmentPackets[numIssuedFragments]; 52010259SAndrew.Bardsley@arm.com} 52110259SAndrew.Bardsley@arm.com 52210259SAndrew.Bardsley@arm.comvoid 52310259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::stepToNextPacket() 52410259SAndrew.Bardsley@arm.com{ 52510259SAndrew.Bardsley@arm.com assert(numIssuedFragments < numFragments); 52610259SAndrew.Bardsley@arm.com 52710259SAndrew.Bardsley@arm.com numIssuedFragments++; 52810259SAndrew.Bardsley@arm.com} 52910259SAndrew.Bardsley@arm.com 53010259SAndrew.Bardsley@arm.comvoid 53110259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::retireResponse(PacketPtr response) 53210259SAndrew.Bardsley@arm.com{ 53310259SAndrew.Bardsley@arm.com assert(numRetiredFragments < numFragments); 53410259SAndrew.Bardsley@arm.com 53510259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Retiring fragment addr: 0x%x size: %d" 53610259SAndrew.Bardsley@arm.com " offset: 0x%x (retired fragment num: %d) %s\n", 53710259SAndrew.Bardsley@arm.com response->req->getVaddr(), response->req->getSize(), 53810259SAndrew.Bardsley@arm.com request.getVaddr() - response->req->getVaddr(), 53910259SAndrew.Bardsley@arm.com numRetiredFragments, 54010259SAndrew.Bardsley@arm.com (fault == NoFault ? "" : fault->name())); 54110259SAndrew.Bardsley@arm.com 54210259SAndrew.Bardsley@arm.com numRetiredFragments++; 54310259SAndrew.Bardsley@arm.com 54410259SAndrew.Bardsley@arm.com if (skipped) { 54510259SAndrew.Bardsley@arm.com /* Skip because we already knew the request had faulted or been 54610259SAndrew.Bardsley@arm.com * skipped */ 54710259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Skipping this fragment\n"); 54810259SAndrew.Bardsley@arm.com } else if (response->isError()) { 54910259SAndrew.Bardsley@arm.com /* Mark up the error and leave to execute to handle it */ 55010259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Fragment has an error, skipping\n"); 55110259SAndrew.Bardsley@arm.com setSkipped(); 55210259SAndrew.Bardsley@arm.com packet->copyError(response); 55310259SAndrew.Bardsley@arm.com } else { 55410259SAndrew.Bardsley@arm.com if (isLoad) { 55510259SAndrew.Bardsley@arm.com if (!data) { 55610259SAndrew.Bardsley@arm.com /* For a split transfer, a Packet must be constructed 55710259SAndrew.Bardsley@arm.com * to contain all returning data. This is that packet's 55810259SAndrew.Bardsley@arm.com * data */ 55910259SAndrew.Bardsley@arm.com data = new uint8_t[request.getSize()]; 56010259SAndrew.Bardsley@arm.com } 56110259SAndrew.Bardsley@arm.com 56210259SAndrew.Bardsley@arm.com /* Populate the portion of the overall response data represented 56310259SAndrew.Bardsley@arm.com * by the response fragment */ 56410259SAndrew.Bardsley@arm.com std::memcpy( 56510259SAndrew.Bardsley@arm.com data + (response->req->getVaddr() - request.getVaddr()), 56610563Sandreas.hansson@arm.com response->getConstPtr<uint8_t>(), 56710259SAndrew.Bardsley@arm.com response->req->getSize()); 56810259SAndrew.Bardsley@arm.com } 56910259SAndrew.Bardsley@arm.com } 57010259SAndrew.Bardsley@arm.com 57110259SAndrew.Bardsley@arm.com /* Complete early if we're skipping are no more in-flight accesses */ 57210259SAndrew.Bardsley@arm.com if (skipped && !hasPacketsInMemSystem()) { 57310259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Completed skipped burst\n"); 57410259SAndrew.Bardsley@arm.com setState(Complete); 57510259SAndrew.Bardsley@arm.com if (packet->needsResponse()) 57610259SAndrew.Bardsley@arm.com packet->makeResponse(); 57710259SAndrew.Bardsley@arm.com } 57810259SAndrew.Bardsley@arm.com 57910259SAndrew.Bardsley@arm.com if (numRetiredFragments == numFragments) 58010259SAndrew.Bardsley@arm.com setState(Complete); 58110259SAndrew.Bardsley@arm.com 58210259SAndrew.Bardsley@arm.com if (!skipped && isComplete()) { 58310259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Completed burst %d\n", packet != NULL); 58410259SAndrew.Bardsley@arm.com 58510259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Retired packet isRead: %d isWrite: %d" 58610259SAndrew.Bardsley@arm.com " needsResponse: %d packetSize: %s requestSize: %s responseSize:" 58710259SAndrew.Bardsley@arm.com " %s\n", packet->isRead(), packet->isWrite(), 58810259SAndrew.Bardsley@arm.com packet->needsResponse(), packet->getSize(), request.getSize(), 58910259SAndrew.Bardsley@arm.com response->getSize()); 59010259SAndrew.Bardsley@arm.com 59110259SAndrew.Bardsley@arm.com /* A request can become complete by several paths, this is a sanity 59210259SAndrew.Bardsley@arm.com * check to make sure the packet's data is created */ 59310259SAndrew.Bardsley@arm.com if (!data) { 59410259SAndrew.Bardsley@arm.com data = new uint8_t[request.getSize()]; 59510259SAndrew.Bardsley@arm.com } 59610259SAndrew.Bardsley@arm.com 59710259SAndrew.Bardsley@arm.com if (isLoad) { 59810259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Copying read data\n"); 59910259SAndrew.Bardsley@arm.com std::memcpy(packet->getPtr<uint8_t>(), data, request.getSize()); 60010259SAndrew.Bardsley@arm.com } 60110259SAndrew.Bardsley@arm.com packet->makeResponse(); 60210259SAndrew.Bardsley@arm.com } 60310259SAndrew.Bardsley@arm.com 60410259SAndrew.Bardsley@arm.com /* Packets are all deallocated together in ~SplitLSQRequest */ 60510259SAndrew.Bardsley@arm.com} 60610259SAndrew.Bardsley@arm.com 60710259SAndrew.Bardsley@arm.comvoid 60810259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::sendNextFragmentToTranslation() 60910259SAndrew.Bardsley@arm.com{ 61010259SAndrew.Bardsley@arm.com unsigned int fragment_index = numTranslatedFragments; 61110259SAndrew.Bardsley@arm.com 61210259SAndrew.Bardsley@arm.com ThreadContext *thread = port.cpu.getContext( 61310259SAndrew.Bardsley@arm.com inst->id.threadId); 61410259SAndrew.Bardsley@arm.com 61510259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Submitting DTLB request for fragment: %d\n", 61610259SAndrew.Bardsley@arm.com fragment_index); 61710259SAndrew.Bardsley@arm.com 61810259SAndrew.Bardsley@arm.com port.numAccessesInDTLB++; 61910259SAndrew.Bardsley@arm.com numInTranslationFragments++; 62010259SAndrew.Bardsley@arm.com 62110259SAndrew.Bardsley@arm.com thread->getDTBPtr()->translateTiming( 62210259SAndrew.Bardsley@arm.com fragmentRequests[fragment_index], thread, this, (isLoad ? 62310259SAndrew.Bardsley@arm.com BaseTLB::Read : BaseTLB::Write)); 62410259SAndrew.Bardsley@arm.com} 62510259SAndrew.Bardsley@arm.com 62610259SAndrew.Bardsley@arm.combool 62710259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::canInsert() const 62810259SAndrew.Bardsley@arm.com{ 62910259SAndrew.Bardsley@arm.com /* @todo, support store amalgamation */ 63010259SAndrew.Bardsley@arm.com return slots.size() < numSlots; 63110259SAndrew.Bardsley@arm.com} 63210259SAndrew.Bardsley@arm.com 63310259SAndrew.Bardsley@arm.comvoid 63410259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::deleteRequest(LSQRequestPtr request) 63510259SAndrew.Bardsley@arm.com{ 63610259SAndrew.Bardsley@arm.com auto found = std::find(slots.begin(), slots.end(), request); 63710259SAndrew.Bardsley@arm.com 63810259SAndrew.Bardsley@arm.com if (found != slots.end()) { 63910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Deleting request: %s %s %s from StoreBuffer\n", 64010259SAndrew.Bardsley@arm.com request, *found, *(request->inst)); 64110259SAndrew.Bardsley@arm.com slots.erase(found); 64210259SAndrew.Bardsley@arm.com 64310259SAndrew.Bardsley@arm.com delete request; 64410259SAndrew.Bardsley@arm.com } 64510259SAndrew.Bardsley@arm.com} 64610259SAndrew.Bardsley@arm.com 64710259SAndrew.Bardsley@arm.comvoid 64810259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::insert(LSQRequestPtr request) 64910259SAndrew.Bardsley@arm.com{ 65010259SAndrew.Bardsley@arm.com if (!canInsert()) { 65110259SAndrew.Bardsley@arm.com warn("%s: store buffer insertion without space to insert from" 65210259SAndrew.Bardsley@arm.com " inst: %s\n", name(), *(request->inst)); 65310259SAndrew.Bardsley@arm.com } 65410259SAndrew.Bardsley@arm.com 65510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Pushing store: %s into store buffer\n", request); 65610259SAndrew.Bardsley@arm.com 65710259SAndrew.Bardsley@arm.com numUnissuedAccesses++; 65810259SAndrew.Bardsley@arm.com 65910259SAndrew.Bardsley@arm.com if (request->state != LSQRequest::Complete) 66010259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreInStoreBuffer); 66110259SAndrew.Bardsley@arm.com 66210259SAndrew.Bardsley@arm.com slots.push_back(request); 66310259SAndrew.Bardsley@arm.com 66410259SAndrew.Bardsley@arm.com /* Let's try and wake up the processor for the next cycle to step 66510259SAndrew.Bardsley@arm.com * the store buffer */ 66610259SAndrew.Bardsley@arm.com lsq.cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 66710259SAndrew.Bardsley@arm.com} 66810259SAndrew.Bardsley@arm.com 66910259SAndrew.Bardsley@arm.comLSQ::AddrRangeCoverage 67010259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::canForwardDataToLoad(LSQRequestPtr request, 67110259SAndrew.Bardsley@arm.com unsigned int &found_slot) 67210259SAndrew.Bardsley@arm.com{ 67310259SAndrew.Bardsley@arm.com unsigned int slot_index = slots.size() - 1; 67410259SAndrew.Bardsley@arm.com auto i = slots.rbegin(); 67510259SAndrew.Bardsley@arm.com AddrRangeCoverage ret = NoAddrRangeCoverage; 67610259SAndrew.Bardsley@arm.com 67710259SAndrew.Bardsley@arm.com /* Traverse the store buffer in reverse order (most to least recent) 67810259SAndrew.Bardsley@arm.com * and try to find a slot whose address range overlaps this request */ 67910259SAndrew.Bardsley@arm.com while (ret == NoAddrRangeCoverage && i != slots.rend()) { 68010259SAndrew.Bardsley@arm.com LSQRequestPtr slot = *i; 68110259SAndrew.Bardsley@arm.com 68212355Snikos.nikoleris@arm.com /* Cache maintenance instructions go down via the store path * 68312355Snikos.nikoleris@arm.com * but they carry no data and they shouldn't be considered for 68412355Snikos.nikoleris@arm.com * forwarding */ 68511567Smitch.hayenga@arm.com if (slot->packet && 68612355Snikos.nikoleris@arm.com slot->inst->id.threadId == request->inst->id.threadId && 68712355Snikos.nikoleris@arm.com !slot->packet->req->isCacheMaintenance()) { 68810259SAndrew.Bardsley@arm.com AddrRangeCoverage coverage = slot->containsAddrRangeOf(request); 68910259SAndrew.Bardsley@arm.com 69010259SAndrew.Bardsley@arm.com if (coverage != NoAddrRangeCoverage) { 69110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Forwarding: slot: %d result: %s thisAddr:" 69210259SAndrew.Bardsley@arm.com " 0x%x thisSize: %d slotAddr: 0x%x slotSize: %d\n", 69310259SAndrew.Bardsley@arm.com slot_index, coverage, 69410259SAndrew.Bardsley@arm.com request->request.getPaddr(), request->request.getSize(), 69510259SAndrew.Bardsley@arm.com slot->request.getPaddr(), slot->request.getSize()); 69610259SAndrew.Bardsley@arm.com 69710259SAndrew.Bardsley@arm.com found_slot = slot_index; 69810259SAndrew.Bardsley@arm.com ret = coverage; 69910259SAndrew.Bardsley@arm.com } 70010259SAndrew.Bardsley@arm.com } 70110259SAndrew.Bardsley@arm.com 70210259SAndrew.Bardsley@arm.com i++; 70310259SAndrew.Bardsley@arm.com slot_index--; 70410259SAndrew.Bardsley@arm.com } 70510259SAndrew.Bardsley@arm.com 70610259SAndrew.Bardsley@arm.com return ret; 70710259SAndrew.Bardsley@arm.com} 70810259SAndrew.Bardsley@arm.com 70910259SAndrew.Bardsley@arm.com/** Fill the given packet with appropriate date from slot slot_number */ 71010259SAndrew.Bardsley@arm.comvoid 71110259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::forwardStoreData(LSQRequestPtr load, 71210259SAndrew.Bardsley@arm.com unsigned int slot_number) 71310259SAndrew.Bardsley@arm.com{ 71410259SAndrew.Bardsley@arm.com assert(slot_number < slots.size()); 71510259SAndrew.Bardsley@arm.com assert(load->packet); 71610259SAndrew.Bardsley@arm.com assert(load->isLoad); 71710259SAndrew.Bardsley@arm.com 71810259SAndrew.Bardsley@arm.com LSQRequestPtr store = slots[slot_number]; 71910259SAndrew.Bardsley@arm.com 72010259SAndrew.Bardsley@arm.com assert(store->packet); 72110259SAndrew.Bardsley@arm.com assert(store->containsAddrRangeOf(load) == FullAddrRangeCoverage); 72210259SAndrew.Bardsley@arm.com 72310259SAndrew.Bardsley@arm.com Addr load_addr = load->request.getPaddr(); 72410259SAndrew.Bardsley@arm.com Addr store_addr = store->request.getPaddr(); 72510259SAndrew.Bardsley@arm.com Addr addr_offset = load_addr - store_addr; 72610259SAndrew.Bardsley@arm.com 72710259SAndrew.Bardsley@arm.com unsigned int load_size = load->request.getSize(); 72810259SAndrew.Bardsley@arm.com 72910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Forwarding %d bytes for addr: 0x%x from store buffer" 73010259SAndrew.Bardsley@arm.com " slot: %d addr: 0x%x addressOffset: 0x%x\n", 73110259SAndrew.Bardsley@arm.com load_size, load_addr, slot_number, 73210259SAndrew.Bardsley@arm.com store_addr, addr_offset); 73310259SAndrew.Bardsley@arm.com 73410259SAndrew.Bardsley@arm.com void *load_packet_data = load->packet->getPtr<void>(); 73510259SAndrew.Bardsley@arm.com void *store_packet_data = store->packet->getPtr<uint8_t>() + addr_offset; 73610259SAndrew.Bardsley@arm.com 73710259SAndrew.Bardsley@arm.com std::memcpy(load_packet_data, store_packet_data, load_size); 73810259SAndrew.Bardsley@arm.com} 73910259SAndrew.Bardsley@arm.com 74010259SAndrew.Bardsley@arm.comvoid 74110581SAndrew.Bardsley@arm.comLSQ::StoreBuffer::countIssuedStore(LSQRequestPtr request) 74210581SAndrew.Bardsley@arm.com{ 74310581SAndrew.Bardsley@arm.com /* Barriers are accounted for as they are cleared from 74410581SAndrew.Bardsley@arm.com * the queue, not after their transfers are complete */ 74510581SAndrew.Bardsley@arm.com if (!request->isBarrier()) 74610581SAndrew.Bardsley@arm.com numUnissuedAccesses--; 74710581SAndrew.Bardsley@arm.com} 74810581SAndrew.Bardsley@arm.com 74910581SAndrew.Bardsley@arm.comvoid 75010259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::step() 75110259SAndrew.Bardsley@arm.com{ 75210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "StoreBuffer step numUnissuedAccesses: %d\n", 75310259SAndrew.Bardsley@arm.com numUnissuedAccesses); 75410259SAndrew.Bardsley@arm.com 75510259SAndrew.Bardsley@arm.com if (numUnissuedAccesses != 0 && lsq.state == LSQ::MemoryRunning) { 75610259SAndrew.Bardsley@arm.com /* Clear all the leading barriers */ 75710259SAndrew.Bardsley@arm.com while (!slots.empty() && 75810259SAndrew.Bardsley@arm.com slots.front()->isComplete() && slots.front()->isBarrier()) 75910259SAndrew.Bardsley@arm.com { 76010259SAndrew.Bardsley@arm.com LSQRequestPtr barrier = slots.front(); 76110259SAndrew.Bardsley@arm.com 76210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Clearing barrier for inst: %s\n", 76310259SAndrew.Bardsley@arm.com *(barrier->inst)); 76410259SAndrew.Bardsley@arm.com 76510259SAndrew.Bardsley@arm.com numUnissuedAccesses--; 76610259SAndrew.Bardsley@arm.com lsq.clearMemBarrier(barrier->inst); 76710259SAndrew.Bardsley@arm.com slots.pop_front(); 76810259SAndrew.Bardsley@arm.com 76910259SAndrew.Bardsley@arm.com delete barrier; 77010259SAndrew.Bardsley@arm.com } 77110259SAndrew.Bardsley@arm.com 77210259SAndrew.Bardsley@arm.com auto i = slots.begin(); 77310259SAndrew.Bardsley@arm.com bool issued = true; 77410259SAndrew.Bardsley@arm.com unsigned int issue_count = 0; 77510259SAndrew.Bardsley@arm.com 77610259SAndrew.Bardsley@arm.com /* Skip trying if the memory system is busy */ 77710259SAndrew.Bardsley@arm.com if (lsq.state == LSQ::MemoryNeedsRetry) 77810259SAndrew.Bardsley@arm.com issued = false; 77910259SAndrew.Bardsley@arm.com 78010259SAndrew.Bardsley@arm.com /* Try to issue all stores in order starting from the head 78110259SAndrew.Bardsley@arm.com * of the queue. Responses are allowed to be retired 78210259SAndrew.Bardsley@arm.com * out of order */ 78310259SAndrew.Bardsley@arm.com while (issued && 78410259SAndrew.Bardsley@arm.com issue_count < storeLimitPerCycle && 78510259SAndrew.Bardsley@arm.com lsq.canSendToMemorySystem() && 78610259SAndrew.Bardsley@arm.com i != slots.end()) 78710259SAndrew.Bardsley@arm.com { 78810259SAndrew.Bardsley@arm.com LSQRequestPtr request = *i; 78910259SAndrew.Bardsley@arm.com 79010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Considering request: %s, sentAllPackets: %d" 79110259SAndrew.Bardsley@arm.com " state: %s\n", 79210259SAndrew.Bardsley@arm.com *(request->inst), request->sentAllPackets(), 79310259SAndrew.Bardsley@arm.com request->state); 79410259SAndrew.Bardsley@arm.com 79510259SAndrew.Bardsley@arm.com if (request->isBarrier() && request->isComplete()) { 79610259SAndrew.Bardsley@arm.com /* Give up at barriers */ 79710259SAndrew.Bardsley@arm.com issued = false; 79810259SAndrew.Bardsley@arm.com } else if (!(request->state == LSQRequest::StoreBufferIssuing && 79910259SAndrew.Bardsley@arm.com request->sentAllPackets())) 80010259SAndrew.Bardsley@arm.com { 80110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Trying to send request: %s to memory" 80210259SAndrew.Bardsley@arm.com " system\n", *(request->inst)); 80310259SAndrew.Bardsley@arm.com 80410259SAndrew.Bardsley@arm.com if (lsq.tryToSend(request)) { 80510581SAndrew.Bardsley@arm.com countIssuedStore(request); 80610259SAndrew.Bardsley@arm.com issue_count++; 80710259SAndrew.Bardsley@arm.com } else { 80810259SAndrew.Bardsley@arm.com /* Don't step on to the next store buffer entry if this 80910259SAndrew.Bardsley@arm.com * one hasn't issued all its packets as the store 81010259SAndrew.Bardsley@arm.com * buffer must still enforce ordering */ 81110259SAndrew.Bardsley@arm.com issued = false; 81210259SAndrew.Bardsley@arm.com } 81310259SAndrew.Bardsley@arm.com } 81410259SAndrew.Bardsley@arm.com i++; 81510259SAndrew.Bardsley@arm.com } 81610259SAndrew.Bardsley@arm.com } 81710259SAndrew.Bardsley@arm.com} 81810259SAndrew.Bardsley@arm.com 81910259SAndrew.Bardsley@arm.comvoid 82010259SAndrew.Bardsley@arm.comLSQ::completeMemBarrierInst(MinorDynInstPtr inst, 82110259SAndrew.Bardsley@arm.com bool committed) 82210259SAndrew.Bardsley@arm.com{ 82310259SAndrew.Bardsley@arm.com if (committed) { 82410259SAndrew.Bardsley@arm.com /* Not already sent to the store buffer as a store request? */ 82510259SAndrew.Bardsley@arm.com if (!inst->inStoreBuffer) { 82610259SAndrew.Bardsley@arm.com /* Insert an entry into the store buffer to tick off barriers 82710259SAndrew.Bardsley@arm.com * until there are none in flight */ 82810259SAndrew.Bardsley@arm.com storeBuffer.insert(new BarrierDataRequest(*this, inst)); 82910259SAndrew.Bardsley@arm.com } 83010259SAndrew.Bardsley@arm.com } else { 83110259SAndrew.Bardsley@arm.com /* Clear the barrier anyway if it wasn't actually committed */ 83210259SAndrew.Bardsley@arm.com clearMemBarrier(inst); 83310259SAndrew.Bardsley@arm.com } 83410259SAndrew.Bardsley@arm.com} 83510259SAndrew.Bardsley@arm.com 83610259SAndrew.Bardsley@arm.comvoid 83710259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::minorTrace() const 83810259SAndrew.Bardsley@arm.com{ 83910259SAndrew.Bardsley@arm.com unsigned int size = slots.size(); 84010259SAndrew.Bardsley@arm.com unsigned int i = 0; 84110259SAndrew.Bardsley@arm.com std::ostringstream os; 84210259SAndrew.Bardsley@arm.com 84310259SAndrew.Bardsley@arm.com while (i < size) { 84410259SAndrew.Bardsley@arm.com LSQRequestPtr request = slots[i]; 84510259SAndrew.Bardsley@arm.com 84610259SAndrew.Bardsley@arm.com request->reportData(os); 84710259SAndrew.Bardsley@arm.com 84810259SAndrew.Bardsley@arm.com i++; 84910259SAndrew.Bardsley@arm.com if (i < numSlots) 85010259SAndrew.Bardsley@arm.com os << ','; 85110259SAndrew.Bardsley@arm.com } 85210259SAndrew.Bardsley@arm.com 85310259SAndrew.Bardsley@arm.com while (i < numSlots) { 85410259SAndrew.Bardsley@arm.com os << '-'; 85510259SAndrew.Bardsley@arm.com 85610259SAndrew.Bardsley@arm.com i++; 85710259SAndrew.Bardsley@arm.com if (i < numSlots) 85810259SAndrew.Bardsley@arm.com os << ','; 85910259SAndrew.Bardsley@arm.com } 86010259SAndrew.Bardsley@arm.com 86110259SAndrew.Bardsley@arm.com MINORTRACE("addr=%s num_unissued_stores=%d\n", os.str(), 86210259SAndrew.Bardsley@arm.com numUnissuedAccesses); 86310259SAndrew.Bardsley@arm.com} 86410259SAndrew.Bardsley@arm.com 86510259SAndrew.Bardsley@arm.comvoid 86610259SAndrew.Bardsley@arm.comLSQ::tryToSendToTransfers(LSQRequestPtr request) 86710259SAndrew.Bardsley@arm.com{ 86810259SAndrew.Bardsley@arm.com if (state == MemoryNeedsRetry) { 86910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request needs retry, not issuing to" 87010259SAndrew.Bardsley@arm.com " memory until retry arrives\n"); 87110259SAndrew.Bardsley@arm.com return; 87210259SAndrew.Bardsley@arm.com } 87310259SAndrew.Bardsley@arm.com 87410259SAndrew.Bardsley@arm.com if (request->state == LSQRequest::InTranslation) { 87510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request still in translation, not issuing to" 87610259SAndrew.Bardsley@arm.com " memory\n"); 87710259SAndrew.Bardsley@arm.com return; 87810259SAndrew.Bardsley@arm.com } 87910259SAndrew.Bardsley@arm.com 88010259SAndrew.Bardsley@arm.com assert(request->state == LSQRequest::Translated || 88110259SAndrew.Bardsley@arm.com request->state == LSQRequest::RequestIssuing || 88210259SAndrew.Bardsley@arm.com request->state == LSQRequest::Failed || 88310259SAndrew.Bardsley@arm.com request->state == LSQRequest::Complete); 88410259SAndrew.Bardsley@arm.com 88510259SAndrew.Bardsley@arm.com if (requests.empty() || requests.front() != request) { 88610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request not at front of requests queue, can't" 88710259SAndrew.Bardsley@arm.com " issue to memory\n"); 88810259SAndrew.Bardsley@arm.com return; 88910259SAndrew.Bardsley@arm.com } 89010259SAndrew.Bardsley@arm.com 89110259SAndrew.Bardsley@arm.com if (transfers.unreservedRemainingSpace() == 0) { 89210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "No space to insert request into transfers" 89310259SAndrew.Bardsley@arm.com " queue\n"); 89410259SAndrew.Bardsley@arm.com return; 89510259SAndrew.Bardsley@arm.com } 89610259SAndrew.Bardsley@arm.com 89710259SAndrew.Bardsley@arm.com if (request->isComplete() || request->state == LSQRequest::Failed) { 89810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Passing a %s transfer on to transfers" 89910259SAndrew.Bardsley@arm.com " queue\n", (request->isComplete() ? "completed" : "failed")); 90010259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 90110259SAndrew.Bardsley@arm.com request->setSkipped(); 90210259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 90310259SAndrew.Bardsley@arm.com return; 90410259SAndrew.Bardsley@arm.com } 90510259SAndrew.Bardsley@arm.com 90610259SAndrew.Bardsley@arm.com if (!execute.instIsRightStream(request->inst)) { 90710259SAndrew.Bardsley@arm.com /* Wrong stream, try to abort the transfer but only do so if 90810259SAndrew.Bardsley@arm.com * there are no packets in flight */ 90910259SAndrew.Bardsley@arm.com if (request->hasPacketsInMemSystem()) { 91010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request's inst. is from the wrong stream," 91110259SAndrew.Bardsley@arm.com " waiting for responses before aborting request\n"); 91210259SAndrew.Bardsley@arm.com } else { 91310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request's inst. is from the wrong stream," 91410259SAndrew.Bardsley@arm.com " aborting request\n"); 91510259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 91610259SAndrew.Bardsley@arm.com request->setSkipped(); 91710259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 91810259SAndrew.Bardsley@arm.com } 91910259SAndrew.Bardsley@arm.com return; 92010259SAndrew.Bardsley@arm.com } 92110259SAndrew.Bardsley@arm.com 92210259SAndrew.Bardsley@arm.com if (request->fault != NoFault) { 92310259SAndrew.Bardsley@arm.com if (request->inst->staticInst->isPrefetch()) { 92410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Not signalling fault for faulting prefetch\n"); 92510259SAndrew.Bardsley@arm.com } 92610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Moving faulting request into the transfers" 92710259SAndrew.Bardsley@arm.com " queue\n"); 92810259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 92910259SAndrew.Bardsley@arm.com request->setSkipped(); 93010259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 93110259SAndrew.Bardsley@arm.com return; 93210259SAndrew.Bardsley@arm.com } 93310259SAndrew.Bardsley@arm.com 93410259SAndrew.Bardsley@arm.com bool is_load = request->isLoad; 93510259SAndrew.Bardsley@arm.com bool is_llsc = request->request.isLLSC(); 93610259SAndrew.Bardsley@arm.com bool is_swap = request->request.isSwap(); 93710824SAndreas.Sandberg@ARM.com bool bufferable = !(request->request.isStrictlyOrdered() || 93810259SAndrew.Bardsley@arm.com is_llsc || is_swap); 93910259SAndrew.Bardsley@arm.com 94010259SAndrew.Bardsley@arm.com if (is_load) { 94110259SAndrew.Bardsley@arm.com if (numStoresInTransfers != 0) { 94210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Load request with stores still in transfers" 94310259SAndrew.Bardsley@arm.com " queue, stalling\n"); 94410259SAndrew.Bardsley@arm.com return; 94510259SAndrew.Bardsley@arm.com } 94610259SAndrew.Bardsley@arm.com } else { 94710259SAndrew.Bardsley@arm.com /* Store. Can it be sent to the store buffer? */ 94810259SAndrew.Bardsley@arm.com if (bufferable && !request->request.isMmappedIpr()) { 94910259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreToStoreBuffer); 95010259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 95110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Moving store into transfers queue\n"); 95210259SAndrew.Bardsley@arm.com return; 95310259SAndrew.Bardsley@arm.com } 95410259SAndrew.Bardsley@arm.com } 95510259SAndrew.Bardsley@arm.com 95610259SAndrew.Bardsley@arm.com /* Check if this is the head instruction (and so must be executable as 95710259SAndrew.Bardsley@arm.com * its stream sequence number was checked above) for loads which must 95810259SAndrew.Bardsley@arm.com * not be speculatively issued and stores which must be issued here */ 95910259SAndrew.Bardsley@arm.com if (!bufferable) { 96010259SAndrew.Bardsley@arm.com if (!execute.instIsHeadInst(request->inst)) { 96110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Memory access not the head inst., can't be" 96210259SAndrew.Bardsley@arm.com " sure it can be performed, not issuing\n"); 96310259SAndrew.Bardsley@arm.com return; 96410259SAndrew.Bardsley@arm.com } 96510259SAndrew.Bardsley@arm.com 96610259SAndrew.Bardsley@arm.com unsigned int forwarding_slot = 0; 96710259SAndrew.Bardsley@arm.com 96810259SAndrew.Bardsley@arm.com if (storeBuffer.canForwardDataToLoad(request, forwarding_slot) != 96910259SAndrew.Bardsley@arm.com NoAddrRangeCoverage) 97010259SAndrew.Bardsley@arm.com { 97110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Memory access can receive forwarded data" 97210259SAndrew.Bardsley@arm.com " from the store buffer, need to wait for store buffer to" 97310259SAndrew.Bardsley@arm.com " drain\n"); 97410259SAndrew.Bardsley@arm.com return; 97510259SAndrew.Bardsley@arm.com } 97610259SAndrew.Bardsley@arm.com } 97710259SAndrew.Bardsley@arm.com 97810259SAndrew.Bardsley@arm.com /* True: submit this packet to the transfers queue to be sent to the 97910259SAndrew.Bardsley@arm.com * memory system. 98010259SAndrew.Bardsley@arm.com * False: skip the memory and push a packet for this request onto 98110259SAndrew.Bardsley@arm.com * requests */ 98210259SAndrew.Bardsley@arm.com bool do_access = true; 98310259SAndrew.Bardsley@arm.com 98410259SAndrew.Bardsley@arm.com if (!is_llsc) { 98510259SAndrew.Bardsley@arm.com /* Check for match in the store buffer */ 98610259SAndrew.Bardsley@arm.com if (is_load) { 98710259SAndrew.Bardsley@arm.com unsigned int forwarding_slot = 0; 98810259SAndrew.Bardsley@arm.com AddrRangeCoverage forwarding_result = 98910259SAndrew.Bardsley@arm.com storeBuffer.canForwardDataToLoad(request, 99010259SAndrew.Bardsley@arm.com forwarding_slot); 99110259SAndrew.Bardsley@arm.com 99210259SAndrew.Bardsley@arm.com switch (forwarding_result) { 99310259SAndrew.Bardsley@arm.com case FullAddrRangeCoverage: 99410259SAndrew.Bardsley@arm.com /* Forward data from the store buffer into this request and 99510259SAndrew.Bardsley@arm.com * repurpose this request's packet into a response packet */ 99610259SAndrew.Bardsley@arm.com storeBuffer.forwardStoreData(request, forwarding_slot); 99710259SAndrew.Bardsley@arm.com request->packet->makeResponse(); 99810259SAndrew.Bardsley@arm.com 99910259SAndrew.Bardsley@arm.com /* Just move between queues, no access */ 100010259SAndrew.Bardsley@arm.com do_access = false; 100110259SAndrew.Bardsley@arm.com break; 100210259SAndrew.Bardsley@arm.com case PartialAddrRangeCoverage: 100310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Load partly satisfied by store buffer" 100410259SAndrew.Bardsley@arm.com " data. Must wait for the store to complete\n"); 100510259SAndrew.Bardsley@arm.com return; 100610259SAndrew.Bardsley@arm.com break; 100710259SAndrew.Bardsley@arm.com case NoAddrRangeCoverage: 100810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "No forwardable data from store buffer\n"); 100910259SAndrew.Bardsley@arm.com /* Fall through to try access */ 101010259SAndrew.Bardsley@arm.com break; 101110259SAndrew.Bardsley@arm.com } 101210259SAndrew.Bardsley@arm.com } 101310259SAndrew.Bardsley@arm.com } else { 101410259SAndrew.Bardsley@arm.com if (!canSendToMemorySystem()) { 101510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Can't send request to memory system yet\n"); 101610259SAndrew.Bardsley@arm.com return; 101710259SAndrew.Bardsley@arm.com } 101810259SAndrew.Bardsley@arm.com 101910259SAndrew.Bardsley@arm.com SimpleThread &thread = *cpu.threads[request->inst->id.threadId]; 102010259SAndrew.Bardsley@arm.com 102110259SAndrew.Bardsley@arm.com TheISA::PCState old_pc = thread.pcState(); 102210259SAndrew.Bardsley@arm.com ExecContext context(cpu, thread, execute, request->inst); 102310259SAndrew.Bardsley@arm.com 102410259SAndrew.Bardsley@arm.com /* Handle LLSC requests and tests */ 102510259SAndrew.Bardsley@arm.com if (is_load) { 102610259SAndrew.Bardsley@arm.com TheISA::handleLockedRead(&context, &request->request); 102710259SAndrew.Bardsley@arm.com } else { 102810259SAndrew.Bardsley@arm.com do_access = TheISA::handleLockedWrite(&context, 102910259SAndrew.Bardsley@arm.com &request->request, cacheBlockMask); 103010259SAndrew.Bardsley@arm.com 103110259SAndrew.Bardsley@arm.com if (!do_access) { 103210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Not perfoming a memory " 103310259SAndrew.Bardsley@arm.com "access for store conditional\n"); 103410259SAndrew.Bardsley@arm.com } 103510259SAndrew.Bardsley@arm.com } 103610259SAndrew.Bardsley@arm.com thread.pcState(old_pc); 103710259SAndrew.Bardsley@arm.com } 103810259SAndrew.Bardsley@arm.com 103910259SAndrew.Bardsley@arm.com /* See the do_access comment above */ 104010259SAndrew.Bardsley@arm.com if (do_access) { 104110259SAndrew.Bardsley@arm.com if (!canSendToMemorySystem()) { 104210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Can't send request to memory system yet\n"); 104310259SAndrew.Bardsley@arm.com return; 104410259SAndrew.Bardsley@arm.com } 104510259SAndrew.Bardsley@arm.com 104610259SAndrew.Bardsley@arm.com /* Remember if this is an access which can't be idly 104710259SAndrew.Bardsley@arm.com * discarded by an interrupt */ 104810368SAndrew.Bardsley@arm.com if (!bufferable && !request->issuedToMemory) { 104910259SAndrew.Bardsley@arm.com numAccessesIssuedToMemory++; 105010259SAndrew.Bardsley@arm.com request->issuedToMemory = true; 105110259SAndrew.Bardsley@arm.com } 105210259SAndrew.Bardsley@arm.com 105311567Smitch.hayenga@arm.com if (tryToSend(request)) { 105410259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 105511567Smitch.hayenga@arm.com } 105610259SAndrew.Bardsley@arm.com } else { 105710259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 105810259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 105910259SAndrew.Bardsley@arm.com } 106010259SAndrew.Bardsley@arm.com} 106110259SAndrew.Bardsley@arm.com 106210259SAndrew.Bardsley@arm.combool 106310259SAndrew.Bardsley@arm.comLSQ::tryToSend(LSQRequestPtr request) 106410259SAndrew.Bardsley@arm.com{ 106510259SAndrew.Bardsley@arm.com bool ret = false; 106610259SAndrew.Bardsley@arm.com 106710259SAndrew.Bardsley@arm.com if (!canSendToMemorySystem()) { 106810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Can't send request: %s yet, no space in memory\n", 106910259SAndrew.Bardsley@arm.com *(request->inst)); 107010259SAndrew.Bardsley@arm.com } else { 107110259SAndrew.Bardsley@arm.com PacketPtr packet = request->getHeadPacket(); 107210259SAndrew.Bardsley@arm.com 107310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Trying to send request: %s addr: 0x%x\n", 107410259SAndrew.Bardsley@arm.com *(request->inst), packet->req->getVaddr()); 107510259SAndrew.Bardsley@arm.com 107610259SAndrew.Bardsley@arm.com /* The sender state of the packet *must* be an LSQRequest 107710259SAndrew.Bardsley@arm.com * so the response can be correctly handled */ 107810259SAndrew.Bardsley@arm.com assert(packet->findNextSenderState<LSQRequest>()); 107910259SAndrew.Bardsley@arm.com 108010259SAndrew.Bardsley@arm.com if (request->request.isMmappedIpr()) { 108110259SAndrew.Bardsley@arm.com ThreadContext *thread = 108211435Smitch.hayenga@arm.com cpu.getContext(cpu.contextToThread( 108311435Smitch.hayenga@arm.com request->request.contextId())); 108410259SAndrew.Bardsley@arm.com 108510259SAndrew.Bardsley@arm.com if (request->isLoad) { 108610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "IPR read inst: %s\n", *(request->inst)); 108710259SAndrew.Bardsley@arm.com TheISA::handleIprRead(thread, packet); 108810259SAndrew.Bardsley@arm.com } else { 108910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "IPR write inst: %s\n", *(request->inst)); 109010259SAndrew.Bardsley@arm.com TheISA::handleIprWrite(thread, packet); 109110259SAndrew.Bardsley@arm.com } 109210259SAndrew.Bardsley@arm.com 109310259SAndrew.Bardsley@arm.com request->stepToNextPacket(); 109410259SAndrew.Bardsley@arm.com ret = request->sentAllPackets(); 109510259SAndrew.Bardsley@arm.com 109610259SAndrew.Bardsley@arm.com if (!ret) { 109710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "IPR access has another packet: %s\n", 109810259SAndrew.Bardsley@arm.com *(request->inst)); 109910259SAndrew.Bardsley@arm.com } 110010259SAndrew.Bardsley@arm.com 110110259SAndrew.Bardsley@arm.com if (ret) 110210259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 110310259SAndrew.Bardsley@arm.com else 110410259SAndrew.Bardsley@arm.com request->setState(LSQRequest::RequestIssuing); 110510259SAndrew.Bardsley@arm.com } else if (dcachePort.sendTimingReq(packet)) { 110610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Sent data memory request\n"); 110710259SAndrew.Bardsley@arm.com 110810259SAndrew.Bardsley@arm.com numAccessesInMemorySystem++; 110910259SAndrew.Bardsley@arm.com 111010259SAndrew.Bardsley@arm.com request->stepToNextPacket(); 111110259SAndrew.Bardsley@arm.com 111210259SAndrew.Bardsley@arm.com ret = request->sentAllPackets(); 111310259SAndrew.Bardsley@arm.com 111410259SAndrew.Bardsley@arm.com switch (request->state) { 111510259SAndrew.Bardsley@arm.com case LSQRequest::Translated: 111610259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 111710259SAndrew.Bardsley@arm.com /* Fully or partially issued a request in the transfers 111810259SAndrew.Bardsley@arm.com * queue */ 111910259SAndrew.Bardsley@arm.com request->setState(LSQRequest::RequestIssuing); 112010259SAndrew.Bardsley@arm.com break; 112110259SAndrew.Bardsley@arm.com case LSQRequest::StoreInStoreBuffer: 112210259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 112310259SAndrew.Bardsley@arm.com /* Fully or partially issued a request in the store 112410259SAndrew.Bardsley@arm.com * buffer */ 112510259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreBufferIssuing); 112610259SAndrew.Bardsley@arm.com break; 112710259SAndrew.Bardsley@arm.com default: 112810259SAndrew.Bardsley@arm.com assert(false); 112910259SAndrew.Bardsley@arm.com break; 113010259SAndrew.Bardsley@arm.com } 113110259SAndrew.Bardsley@arm.com 113210259SAndrew.Bardsley@arm.com state = MemoryRunning; 113310259SAndrew.Bardsley@arm.com } else { 113410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, 113510259SAndrew.Bardsley@arm.com "Sending data memory request - needs retry\n"); 113610259SAndrew.Bardsley@arm.com 113710259SAndrew.Bardsley@arm.com /* Needs to be resent, wait for that */ 113810259SAndrew.Bardsley@arm.com state = MemoryNeedsRetry; 113910259SAndrew.Bardsley@arm.com retryRequest = request; 114010259SAndrew.Bardsley@arm.com 114110259SAndrew.Bardsley@arm.com switch (request->state) { 114210259SAndrew.Bardsley@arm.com case LSQRequest::Translated: 114310259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 114410259SAndrew.Bardsley@arm.com request->setState(LSQRequest::RequestNeedsRetry); 114510259SAndrew.Bardsley@arm.com break; 114610259SAndrew.Bardsley@arm.com case LSQRequest::StoreInStoreBuffer: 114710259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 114810259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreBufferNeedsRetry); 114910259SAndrew.Bardsley@arm.com break; 115010259SAndrew.Bardsley@arm.com default: 115110259SAndrew.Bardsley@arm.com assert(false); 115210259SAndrew.Bardsley@arm.com break; 115310259SAndrew.Bardsley@arm.com } 115410259SAndrew.Bardsley@arm.com } 115510259SAndrew.Bardsley@arm.com } 115610259SAndrew.Bardsley@arm.com 115711567Smitch.hayenga@arm.com if (ret) 115811567Smitch.hayenga@arm.com threadSnoop(request); 115911567Smitch.hayenga@arm.com 116010259SAndrew.Bardsley@arm.com return ret; 116110259SAndrew.Bardsley@arm.com} 116210259SAndrew.Bardsley@arm.com 116310259SAndrew.Bardsley@arm.comvoid 116410259SAndrew.Bardsley@arm.comLSQ::moveFromRequestsToTransfers(LSQRequestPtr request) 116510259SAndrew.Bardsley@arm.com{ 116610259SAndrew.Bardsley@arm.com assert(!requests.empty() && requests.front() == request); 116710259SAndrew.Bardsley@arm.com assert(transfers.unreservedRemainingSpace() != 0); 116810259SAndrew.Bardsley@arm.com 116910259SAndrew.Bardsley@arm.com /* Need to count the number of stores in the transfers 117010259SAndrew.Bardsley@arm.com * queue so that loads know when their store buffer forwarding 117110259SAndrew.Bardsley@arm.com * results will be correct (only when all those stores 117210259SAndrew.Bardsley@arm.com * have reached the store buffer) */ 117310259SAndrew.Bardsley@arm.com if (!request->isLoad) 117410259SAndrew.Bardsley@arm.com numStoresInTransfers++; 117510259SAndrew.Bardsley@arm.com 117610259SAndrew.Bardsley@arm.com requests.pop(); 117710259SAndrew.Bardsley@arm.com transfers.push(request); 117810259SAndrew.Bardsley@arm.com} 117910259SAndrew.Bardsley@arm.com 118010259SAndrew.Bardsley@arm.combool 118110259SAndrew.Bardsley@arm.comLSQ::canSendToMemorySystem() 118210259SAndrew.Bardsley@arm.com{ 118310259SAndrew.Bardsley@arm.com return state == MemoryRunning && 118410259SAndrew.Bardsley@arm.com numAccessesInMemorySystem < inMemorySystemLimit; 118510259SAndrew.Bardsley@arm.com} 118610259SAndrew.Bardsley@arm.com 118710259SAndrew.Bardsley@arm.combool 118810259SAndrew.Bardsley@arm.comLSQ::recvTimingResp(PacketPtr response) 118910259SAndrew.Bardsley@arm.com{ 119010259SAndrew.Bardsley@arm.com LSQRequestPtr request = 119110259SAndrew.Bardsley@arm.com safe_cast<LSQRequestPtr>(response->popSenderState()); 119210259SAndrew.Bardsley@arm.com 119310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Received response packet inst: %s" 119410259SAndrew.Bardsley@arm.com " addr: 0x%x cmd: %s\n", 119510259SAndrew.Bardsley@arm.com *(request->inst), response->getAddr(), 119610259SAndrew.Bardsley@arm.com response->cmd.toString()); 119710259SAndrew.Bardsley@arm.com 119810259SAndrew.Bardsley@arm.com numAccessesInMemorySystem--; 119910259SAndrew.Bardsley@arm.com 120010259SAndrew.Bardsley@arm.com if (response->isError()) { 120110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Received error response packet: %s\n", 120210259SAndrew.Bardsley@arm.com *request->inst); 120310259SAndrew.Bardsley@arm.com } 120410259SAndrew.Bardsley@arm.com 120510259SAndrew.Bardsley@arm.com switch (request->state) { 120610259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 120710259SAndrew.Bardsley@arm.com case LSQRequest::RequestNeedsRetry: 120810259SAndrew.Bardsley@arm.com /* Response to a request from the transfers queue */ 120910259SAndrew.Bardsley@arm.com request->retireResponse(response); 121010259SAndrew.Bardsley@arm.com 121110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Has outstanding packets?: %d %d\n", 121210259SAndrew.Bardsley@arm.com request->hasPacketsInMemSystem(), request->isComplete()); 121310259SAndrew.Bardsley@arm.com 121410259SAndrew.Bardsley@arm.com break; 121510259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 121610259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferNeedsRetry: 121710259SAndrew.Bardsley@arm.com /* Response to a request from the store buffer */ 121810259SAndrew.Bardsley@arm.com request->retireResponse(response); 121910259SAndrew.Bardsley@arm.com 122010581SAndrew.Bardsley@arm.com /* Remove completed requests unless they are barriers (which will 122110259SAndrew.Bardsley@arm.com * need to be removed in order */ 122210259SAndrew.Bardsley@arm.com if (request->isComplete()) { 122310259SAndrew.Bardsley@arm.com if (!request->isBarrier()) { 122410259SAndrew.Bardsley@arm.com storeBuffer.deleteRequest(request); 122510259SAndrew.Bardsley@arm.com } else { 122610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Completed transfer for barrier: %s" 122710259SAndrew.Bardsley@arm.com " leaving the request as it is also a barrier\n", 122810259SAndrew.Bardsley@arm.com *(request->inst)); 122910259SAndrew.Bardsley@arm.com } 123010259SAndrew.Bardsley@arm.com } 123110259SAndrew.Bardsley@arm.com break; 123210259SAndrew.Bardsley@arm.com default: 123310259SAndrew.Bardsley@arm.com /* Shouldn't be allowed to receive a response from another 123410259SAndrew.Bardsley@arm.com * state */ 123510259SAndrew.Bardsley@arm.com assert(false); 123610259SAndrew.Bardsley@arm.com break; 123710259SAndrew.Bardsley@arm.com } 123810259SAndrew.Bardsley@arm.com 123910259SAndrew.Bardsley@arm.com /* We go to idle even if there are more things in the requests queue 124010259SAndrew.Bardsley@arm.com * as it's the job of step to actually step us on to the next 124110259SAndrew.Bardsley@arm.com * transaction */ 124210259SAndrew.Bardsley@arm.com 124310259SAndrew.Bardsley@arm.com /* Let's try and wake up the processor for the next cycle */ 124410259SAndrew.Bardsley@arm.com cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 124510259SAndrew.Bardsley@arm.com 124610259SAndrew.Bardsley@arm.com /* Never busy */ 124710259SAndrew.Bardsley@arm.com return true; 124810259SAndrew.Bardsley@arm.com} 124910259SAndrew.Bardsley@arm.com 125010259SAndrew.Bardsley@arm.comvoid 125110713Sandreas.hansson@arm.comLSQ::recvReqRetry() 125210259SAndrew.Bardsley@arm.com{ 125310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Received retry request\n"); 125410259SAndrew.Bardsley@arm.com 125510259SAndrew.Bardsley@arm.com assert(state == MemoryNeedsRetry); 125610259SAndrew.Bardsley@arm.com 125710259SAndrew.Bardsley@arm.com switch (retryRequest->state) { 125810259SAndrew.Bardsley@arm.com case LSQRequest::RequestNeedsRetry: 125910259SAndrew.Bardsley@arm.com /* Retry in the requests queue */ 126010259SAndrew.Bardsley@arm.com retryRequest->setState(LSQRequest::Translated); 126110259SAndrew.Bardsley@arm.com break; 126210259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferNeedsRetry: 126310259SAndrew.Bardsley@arm.com /* Retry in the store buffer */ 126410259SAndrew.Bardsley@arm.com retryRequest->setState(LSQRequest::StoreInStoreBuffer); 126510259SAndrew.Bardsley@arm.com break; 126610259SAndrew.Bardsley@arm.com default: 126710259SAndrew.Bardsley@arm.com assert(false); 126810259SAndrew.Bardsley@arm.com } 126910259SAndrew.Bardsley@arm.com 127010259SAndrew.Bardsley@arm.com /* Set state back to MemoryRunning so that the following 127110259SAndrew.Bardsley@arm.com * tryToSend can actually send. Note that this won't 127210259SAndrew.Bardsley@arm.com * allow another transfer in as tryToSend should 127310259SAndrew.Bardsley@arm.com * issue a memory request and either succeed for this 127410259SAndrew.Bardsley@arm.com * request or return the LSQ back to MemoryNeedsRetry */ 127510259SAndrew.Bardsley@arm.com state = MemoryRunning; 127610259SAndrew.Bardsley@arm.com 127710259SAndrew.Bardsley@arm.com /* Try to resend the request */ 127810259SAndrew.Bardsley@arm.com if (tryToSend(retryRequest)) { 127910259SAndrew.Bardsley@arm.com /* Successfully sent, need to move the request */ 128010259SAndrew.Bardsley@arm.com switch (retryRequest->state) { 128110259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 128210259SAndrew.Bardsley@arm.com /* In the requests queue */ 128310259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(retryRequest); 128410259SAndrew.Bardsley@arm.com break; 128510259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 128610259SAndrew.Bardsley@arm.com /* In the store buffer */ 128710581SAndrew.Bardsley@arm.com storeBuffer.countIssuedStore(retryRequest); 128810259SAndrew.Bardsley@arm.com break; 128910259SAndrew.Bardsley@arm.com default: 129010259SAndrew.Bardsley@arm.com assert(false); 129110259SAndrew.Bardsley@arm.com break; 129210259SAndrew.Bardsley@arm.com } 129310647Sandreas.hansson@arm.com 129410647Sandreas.hansson@arm.com retryRequest = NULL; 129510259SAndrew.Bardsley@arm.com } 129610259SAndrew.Bardsley@arm.com} 129710259SAndrew.Bardsley@arm.com 129810259SAndrew.Bardsley@arm.comLSQ::LSQ(std::string name_, std::string dcache_port_name_, 129910259SAndrew.Bardsley@arm.com MinorCPU &cpu_, Execute &execute_, 130010259SAndrew.Bardsley@arm.com unsigned int in_memory_system_limit, unsigned int line_width, 130110259SAndrew.Bardsley@arm.com unsigned int requests_queue_size, unsigned int transfers_queue_size, 130210259SAndrew.Bardsley@arm.com unsigned int store_buffer_size, 130310259SAndrew.Bardsley@arm.com unsigned int store_buffer_cycle_store_limit) : 130410259SAndrew.Bardsley@arm.com Named(name_), 130510259SAndrew.Bardsley@arm.com cpu(cpu_), 130610259SAndrew.Bardsley@arm.com execute(execute_), 130710259SAndrew.Bardsley@arm.com dcachePort(dcache_port_name_, *this, cpu_), 130811567Smitch.hayenga@arm.com lastMemBarrier(cpu.numThreads, 0), 130910259SAndrew.Bardsley@arm.com state(MemoryRunning), 131010259SAndrew.Bardsley@arm.com inMemorySystemLimit(in_memory_system_limit), 131110259SAndrew.Bardsley@arm.com lineWidth((line_width == 0 ? cpu.cacheLineSize() : line_width)), 131210259SAndrew.Bardsley@arm.com requests(name_ + ".requests", "addr", requests_queue_size), 131310259SAndrew.Bardsley@arm.com transfers(name_ + ".transfers", "addr", transfers_queue_size), 131410259SAndrew.Bardsley@arm.com storeBuffer(name_ + ".storeBuffer", 131510259SAndrew.Bardsley@arm.com *this, store_buffer_size, store_buffer_cycle_store_limit), 131610259SAndrew.Bardsley@arm.com numAccessesInMemorySystem(0), 131710259SAndrew.Bardsley@arm.com numAccessesInDTLB(0), 131810259SAndrew.Bardsley@arm.com numStoresInTransfers(0), 131910259SAndrew.Bardsley@arm.com numAccessesIssuedToMemory(0), 132010259SAndrew.Bardsley@arm.com retryRequest(NULL), 132110259SAndrew.Bardsley@arm.com cacheBlockMask(~(cpu_.cacheLineSize() - 1)) 132210259SAndrew.Bardsley@arm.com{ 132310259SAndrew.Bardsley@arm.com if (in_memory_system_limit < 1) { 132410259SAndrew.Bardsley@arm.com fatal("%s: executeMaxAccessesInMemory must be >= 1 (%d)\n", name_, 132510259SAndrew.Bardsley@arm.com in_memory_system_limit); 132610259SAndrew.Bardsley@arm.com } 132710259SAndrew.Bardsley@arm.com 132810259SAndrew.Bardsley@arm.com if (store_buffer_cycle_store_limit < 1) { 132910259SAndrew.Bardsley@arm.com fatal("%s: executeLSQMaxStoreBufferStoresPerCycle must be" 133010259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, store_buffer_cycle_store_limit); 133110259SAndrew.Bardsley@arm.com } 133210259SAndrew.Bardsley@arm.com 133310259SAndrew.Bardsley@arm.com if (requests_queue_size < 1) { 133410259SAndrew.Bardsley@arm.com fatal("%s: executeLSQRequestsQueueSize must be" 133510259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, requests_queue_size); 133610259SAndrew.Bardsley@arm.com } 133710259SAndrew.Bardsley@arm.com 133810259SAndrew.Bardsley@arm.com if (transfers_queue_size < 1) { 133910259SAndrew.Bardsley@arm.com fatal("%s: executeLSQTransfersQueueSize must be" 134010259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, transfers_queue_size); 134110259SAndrew.Bardsley@arm.com } 134210259SAndrew.Bardsley@arm.com 134310259SAndrew.Bardsley@arm.com if (store_buffer_size < 1) { 134410259SAndrew.Bardsley@arm.com fatal("%s: executeLSQStoreBufferSize must be" 134510259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, store_buffer_size); 134610259SAndrew.Bardsley@arm.com } 134710259SAndrew.Bardsley@arm.com 134810259SAndrew.Bardsley@arm.com if ((lineWidth & (lineWidth - 1)) != 0) { 134910259SAndrew.Bardsley@arm.com fatal("%s: lineWidth: %d must be a power of 2\n", name(), lineWidth); 135010259SAndrew.Bardsley@arm.com } 135110259SAndrew.Bardsley@arm.com} 135210259SAndrew.Bardsley@arm.com 135310259SAndrew.Bardsley@arm.comLSQ::~LSQ() 135410259SAndrew.Bardsley@arm.com{ } 135510259SAndrew.Bardsley@arm.com 135610259SAndrew.Bardsley@arm.comLSQ::LSQRequest::~LSQRequest() 135710259SAndrew.Bardsley@arm.com{ 135810259SAndrew.Bardsley@arm.com if (packet) 135910259SAndrew.Bardsley@arm.com delete packet; 136010259SAndrew.Bardsley@arm.com if (data) 136110259SAndrew.Bardsley@arm.com delete [] data; 136210259SAndrew.Bardsley@arm.com} 136310259SAndrew.Bardsley@arm.com 136410259SAndrew.Bardsley@arm.com/** 136510259SAndrew.Bardsley@arm.com * Step the memory access mechanism on to its next state. In reality, most 136610259SAndrew.Bardsley@arm.com * of the stepping is done by the callbacks on the LSQ but this 136710259SAndrew.Bardsley@arm.com * function is responsible for issuing memory requests lodged in the 136810259SAndrew.Bardsley@arm.com * requests queue. 136910259SAndrew.Bardsley@arm.com */ 137010259SAndrew.Bardsley@arm.comvoid 137110259SAndrew.Bardsley@arm.comLSQ::step() 137210259SAndrew.Bardsley@arm.com{ 137310259SAndrew.Bardsley@arm.com /* Try to move address-translated requests between queues and issue 137410259SAndrew.Bardsley@arm.com * them */ 137510259SAndrew.Bardsley@arm.com if (!requests.empty()) 137610259SAndrew.Bardsley@arm.com tryToSendToTransfers(requests.front()); 137710259SAndrew.Bardsley@arm.com 137810259SAndrew.Bardsley@arm.com storeBuffer.step(); 137910259SAndrew.Bardsley@arm.com} 138010259SAndrew.Bardsley@arm.com 138110259SAndrew.Bardsley@arm.comLSQ::LSQRequestPtr 138210259SAndrew.Bardsley@arm.comLSQ::findResponse(MinorDynInstPtr inst) 138310259SAndrew.Bardsley@arm.com{ 138410259SAndrew.Bardsley@arm.com LSQ::LSQRequestPtr ret = NULL; 138510259SAndrew.Bardsley@arm.com 138610259SAndrew.Bardsley@arm.com if (!transfers.empty()) { 138710259SAndrew.Bardsley@arm.com LSQRequestPtr request = transfers.front(); 138810259SAndrew.Bardsley@arm.com 138910259SAndrew.Bardsley@arm.com /* Same instruction and complete access or a store that's 139010259SAndrew.Bardsley@arm.com * capable of being moved to the store buffer */ 139110259SAndrew.Bardsley@arm.com if (request->inst->id == inst->id) { 139210504SAndrew.Bardsley@arm.com bool complete = request->isComplete(); 139310504SAndrew.Bardsley@arm.com bool can_store = storeBuffer.canInsert(); 139410504SAndrew.Bardsley@arm.com bool to_store_buffer = request->state == 139510504SAndrew.Bardsley@arm.com LSQRequest::StoreToStoreBuffer; 139610504SAndrew.Bardsley@arm.com 139710504SAndrew.Bardsley@arm.com if ((complete && !(request->isBarrier() && !can_store)) || 139810504SAndrew.Bardsley@arm.com (to_store_buffer && can_store)) 139910259SAndrew.Bardsley@arm.com { 140010259SAndrew.Bardsley@arm.com ret = request; 140110259SAndrew.Bardsley@arm.com } 140210259SAndrew.Bardsley@arm.com } 140310259SAndrew.Bardsley@arm.com } 140410259SAndrew.Bardsley@arm.com 140510259SAndrew.Bardsley@arm.com if (ret) { 140610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Found matching memory response for inst: %s\n", 140710259SAndrew.Bardsley@arm.com *inst); 140810259SAndrew.Bardsley@arm.com } else { 140910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "No matching memory response for inst: %s\n", 141010259SAndrew.Bardsley@arm.com *inst); 141110259SAndrew.Bardsley@arm.com } 141210259SAndrew.Bardsley@arm.com 141310259SAndrew.Bardsley@arm.com return ret; 141410259SAndrew.Bardsley@arm.com} 141510259SAndrew.Bardsley@arm.com 141610259SAndrew.Bardsley@arm.comvoid 141710259SAndrew.Bardsley@arm.comLSQ::popResponse(LSQ::LSQRequestPtr response) 141810259SAndrew.Bardsley@arm.com{ 141910259SAndrew.Bardsley@arm.com assert(!transfers.empty() && transfers.front() == response); 142010259SAndrew.Bardsley@arm.com 142110259SAndrew.Bardsley@arm.com transfers.pop(); 142210259SAndrew.Bardsley@arm.com 142310259SAndrew.Bardsley@arm.com if (!response->isLoad) 142410259SAndrew.Bardsley@arm.com numStoresInTransfers--; 142510259SAndrew.Bardsley@arm.com 142610259SAndrew.Bardsley@arm.com if (response->issuedToMemory) 142710259SAndrew.Bardsley@arm.com numAccessesIssuedToMemory--; 142810259SAndrew.Bardsley@arm.com 142910259SAndrew.Bardsley@arm.com if (response->state != LSQRequest::StoreInStoreBuffer) { 143010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Deleting %s request: %s\n", 143110259SAndrew.Bardsley@arm.com (response->isLoad ? "load" : "store"), 143210259SAndrew.Bardsley@arm.com *(response->inst)); 143310259SAndrew.Bardsley@arm.com 143410259SAndrew.Bardsley@arm.com delete response; 143510259SAndrew.Bardsley@arm.com } 143610259SAndrew.Bardsley@arm.com} 143710259SAndrew.Bardsley@arm.com 143810259SAndrew.Bardsley@arm.comvoid 143910259SAndrew.Bardsley@arm.comLSQ::sendStoreToStoreBuffer(LSQRequestPtr request) 144010259SAndrew.Bardsley@arm.com{ 144110259SAndrew.Bardsley@arm.com assert(request->state == LSQRequest::StoreToStoreBuffer); 144210259SAndrew.Bardsley@arm.com 144310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Sending store: %s to store buffer\n", 144410259SAndrew.Bardsley@arm.com *(request->inst)); 144510259SAndrew.Bardsley@arm.com 144610259SAndrew.Bardsley@arm.com request->inst->inStoreBuffer = true; 144710259SAndrew.Bardsley@arm.com 144810259SAndrew.Bardsley@arm.com storeBuffer.insert(request); 144910259SAndrew.Bardsley@arm.com} 145010259SAndrew.Bardsley@arm.com 145110259SAndrew.Bardsley@arm.combool 145210259SAndrew.Bardsley@arm.comLSQ::isDrained() 145310259SAndrew.Bardsley@arm.com{ 145410259SAndrew.Bardsley@arm.com return requests.empty() && transfers.empty() && 145510259SAndrew.Bardsley@arm.com storeBuffer.isDrained(); 145610259SAndrew.Bardsley@arm.com} 145710259SAndrew.Bardsley@arm.com 145810259SAndrew.Bardsley@arm.combool 145910259SAndrew.Bardsley@arm.comLSQ::needsToTick() 146010259SAndrew.Bardsley@arm.com{ 146110259SAndrew.Bardsley@arm.com bool ret = false; 146210259SAndrew.Bardsley@arm.com 146310259SAndrew.Bardsley@arm.com if (canSendToMemorySystem()) { 146410259SAndrew.Bardsley@arm.com bool have_translated_requests = !requests.empty() && 146510259SAndrew.Bardsley@arm.com requests.front()->state != LSQRequest::InTranslation && 146610259SAndrew.Bardsley@arm.com transfers.unreservedRemainingSpace() != 0; 146710259SAndrew.Bardsley@arm.com 146810259SAndrew.Bardsley@arm.com ret = have_translated_requests || 146910259SAndrew.Bardsley@arm.com storeBuffer.numUnissuedStores() != 0; 147010259SAndrew.Bardsley@arm.com } 147110259SAndrew.Bardsley@arm.com 147210259SAndrew.Bardsley@arm.com if (ret) 147310259SAndrew.Bardsley@arm.com DPRINTF(Activity, "Need to tick\n"); 147410259SAndrew.Bardsley@arm.com 147510259SAndrew.Bardsley@arm.com return ret; 147610259SAndrew.Bardsley@arm.com} 147710259SAndrew.Bardsley@arm.com 147810259SAndrew.Bardsley@arm.comvoid 147910259SAndrew.Bardsley@arm.comLSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, 148011608Snikos.nikoleris@arm.com unsigned int size, Addr addr, Request::Flags flags, 148111608Snikos.nikoleris@arm.com uint64_t *res) 148210259SAndrew.Bardsley@arm.com{ 148310259SAndrew.Bardsley@arm.com bool needs_burst = transferNeedsBurst(addr, size, lineWidth); 148410259SAndrew.Bardsley@arm.com LSQRequestPtr request; 148510259SAndrew.Bardsley@arm.com 148610259SAndrew.Bardsley@arm.com /* Copy given data into the request. The request will pass this to the 148710259SAndrew.Bardsley@arm.com * packet and then it will own the data */ 148810259SAndrew.Bardsley@arm.com uint8_t *request_data = NULL; 148910259SAndrew.Bardsley@arm.com 149010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Pushing request (%s) addr: 0x%x size: %d flags:" 149110259SAndrew.Bardsley@arm.com " 0x%x%s lineWidth : 0x%x\n", 149210259SAndrew.Bardsley@arm.com (isLoad ? "load" : "store"), addr, size, flags, 149310259SAndrew.Bardsley@arm.com (needs_burst ? " (needs burst)" : ""), lineWidth); 149410259SAndrew.Bardsley@arm.com 149510259SAndrew.Bardsley@arm.com if (!isLoad) { 149610259SAndrew.Bardsley@arm.com /* request_data becomes the property of a ...DataRequest (see below) 149710259SAndrew.Bardsley@arm.com * and destroyed by its destructor */ 149810259SAndrew.Bardsley@arm.com request_data = new uint8_t[size]; 149912355Snikos.nikoleris@arm.com if (flags & Request::STORE_NO_DATA) { 150010259SAndrew.Bardsley@arm.com /* For cache zeroing, just use zeroed data */ 150110259SAndrew.Bardsley@arm.com std::memset(request_data, 0, size); 150210259SAndrew.Bardsley@arm.com } else { 150310259SAndrew.Bardsley@arm.com std::memcpy(request_data, data, size); 150410259SAndrew.Bardsley@arm.com } 150510259SAndrew.Bardsley@arm.com } 150610259SAndrew.Bardsley@arm.com 150710259SAndrew.Bardsley@arm.com if (needs_burst) { 150810259SAndrew.Bardsley@arm.com request = new SplitDataRequest( 150910259SAndrew.Bardsley@arm.com *this, inst, isLoad, request_data, res); 151010259SAndrew.Bardsley@arm.com } else { 151110259SAndrew.Bardsley@arm.com request = new SingleDataRequest( 151210259SAndrew.Bardsley@arm.com *this, inst, isLoad, request_data, res); 151310259SAndrew.Bardsley@arm.com } 151410259SAndrew.Bardsley@arm.com 151510259SAndrew.Bardsley@arm.com if (inst->traceData) 151610665SAli.Saidi@ARM.com inst->traceData->setMem(addr, size, flags); 151710259SAndrew.Bardsley@arm.com 151811148Smitch.hayenga@arm.com int cid = cpu.threads[inst->id.threadId]->getTC()->contextId(); 151911435Smitch.hayenga@arm.com request->request.setContext(cid); 152010259SAndrew.Bardsley@arm.com request->request.setVirt(0 /* asid */, 152110634Slukefahr@umich.edu addr, size, flags, cpu.dataMasterId(), 152210259SAndrew.Bardsley@arm.com /* I've no idea why we need the PC, but give it */ 152310259SAndrew.Bardsley@arm.com inst->pc.instAddr()); 152410259SAndrew.Bardsley@arm.com 152510259SAndrew.Bardsley@arm.com requests.push(request); 152610259SAndrew.Bardsley@arm.com request->startAddrTranslation(); 152710259SAndrew.Bardsley@arm.com} 152810259SAndrew.Bardsley@arm.com 152910259SAndrew.Bardsley@arm.comvoid 153010259SAndrew.Bardsley@arm.comLSQ::pushFailedRequest(MinorDynInstPtr inst) 153110259SAndrew.Bardsley@arm.com{ 153210259SAndrew.Bardsley@arm.com LSQRequestPtr request = new FailedDataRequest(*this, inst); 153310259SAndrew.Bardsley@arm.com requests.push(request); 153410259SAndrew.Bardsley@arm.com} 153510259SAndrew.Bardsley@arm.com 153610259SAndrew.Bardsley@arm.comvoid 153710259SAndrew.Bardsley@arm.comLSQ::minorTrace() const 153810259SAndrew.Bardsley@arm.com{ 153910259SAndrew.Bardsley@arm.com MINORTRACE("state=%s in_tlb_mem=%d/%d stores_in_transfers=%d" 154010259SAndrew.Bardsley@arm.com " lastMemBarrier=%d\n", 154110259SAndrew.Bardsley@arm.com state, numAccessesInDTLB, numAccessesInMemorySystem, 154211567Smitch.hayenga@arm.com numStoresInTransfers, lastMemBarrier[0]); 154310259SAndrew.Bardsley@arm.com requests.minorTrace(); 154410259SAndrew.Bardsley@arm.com transfers.minorTrace(); 154510259SAndrew.Bardsley@arm.com storeBuffer.minorTrace(); 154610259SAndrew.Bardsley@arm.com} 154710259SAndrew.Bardsley@arm.com 154810259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::StoreBuffer(std::string name_, LSQ &lsq_, 154910259SAndrew.Bardsley@arm.com unsigned int store_buffer_size, 155010259SAndrew.Bardsley@arm.com unsigned int store_limit_per_cycle) : 155110259SAndrew.Bardsley@arm.com Named(name_), lsq(lsq_), 155210259SAndrew.Bardsley@arm.com numSlots(store_buffer_size), 155310259SAndrew.Bardsley@arm.com storeLimitPerCycle(store_limit_per_cycle), 155410259SAndrew.Bardsley@arm.com slots(), 155510259SAndrew.Bardsley@arm.com numUnissuedAccesses(0) 155610259SAndrew.Bardsley@arm.com{ 155710259SAndrew.Bardsley@arm.com} 155810259SAndrew.Bardsley@arm.com 155910259SAndrew.Bardsley@arm.comPacketPtr 156010259SAndrew.Bardsley@arm.commakePacketForRequest(Request &request, bool isLoad, 156110259SAndrew.Bardsley@arm.com Packet::SenderState *sender_state, PacketDataPtr data) 156210259SAndrew.Bardsley@arm.com{ 156310739Ssteve.reinhardt@amd.com PacketPtr ret = isLoad ? Packet::createRead(&request) 156410739Ssteve.reinhardt@amd.com : Packet::createWrite(&request); 156510259SAndrew.Bardsley@arm.com 156610259SAndrew.Bardsley@arm.com if (sender_state) 156710259SAndrew.Bardsley@arm.com ret->pushSenderState(sender_state); 156810259SAndrew.Bardsley@arm.com 156912355Snikos.nikoleris@arm.com if (isLoad) { 157010259SAndrew.Bardsley@arm.com ret->allocate(); 157112355Snikos.nikoleris@arm.com } else if (!request.isCacheMaintenance()) { 157212355Snikos.nikoleris@arm.com // CMOs are treated as stores but they don't have data. All 157312355Snikos.nikoleris@arm.com // stores otherwise need to allocate for data. 157410566Sandreas.hansson@arm.com ret->dataDynamic(data); 157512355Snikos.nikoleris@arm.com } 157610259SAndrew.Bardsley@arm.com 157710259SAndrew.Bardsley@arm.com return ret; 157810259SAndrew.Bardsley@arm.com} 157910259SAndrew.Bardsley@arm.com 158010259SAndrew.Bardsley@arm.comvoid 158110259SAndrew.Bardsley@arm.comLSQ::issuedMemBarrierInst(MinorDynInstPtr inst) 158210259SAndrew.Bardsley@arm.com{ 158310259SAndrew.Bardsley@arm.com assert(inst->isInst() && inst->staticInst->isMemBarrier()); 158411567Smitch.hayenga@arm.com assert(inst->id.execSeqNum > lastMemBarrier[inst->id.threadId]); 158510259SAndrew.Bardsley@arm.com 158610259SAndrew.Bardsley@arm.com /* Remember the barrier. We only have a notion of one 158710259SAndrew.Bardsley@arm.com * barrier so this may result in some mem refs being 158810259SAndrew.Bardsley@arm.com * delayed if they are between barriers */ 158911567Smitch.hayenga@arm.com lastMemBarrier[inst->id.threadId] = inst->id.execSeqNum; 159010259SAndrew.Bardsley@arm.com} 159110259SAndrew.Bardsley@arm.com 159210259SAndrew.Bardsley@arm.comvoid 159310259SAndrew.Bardsley@arm.comLSQ::LSQRequest::makePacket() 159410259SAndrew.Bardsley@arm.com{ 159510259SAndrew.Bardsley@arm.com /* Make the function idempotent */ 159610259SAndrew.Bardsley@arm.com if (packet) 159710259SAndrew.Bardsley@arm.com return; 159810259SAndrew.Bardsley@arm.com 159911056Sandreas.hansson@arm.com // if the translation faulted, do not create a packet 160011056Sandreas.hansson@arm.com if (fault != NoFault) { 160111056Sandreas.hansson@arm.com assert(packet == NULL); 160211056Sandreas.hansson@arm.com return; 160311056Sandreas.hansson@arm.com } 160411056Sandreas.hansson@arm.com 160510259SAndrew.Bardsley@arm.com packet = makePacketForRequest(request, isLoad, this, data); 160610259SAndrew.Bardsley@arm.com /* Null the ret data so we know not to deallocate it when the 160710259SAndrew.Bardsley@arm.com * ret is destroyed. The data now belongs to the ret and 160810259SAndrew.Bardsley@arm.com * the ret is responsible for its destruction */ 160910259SAndrew.Bardsley@arm.com data = NULL; 161010259SAndrew.Bardsley@arm.com} 161110259SAndrew.Bardsley@arm.com 161210259SAndrew.Bardsley@arm.comstd::ostream & 161310259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, LSQ::MemoryState state) 161410259SAndrew.Bardsley@arm.com{ 161510259SAndrew.Bardsley@arm.com switch (state) { 161610259SAndrew.Bardsley@arm.com case LSQ::MemoryRunning: 161710259SAndrew.Bardsley@arm.com os << "MemoryRunning"; 161810259SAndrew.Bardsley@arm.com break; 161910259SAndrew.Bardsley@arm.com case LSQ::MemoryNeedsRetry: 162010259SAndrew.Bardsley@arm.com os << "MemoryNeedsRetry"; 162110259SAndrew.Bardsley@arm.com break; 162210259SAndrew.Bardsley@arm.com default: 162310259SAndrew.Bardsley@arm.com os << "MemoryState-" << static_cast<int>(state); 162410259SAndrew.Bardsley@arm.com break; 162510259SAndrew.Bardsley@arm.com } 162610259SAndrew.Bardsley@arm.com return os; 162710259SAndrew.Bardsley@arm.com} 162810259SAndrew.Bardsley@arm.com 162910259SAndrew.Bardsley@arm.comvoid 163010259SAndrew.Bardsley@arm.comLSQ::recvTimingSnoopReq(PacketPtr pkt) 163110259SAndrew.Bardsley@arm.com{ 163210259SAndrew.Bardsley@arm.com /* LLSC operations in Minor can't be speculative and are executed from 163310259SAndrew.Bardsley@arm.com * the head of the requests queue. We shouldn't need to do more than 163410259SAndrew.Bardsley@arm.com * this action on snoops. */ 163511567Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 163611567Smitch.hayenga@arm.com if (cpu.getCpuAddrMonitor(tid)->doMonitor(pkt)) { 163711567Smitch.hayenga@arm.com cpu.wakeup(tid); 163811567Smitch.hayenga@arm.com } 163911567Smitch.hayenga@arm.com } 164010259SAndrew.Bardsley@arm.com 164111356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 164211567Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 164311567Smitch.hayenga@arm.com TheISA::handleLockedSnoop(cpu.getContext(tid), pkt, 164411567Smitch.hayenga@arm.com cacheBlockMask); 164511567Smitch.hayenga@arm.com } 164611567Smitch.hayenga@arm.com } 164711567Smitch.hayenga@arm.com} 164811567Smitch.hayenga@arm.com 164911567Smitch.hayenga@arm.comvoid 165011567Smitch.hayenga@arm.comLSQ::threadSnoop(LSQRequestPtr request) 165111567Smitch.hayenga@arm.com{ 165211567Smitch.hayenga@arm.com /* LLSC operations in Minor can't be speculative and are executed from 165311567Smitch.hayenga@arm.com * the head of the requests queue. We shouldn't need to do more than 165411567Smitch.hayenga@arm.com * this action on snoops. */ 165511567Smitch.hayenga@arm.com ThreadID req_tid = request->inst->id.threadId; 165611567Smitch.hayenga@arm.com PacketPtr pkt = request->packet; 165711567Smitch.hayenga@arm.com 165811567Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 165911567Smitch.hayenga@arm.com if (tid != req_tid) { 166011567Smitch.hayenga@arm.com if (cpu.getCpuAddrMonitor(tid)->doMonitor(pkt)) { 166111567Smitch.hayenga@arm.com cpu.wakeup(tid); 166211567Smitch.hayenga@arm.com } 166311567Smitch.hayenga@arm.com 166411567Smitch.hayenga@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 166511567Smitch.hayenga@arm.com TheISA::handleLockedSnoop(cpu.getContext(tid), pkt, 166611567Smitch.hayenga@arm.com cacheBlockMask); 166711567Smitch.hayenga@arm.com } 166811567Smitch.hayenga@arm.com } 166911356Skrinat01@arm.com } 167010259SAndrew.Bardsley@arm.com} 167110259SAndrew.Bardsley@arm.com 167210259SAndrew.Bardsley@arm.com} 1673