lsq.cc revision 11435
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2013-2014 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1510259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1610259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 1710259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 1810259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1910259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2010259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2110259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2210259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2310259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2410259SAndrew.Bardsley@arm.com * 2510259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610259SAndrew.Bardsley@arm.com * 3710259SAndrew.Bardsley@arm.com * Authors: Andrew Bardsley 3810259SAndrew.Bardsley@arm.com */ 3910259SAndrew.Bardsley@arm.com 4010259SAndrew.Bardsley@arm.com#include <iomanip> 4110259SAndrew.Bardsley@arm.com#include <sstream> 4210259SAndrew.Bardsley@arm.com 4310259SAndrew.Bardsley@arm.com#include "arch/locked_mem.hh" 4410259SAndrew.Bardsley@arm.com#include "arch/mmapped_ipr.hh" 4510259SAndrew.Bardsley@arm.com#include "cpu/minor/cpu.hh" 4610259SAndrew.Bardsley@arm.com#include "cpu/minor/exec_context.hh" 4710259SAndrew.Bardsley@arm.com#include "cpu/minor/execute.hh" 4810259SAndrew.Bardsley@arm.com#include "cpu/minor/lsq.hh" 4910259SAndrew.Bardsley@arm.com#include "cpu/minor/pipeline.hh" 5010259SAndrew.Bardsley@arm.com#include "debug/Activity.hh" 5110259SAndrew.Bardsley@arm.com#include "debug/MinorMem.hh" 5210259SAndrew.Bardsley@arm.com 5310259SAndrew.Bardsley@arm.comnamespace Minor 5410259SAndrew.Bardsley@arm.com{ 5510259SAndrew.Bardsley@arm.com 5610259SAndrew.Bardsley@arm.com/** Returns the offset of addr into an aligned a block of size block_size */ 5710259SAndrew.Bardsley@arm.comstatic Addr 5810259SAndrew.Bardsley@arm.comaddrBlockOffset(Addr addr, unsigned int block_size) 5910259SAndrew.Bardsley@arm.com{ 6010259SAndrew.Bardsley@arm.com return addr & (block_size - 1); 6110259SAndrew.Bardsley@arm.com} 6210259SAndrew.Bardsley@arm.com 6310259SAndrew.Bardsley@arm.com/** Returns true if the given [addr .. addr+size-1] transfer needs to be 6410259SAndrew.Bardsley@arm.com * fragmented across a block size of block_size */ 6510259SAndrew.Bardsley@arm.comstatic bool 6610259SAndrew.Bardsley@arm.comtransferNeedsBurst(Addr addr, unsigned int size, unsigned int block_size) 6710259SAndrew.Bardsley@arm.com{ 6810259SAndrew.Bardsley@arm.com return (addrBlockOffset(addr, block_size) + size) > block_size; 6910259SAndrew.Bardsley@arm.com} 7010259SAndrew.Bardsley@arm.com 7110259SAndrew.Bardsley@arm.comLSQ::LSQRequest::LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_, 7210259SAndrew.Bardsley@arm.com PacketDataPtr data_, uint64_t *res_) : 7310259SAndrew.Bardsley@arm.com SenderState(), 7410259SAndrew.Bardsley@arm.com port(port_), 7510259SAndrew.Bardsley@arm.com inst(inst_), 7610259SAndrew.Bardsley@arm.com isLoad(isLoad_), 7710259SAndrew.Bardsley@arm.com data(data_), 7810259SAndrew.Bardsley@arm.com packet(NULL), 7910259SAndrew.Bardsley@arm.com request(), 8010259SAndrew.Bardsley@arm.com fault(NoFault), 8110259SAndrew.Bardsley@arm.com res(res_), 8210259SAndrew.Bardsley@arm.com skipped(false), 8310259SAndrew.Bardsley@arm.com issuedToMemory(false), 8410259SAndrew.Bardsley@arm.com state(NotIssued) 8510259SAndrew.Bardsley@arm.com{ } 8610259SAndrew.Bardsley@arm.com 8710259SAndrew.Bardsley@arm.comLSQ::AddrRangeCoverage 8810259SAndrew.Bardsley@arm.comLSQ::LSQRequest::containsAddrRangeOf( 8910259SAndrew.Bardsley@arm.com Addr req1_addr, unsigned int req1_size, 9010259SAndrew.Bardsley@arm.com Addr req2_addr, unsigned int req2_size) 9110259SAndrew.Bardsley@arm.com{ 9210259SAndrew.Bardsley@arm.com /* 'end' here means the address of the byte just past the request 9310259SAndrew.Bardsley@arm.com * blocks */ 9410259SAndrew.Bardsley@arm.com Addr req2_end_addr = req2_addr + req2_size; 9510259SAndrew.Bardsley@arm.com Addr req1_end_addr = req1_addr + req1_size; 9610259SAndrew.Bardsley@arm.com 9710259SAndrew.Bardsley@arm.com AddrRangeCoverage ret; 9810259SAndrew.Bardsley@arm.com 9910259SAndrew.Bardsley@arm.com if (req1_addr > req2_end_addr || req1_end_addr < req2_addr) 10010259SAndrew.Bardsley@arm.com ret = NoAddrRangeCoverage; 10110259SAndrew.Bardsley@arm.com else if (req1_addr <= req2_addr && req1_end_addr >= req2_end_addr) 10210259SAndrew.Bardsley@arm.com ret = FullAddrRangeCoverage; 10310259SAndrew.Bardsley@arm.com else 10410259SAndrew.Bardsley@arm.com ret = PartialAddrRangeCoverage; 10510259SAndrew.Bardsley@arm.com 10610259SAndrew.Bardsley@arm.com return ret; 10710259SAndrew.Bardsley@arm.com} 10810259SAndrew.Bardsley@arm.com 10910259SAndrew.Bardsley@arm.comLSQ::AddrRangeCoverage 11010259SAndrew.Bardsley@arm.comLSQ::LSQRequest::containsAddrRangeOf(LSQRequestPtr other_request) 11110259SAndrew.Bardsley@arm.com{ 11210259SAndrew.Bardsley@arm.com return containsAddrRangeOf(request.getPaddr(), request.getSize(), 11310259SAndrew.Bardsley@arm.com other_request->request.getPaddr(), other_request->request.getSize()); 11410259SAndrew.Bardsley@arm.com} 11510259SAndrew.Bardsley@arm.com 11610259SAndrew.Bardsley@arm.combool 11710259SAndrew.Bardsley@arm.comLSQ::LSQRequest::isBarrier() 11810259SAndrew.Bardsley@arm.com{ 11910259SAndrew.Bardsley@arm.com return inst->isInst() && inst->staticInst->isMemBarrier(); 12010259SAndrew.Bardsley@arm.com} 12110259SAndrew.Bardsley@arm.com 12210259SAndrew.Bardsley@arm.combool 12310259SAndrew.Bardsley@arm.comLSQ::LSQRequest::needsToBeSentToStoreBuffer() 12410259SAndrew.Bardsley@arm.com{ 12510259SAndrew.Bardsley@arm.com return state == StoreToStoreBuffer; 12610259SAndrew.Bardsley@arm.com} 12710259SAndrew.Bardsley@arm.com 12810259SAndrew.Bardsley@arm.comvoid 12910259SAndrew.Bardsley@arm.comLSQ::LSQRequest::setState(LSQRequestState new_state) 13010259SAndrew.Bardsley@arm.com{ 13110259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Setting state from %d to %d for request:" 13210259SAndrew.Bardsley@arm.com " %s\n", state, new_state, *inst); 13310259SAndrew.Bardsley@arm.com state = new_state; 13410259SAndrew.Bardsley@arm.com} 13510259SAndrew.Bardsley@arm.com 13610259SAndrew.Bardsley@arm.combool 13710259SAndrew.Bardsley@arm.comLSQ::LSQRequest::isComplete() const 13810259SAndrew.Bardsley@arm.com{ 13910259SAndrew.Bardsley@arm.com /* @todo, There is currently only one 'completed' state. This 14010259SAndrew.Bardsley@arm.com * may not be a good choice */ 14110259SAndrew.Bardsley@arm.com return state == Complete; 14210259SAndrew.Bardsley@arm.com} 14310259SAndrew.Bardsley@arm.com 14410259SAndrew.Bardsley@arm.comvoid 14510259SAndrew.Bardsley@arm.comLSQ::LSQRequest::reportData(std::ostream &os) const 14610259SAndrew.Bardsley@arm.com{ 14710259SAndrew.Bardsley@arm.com os << (isLoad ? 'R' : 'W') << ';'; 14810259SAndrew.Bardsley@arm.com inst->reportData(os); 14910259SAndrew.Bardsley@arm.com os << ';' << state; 15010259SAndrew.Bardsley@arm.com} 15110259SAndrew.Bardsley@arm.com 15210259SAndrew.Bardsley@arm.comstd::ostream & 15310259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, LSQ::AddrRangeCoverage coverage) 15410259SAndrew.Bardsley@arm.com{ 15510259SAndrew.Bardsley@arm.com switch (coverage) { 15610259SAndrew.Bardsley@arm.com case LSQ::PartialAddrRangeCoverage: 15710259SAndrew.Bardsley@arm.com os << "PartialAddrRangeCoverage"; 15810259SAndrew.Bardsley@arm.com break; 15910259SAndrew.Bardsley@arm.com case LSQ::FullAddrRangeCoverage: 16010259SAndrew.Bardsley@arm.com os << "FullAddrRangeCoverage"; 16110259SAndrew.Bardsley@arm.com break; 16210259SAndrew.Bardsley@arm.com case LSQ::NoAddrRangeCoverage: 16310259SAndrew.Bardsley@arm.com os << "NoAddrRangeCoverage"; 16410259SAndrew.Bardsley@arm.com break; 16510259SAndrew.Bardsley@arm.com default: 16610259SAndrew.Bardsley@arm.com os << "AddrRangeCoverage-" << static_cast<int>(coverage); 16710259SAndrew.Bardsley@arm.com break; 16810259SAndrew.Bardsley@arm.com } 16910259SAndrew.Bardsley@arm.com return os; 17010259SAndrew.Bardsley@arm.com} 17110259SAndrew.Bardsley@arm.com 17210259SAndrew.Bardsley@arm.comstd::ostream & 17310259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, LSQ::LSQRequest::LSQRequestState state) 17410259SAndrew.Bardsley@arm.com{ 17510259SAndrew.Bardsley@arm.com switch (state) { 17610259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::NotIssued: 17710259SAndrew.Bardsley@arm.com os << "NotIssued"; 17810259SAndrew.Bardsley@arm.com break; 17910259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::InTranslation: 18010259SAndrew.Bardsley@arm.com os << "InTranslation"; 18110259SAndrew.Bardsley@arm.com break; 18210259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::Translated: 18310259SAndrew.Bardsley@arm.com os << "Translated"; 18410259SAndrew.Bardsley@arm.com break; 18510259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::Failed: 18610259SAndrew.Bardsley@arm.com os << "Failed"; 18710259SAndrew.Bardsley@arm.com break; 18810259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::RequestIssuing: 18910259SAndrew.Bardsley@arm.com os << "RequestIssuing"; 19010259SAndrew.Bardsley@arm.com break; 19110259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreToStoreBuffer: 19210259SAndrew.Bardsley@arm.com os << "StoreToStoreBuffer"; 19310259SAndrew.Bardsley@arm.com break; 19410259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreInStoreBuffer: 19510259SAndrew.Bardsley@arm.com os << "StoreInStoreBuffer"; 19610259SAndrew.Bardsley@arm.com break; 19710259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreBufferIssuing: 19810259SAndrew.Bardsley@arm.com os << "StoreBufferIssuing"; 19910259SAndrew.Bardsley@arm.com break; 20010259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::RequestNeedsRetry: 20110259SAndrew.Bardsley@arm.com os << "RequestNeedsRetry"; 20210259SAndrew.Bardsley@arm.com break; 20310259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::StoreBufferNeedsRetry: 20410259SAndrew.Bardsley@arm.com os << "StoreBufferNeedsRetry"; 20510259SAndrew.Bardsley@arm.com break; 20610259SAndrew.Bardsley@arm.com case LSQ::LSQRequest::Complete: 20710259SAndrew.Bardsley@arm.com os << "Complete"; 20810259SAndrew.Bardsley@arm.com break; 20910259SAndrew.Bardsley@arm.com default: 21010259SAndrew.Bardsley@arm.com os << "LSQRequestState-" << static_cast<int>(state); 21110259SAndrew.Bardsley@arm.com break; 21210259SAndrew.Bardsley@arm.com } 21310259SAndrew.Bardsley@arm.com return os; 21410259SAndrew.Bardsley@arm.com} 21510259SAndrew.Bardsley@arm.com 21610259SAndrew.Bardsley@arm.comvoid 21710259SAndrew.Bardsley@arm.comLSQ::clearMemBarrier(MinorDynInstPtr inst) 21810259SAndrew.Bardsley@arm.com{ 21910259SAndrew.Bardsley@arm.com bool is_last_barrier = inst->id.execSeqNum >= lastMemBarrier; 22010259SAndrew.Bardsley@arm.com 22110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Moving %s barrier out of store buffer inst: %s\n", 22210259SAndrew.Bardsley@arm.com (is_last_barrier ? "last" : "a"), *inst); 22310259SAndrew.Bardsley@arm.com 22410259SAndrew.Bardsley@arm.com if (is_last_barrier) 22510259SAndrew.Bardsley@arm.com lastMemBarrier = 0; 22610259SAndrew.Bardsley@arm.com} 22710259SAndrew.Bardsley@arm.com 22810259SAndrew.Bardsley@arm.comvoid 22910379Sandreas.hansson@arm.comLSQ::SingleDataRequest::finish(const Fault &fault_, RequestPtr request_, 23010379Sandreas.hansson@arm.com ThreadContext *tc, BaseTLB::Mode mode) 23110259SAndrew.Bardsley@arm.com{ 23210259SAndrew.Bardsley@arm.com fault = fault_; 23310259SAndrew.Bardsley@arm.com 23410259SAndrew.Bardsley@arm.com port.numAccessesInDTLB--; 23510259SAndrew.Bardsley@arm.com 23610259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Received translation response for" 23710259SAndrew.Bardsley@arm.com " request: %s\n", *inst); 23810259SAndrew.Bardsley@arm.com 23910259SAndrew.Bardsley@arm.com makePacket(); 24010259SAndrew.Bardsley@arm.com 24110259SAndrew.Bardsley@arm.com setState(Translated); 24210259SAndrew.Bardsley@arm.com port.tryToSendToTransfers(this); 24310259SAndrew.Bardsley@arm.com 24410259SAndrew.Bardsley@arm.com /* Let's try and wake up the processor for the next cycle */ 24510259SAndrew.Bardsley@arm.com port.cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 24610259SAndrew.Bardsley@arm.com} 24710259SAndrew.Bardsley@arm.com 24810259SAndrew.Bardsley@arm.comvoid 24910259SAndrew.Bardsley@arm.comLSQ::SingleDataRequest::startAddrTranslation() 25010259SAndrew.Bardsley@arm.com{ 25110259SAndrew.Bardsley@arm.com ThreadContext *thread = port.cpu.getContext( 25210259SAndrew.Bardsley@arm.com inst->id.threadId); 25310259SAndrew.Bardsley@arm.com 25410259SAndrew.Bardsley@arm.com port.numAccessesInDTLB++; 25510259SAndrew.Bardsley@arm.com 25610259SAndrew.Bardsley@arm.com setState(LSQ::LSQRequest::InTranslation); 25710259SAndrew.Bardsley@arm.com 25810259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Submitting DTLB request\n"); 25910259SAndrew.Bardsley@arm.com /* Submit the translation request. The response will come through 26010259SAndrew.Bardsley@arm.com * finish/markDelayed on the LSQRequest as it bears the Translation 26110259SAndrew.Bardsley@arm.com * interface */ 26210259SAndrew.Bardsley@arm.com thread->getDTBPtr()->translateTiming( 26310259SAndrew.Bardsley@arm.com &request, thread, this, (isLoad ? BaseTLB::Read : BaseTLB::Write)); 26410259SAndrew.Bardsley@arm.com} 26510259SAndrew.Bardsley@arm.com 26610259SAndrew.Bardsley@arm.comvoid 26710259SAndrew.Bardsley@arm.comLSQ::SingleDataRequest::retireResponse(PacketPtr packet_) 26810259SAndrew.Bardsley@arm.com{ 26910259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Retiring packet\n"); 27010259SAndrew.Bardsley@arm.com packet = packet_; 27110259SAndrew.Bardsley@arm.com packetInFlight = false; 27210259SAndrew.Bardsley@arm.com setState(Complete); 27310259SAndrew.Bardsley@arm.com} 27410259SAndrew.Bardsley@arm.com 27510259SAndrew.Bardsley@arm.comvoid 27610379Sandreas.hansson@arm.comLSQ::SplitDataRequest::finish(const Fault &fault_, RequestPtr request_, 27710379Sandreas.hansson@arm.com ThreadContext *tc, BaseTLB::Mode mode) 27810259SAndrew.Bardsley@arm.com{ 27910259SAndrew.Bardsley@arm.com fault = fault_; 28010259SAndrew.Bardsley@arm.com 28110259SAndrew.Bardsley@arm.com port.numAccessesInDTLB--; 28210259SAndrew.Bardsley@arm.com 28310259SAndrew.Bardsley@arm.com unsigned int M5_VAR_USED expected_fragment_index = 28410259SAndrew.Bardsley@arm.com numTranslatedFragments; 28510259SAndrew.Bardsley@arm.com 28610259SAndrew.Bardsley@arm.com numInTranslationFragments--; 28710259SAndrew.Bardsley@arm.com numTranslatedFragments++; 28810259SAndrew.Bardsley@arm.com 28910259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Received translation response for fragment" 29010259SAndrew.Bardsley@arm.com " %d of request: %s\n", expected_fragment_index, *inst); 29110259SAndrew.Bardsley@arm.com 29210259SAndrew.Bardsley@arm.com assert(request_ == fragmentRequests[expected_fragment_index]); 29310259SAndrew.Bardsley@arm.com 29410259SAndrew.Bardsley@arm.com /* Wake up next cycle to get things going again in case the 29510259SAndrew.Bardsley@arm.com * tryToSendToTransfers does take */ 29610259SAndrew.Bardsley@arm.com port.cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 29710259SAndrew.Bardsley@arm.com 29810259SAndrew.Bardsley@arm.com if (fault != NoFault) { 29910259SAndrew.Bardsley@arm.com /* tryToSendToTransfers will handle the fault */ 30010259SAndrew.Bardsley@arm.com 30110259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Faulting translation for fragment:" 30210259SAndrew.Bardsley@arm.com " %d of request: %s\n", 30310259SAndrew.Bardsley@arm.com expected_fragment_index, *inst); 30410259SAndrew.Bardsley@arm.com 30510259SAndrew.Bardsley@arm.com setState(Translated); 30610259SAndrew.Bardsley@arm.com port.tryToSendToTransfers(this); 30710259SAndrew.Bardsley@arm.com } else if (numTranslatedFragments == numFragments) { 30810259SAndrew.Bardsley@arm.com makeFragmentPackets(); 30910259SAndrew.Bardsley@arm.com 31010259SAndrew.Bardsley@arm.com setState(Translated); 31110259SAndrew.Bardsley@arm.com port.tryToSendToTransfers(this); 31210259SAndrew.Bardsley@arm.com } else { 31310259SAndrew.Bardsley@arm.com /* Avoid calling translateTiming from within ::finish */ 31410259SAndrew.Bardsley@arm.com assert(!translationEvent.scheduled()); 31510259SAndrew.Bardsley@arm.com port.cpu.schedule(translationEvent, curTick()); 31610259SAndrew.Bardsley@arm.com } 31710259SAndrew.Bardsley@arm.com} 31810259SAndrew.Bardsley@arm.com 31910259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_, 32010259SAndrew.Bardsley@arm.com bool isLoad_, PacketDataPtr data_, uint64_t *res_) : 32110259SAndrew.Bardsley@arm.com LSQRequest(port_, inst_, isLoad_, data_, res_), 32210259SAndrew.Bardsley@arm.com translationEvent(*this), 32310259SAndrew.Bardsley@arm.com numFragments(0), 32410259SAndrew.Bardsley@arm.com numInTranslationFragments(0), 32510259SAndrew.Bardsley@arm.com numTranslatedFragments(0), 32610259SAndrew.Bardsley@arm.com numIssuedFragments(0), 32710259SAndrew.Bardsley@arm.com numRetiredFragments(0), 32810259SAndrew.Bardsley@arm.com fragmentRequests(), 32910259SAndrew.Bardsley@arm.com fragmentPackets() 33010259SAndrew.Bardsley@arm.com{ 33110259SAndrew.Bardsley@arm.com /* Don't know how many elements are needed until the request is 33210259SAndrew.Bardsley@arm.com * populated by the caller. */ 33310259SAndrew.Bardsley@arm.com} 33410259SAndrew.Bardsley@arm.com 33510259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::~SplitDataRequest() 33610259SAndrew.Bardsley@arm.com{ 33710259SAndrew.Bardsley@arm.com for (auto i = fragmentRequests.begin(); 33810259SAndrew.Bardsley@arm.com i != fragmentRequests.end(); i++) 33910259SAndrew.Bardsley@arm.com { 34010259SAndrew.Bardsley@arm.com delete *i; 34110259SAndrew.Bardsley@arm.com } 34210259SAndrew.Bardsley@arm.com 34310259SAndrew.Bardsley@arm.com for (auto i = fragmentPackets.begin(); 34410259SAndrew.Bardsley@arm.com i != fragmentPackets.end(); i++) 34510259SAndrew.Bardsley@arm.com { 34610259SAndrew.Bardsley@arm.com delete *i; 34710259SAndrew.Bardsley@arm.com } 34810259SAndrew.Bardsley@arm.com} 34910259SAndrew.Bardsley@arm.com 35010259SAndrew.Bardsley@arm.comvoid 35110259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::makeFragmentRequests() 35210259SAndrew.Bardsley@arm.com{ 35310259SAndrew.Bardsley@arm.com Addr base_addr = request.getVaddr(); 35410259SAndrew.Bardsley@arm.com unsigned int whole_size = request.getSize(); 35510259SAndrew.Bardsley@arm.com unsigned int line_width = port.lineWidth; 35610259SAndrew.Bardsley@arm.com 35710259SAndrew.Bardsley@arm.com unsigned int fragment_size; 35810259SAndrew.Bardsley@arm.com Addr fragment_addr; 35910259SAndrew.Bardsley@arm.com 36010259SAndrew.Bardsley@arm.com /* Assume that this transfer is across potentially many block snap 36110259SAndrew.Bardsley@arm.com * boundaries: 36210259SAndrew.Bardsley@arm.com * 36310259SAndrew.Bardsley@arm.com * | _|________|________|________|___ | 36410259SAndrew.Bardsley@arm.com * | |0| 1 | 2 | 3 | 4 | | 36510259SAndrew.Bardsley@arm.com * | |_|________|________|________|___| | 36610259SAndrew.Bardsley@arm.com * | | | | | | 36710259SAndrew.Bardsley@arm.com * 36810259SAndrew.Bardsley@arm.com * The first transfer (0) can be up to lineWidth in size. 36910259SAndrew.Bardsley@arm.com * All the middle transfers (1-3) are lineWidth in size 37010259SAndrew.Bardsley@arm.com * The last transfer (4) can be from zero to lineWidth - 1 in size 37110259SAndrew.Bardsley@arm.com */ 37210259SAndrew.Bardsley@arm.com unsigned int first_fragment_offset = 37310259SAndrew.Bardsley@arm.com addrBlockOffset(base_addr, line_width); 37410259SAndrew.Bardsley@arm.com unsigned int last_fragment_size = 37510259SAndrew.Bardsley@arm.com addrBlockOffset(base_addr + whole_size, line_width); 37610259SAndrew.Bardsley@arm.com unsigned int first_fragment_size = 37710259SAndrew.Bardsley@arm.com line_width - first_fragment_offset; 37810259SAndrew.Bardsley@arm.com 37910259SAndrew.Bardsley@arm.com unsigned int middle_fragments_total_size = 38010259SAndrew.Bardsley@arm.com whole_size - (first_fragment_size + last_fragment_size); 38110259SAndrew.Bardsley@arm.com 38210259SAndrew.Bardsley@arm.com assert(addrBlockOffset(middle_fragments_total_size, line_width) == 0); 38310259SAndrew.Bardsley@arm.com 38410259SAndrew.Bardsley@arm.com unsigned int middle_fragment_count = 38510259SAndrew.Bardsley@arm.com middle_fragments_total_size / line_width; 38610259SAndrew.Bardsley@arm.com 38710259SAndrew.Bardsley@arm.com numFragments = 1 /* first */ + middle_fragment_count + 38810259SAndrew.Bardsley@arm.com (last_fragment_size == 0 ? 0 : 1); 38910259SAndrew.Bardsley@arm.com 39010259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Dividing transfer into %d fragmentRequests." 39110259SAndrew.Bardsley@arm.com " First fragment size: %d Last fragment size: %d\n", 39210259SAndrew.Bardsley@arm.com numFragments, first_fragment_size, 39310259SAndrew.Bardsley@arm.com (last_fragment_size == 0 ? line_width : last_fragment_size)); 39410259SAndrew.Bardsley@arm.com 39510259SAndrew.Bardsley@arm.com assert(((middle_fragment_count * line_width) + 39610259SAndrew.Bardsley@arm.com first_fragment_size + last_fragment_size) == whole_size); 39710259SAndrew.Bardsley@arm.com 39810259SAndrew.Bardsley@arm.com fragment_addr = base_addr; 39910259SAndrew.Bardsley@arm.com fragment_size = first_fragment_size; 40010259SAndrew.Bardsley@arm.com 40110259SAndrew.Bardsley@arm.com /* Just past the last address in the request */ 40210259SAndrew.Bardsley@arm.com Addr end_addr = base_addr + whole_size; 40310259SAndrew.Bardsley@arm.com 40410259SAndrew.Bardsley@arm.com for (unsigned int fragment_index = 0; fragment_index < numFragments; 40510259SAndrew.Bardsley@arm.com fragment_index++) 40610259SAndrew.Bardsley@arm.com { 40710259SAndrew.Bardsley@arm.com bool M5_VAR_USED is_last_fragment = false; 40810259SAndrew.Bardsley@arm.com 40910259SAndrew.Bardsley@arm.com if (fragment_addr == base_addr) { 41010259SAndrew.Bardsley@arm.com /* First fragment */ 41110259SAndrew.Bardsley@arm.com fragment_size = first_fragment_size; 41210259SAndrew.Bardsley@arm.com } else { 41310259SAndrew.Bardsley@arm.com if ((fragment_addr + line_width) > end_addr) { 41410259SAndrew.Bardsley@arm.com /* Adjust size of last fragment */ 41510259SAndrew.Bardsley@arm.com fragment_size = end_addr - fragment_addr; 41610259SAndrew.Bardsley@arm.com is_last_fragment = true; 41710259SAndrew.Bardsley@arm.com } else { 41810259SAndrew.Bardsley@arm.com /* Middle fragments */ 41910259SAndrew.Bardsley@arm.com fragment_size = line_width; 42010259SAndrew.Bardsley@arm.com } 42110259SAndrew.Bardsley@arm.com } 42210259SAndrew.Bardsley@arm.com 42310259SAndrew.Bardsley@arm.com Request *fragment = new Request(); 42410259SAndrew.Bardsley@arm.com 42511435Smitch.hayenga@arm.com fragment->setContext(request.contextId()); 42610259SAndrew.Bardsley@arm.com fragment->setVirt(0 /* asid */, 42710259SAndrew.Bardsley@arm.com fragment_addr, fragment_size, request.getFlags(), 42810259SAndrew.Bardsley@arm.com request.masterId(), 42910259SAndrew.Bardsley@arm.com request.getPC()); 43010259SAndrew.Bardsley@arm.com 43110259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Generating fragment addr: 0x%x size: %d" 43210259SAndrew.Bardsley@arm.com " (whole request addr: 0x%x size: %d) %s\n", 43310259SAndrew.Bardsley@arm.com fragment_addr, fragment_size, base_addr, whole_size, 43410259SAndrew.Bardsley@arm.com (is_last_fragment ? "last fragment" : "")); 43510259SAndrew.Bardsley@arm.com 43610259SAndrew.Bardsley@arm.com fragment_addr += fragment_size; 43710259SAndrew.Bardsley@arm.com 43810259SAndrew.Bardsley@arm.com fragmentRequests.push_back(fragment); 43910259SAndrew.Bardsley@arm.com } 44010259SAndrew.Bardsley@arm.com} 44110259SAndrew.Bardsley@arm.com 44210259SAndrew.Bardsley@arm.comvoid 44310259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::makeFragmentPackets() 44410259SAndrew.Bardsley@arm.com{ 44510259SAndrew.Bardsley@arm.com Addr base_addr = request.getVaddr(); 44610259SAndrew.Bardsley@arm.com 44710259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Making packets for request: %s\n", *inst); 44810259SAndrew.Bardsley@arm.com 44910259SAndrew.Bardsley@arm.com for (unsigned int fragment_index = 0; fragment_index < numFragments; 45010259SAndrew.Bardsley@arm.com fragment_index++) 45110259SAndrew.Bardsley@arm.com { 45210259SAndrew.Bardsley@arm.com Request *fragment = fragmentRequests[fragment_index]; 45310259SAndrew.Bardsley@arm.com 45410259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Making packet %d for request: %s" 45510259SAndrew.Bardsley@arm.com " (%d, 0x%x)\n", 45610259SAndrew.Bardsley@arm.com fragment_index, *inst, 45710259SAndrew.Bardsley@arm.com (fragment->hasPaddr() ? "has paddr" : "no paddr"), 45810259SAndrew.Bardsley@arm.com (fragment->hasPaddr() ? fragment->getPaddr() : 0)); 45910259SAndrew.Bardsley@arm.com 46010259SAndrew.Bardsley@arm.com Addr fragment_addr = fragment->getVaddr(); 46110259SAndrew.Bardsley@arm.com unsigned int fragment_size = fragment->getSize(); 46210259SAndrew.Bardsley@arm.com 46310259SAndrew.Bardsley@arm.com uint8_t *request_data = NULL; 46410259SAndrew.Bardsley@arm.com 46510259SAndrew.Bardsley@arm.com if (!isLoad) { 46610259SAndrew.Bardsley@arm.com /* Split data for Packets. Will become the property of the 46710259SAndrew.Bardsley@arm.com * outgoing Packets */ 46810259SAndrew.Bardsley@arm.com request_data = new uint8_t[fragment_size]; 46910259SAndrew.Bardsley@arm.com std::memcpy(request_data, data + (fragment_addr - base_addr), 47010259SAndrew.Bardsley@arm.com fragment_size); 47110259SAndrew.Bardsley@arm.com } 47210259SAndrew.Bardsley@arm.com 47310259SAndrew.Bardsley@arm.com assert(fragment->hasPaddr()); 47410259SAndrew.Bardsley@arm.com 47510259SAndrew.Bardsley@arm.com PacketPtr fragment_packet = 47610259SAndrew.Bardsley@arm.com makePacketForRequest(*fragment, isLoad, this, request_data); 47710259SAndrew.Bardsley@arm.com 47810259SAndrew.Bardsley@arm.com fragmentPackets.push_back(fragment_packet); 47910368SAndrew.Bardsley@arm.com /* Accumulate flags in parent request */ 48010368SAndrew.Bardsley@arm.com request.setFlags(fragment->getFlags()); 48110259SAndrew.Bardsley@arm.com } 48210259SAndrew.Bardsley@arm.com 48310259SAndrew.Bardsley@arm.com /* Might as well make the overall/response packet here */ 48410259SAndrew.Bardsley@arm.com /* Get the physical address for the whole request/packet from the first 48510259SAndrew.Bardsley@arm.com * fragment */ 48610259SAndrew.Bardsley@arm.com request.setPaddr(fragmentRequests[0]->getPaddr()); 48710259SAndrew.Bardsley@arm.com makePacket(); 48810259SAndrew.Bardsley@arm.com} 48910259SAndrew.Bardsley@arm.com 49010259SAndrew.Bardsley@arm.comvoid 49110259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::startAddrTranslation() 49210259SAndrew.Bardsley@arm.com{ 49310259SAndrew.Bardsley@arm.com setState(LSQ::LSQRequest::InTranslation); 49410259SAndrew.Bardsley@arm.com 49510259SAndrew.Bardsley@arm.com makeFragmentRequests(); 49610259SAndrew.Bardsley@arm.com 49710259SAndrew.Bardsley@arm.com numInTranslationFragments = 0; 49810259SAndrew.Bardsley@arm.com numTranslatedFragments = 0; 49910259SAndrew.Bardsley@arm.com 50010259SAndrew.Bardsley@arm.com /* @todo, just do these in sequence for now with 50110259SAndrew.Bardsley@arm.com * a loop of: 50210259SAndrew.Bardsley@arm.com * do { 50310259SAndrew.Bardsley@arm.com * sendNextFragmentToTranslation ; translateTiming ; finish 50410259SAndrew.Bardsley@arm.com * } while (numTranslatedFragments != numFragments); 50510259SAndrew.Bardsley@arm.com */ 50610259SAndrew.Bardsley@arm.com 50710259SAndrew.Bardsley@arm.com /* Do first translation */ 50810259SAndrew.Bardsley@arm.com sendNextFragmentToTranslation(); 50910259SAndrew.Bardsley@arm.com} 51010259SAndrew.Bardsley@arm.com 51110259SAndrew.Bardsley@arm.comPacketPtr 51210259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::getHeadPacket() 51310259SAndrew.Bardsley@arm.com{ 51410259SAndrew.Bardsley@arm.com assert(numIssuedFragments < numFragments); 51510259SAndrew.Bardsley@arm.com 51610259SAndrew.Bardsley@arm.com return fragmentPackets[numIssuedFragments]; 51710259SAndrew.Bardsley@arm.com} 51810259SAndrew.Bardsley@arm.com 51910259SAndrew.Bardsley@arm.comvoid 52010259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::stepToNextPacket() 52110259SAndrew.Bardsley@arm.com{ 52210259SAndrew.Bardsley@arm.com assert(numIssuedFragments < numFragments); 52310259SAndrew.Bardsley@arm.com 52410259SAndrew.Bardsley@arm.com numIssuedFragments++; 52510259SAndrew.Bardsley@arm.com} 52610259SAndrew.Bardsley@arm.com 52710259SAndrew.Bardsley@arm.comvoid 52810259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::retireResponse(PacketPtr response) 52910259SAndrew.Bardsley@arm.com{ 53010259SAndrew.Bardsley@arm.com assert(numRetiredFragments < numFragments); 53110259SAndrew.Bardsley@arm.com 53210259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Retiring fragment addr: 0x%x size: %d" 53310259SAndrew.Bardsley@arm.com " offset: 0x%x (retired fragment num: %d) %s\n", 53410259SAndrew.Bardsley@arm.com response->req->getVaddr(), response->req->getSize(), 53510259SAndrew.Bardsley@arm.com request.getVaddr() - response->req->getVaddr(), 53610259SAndrew.Bardsley@arm.com numRetiredFragments, 53710259SAndrew.Bardsley@arm.com (fault == NoFault ? "" : fault->name())); 53810259SAndrew.Bardsley@arm.com 53910259SAndrew.Bardsley@arm.com numRetiredFragments++; 54010259SAndrew.Bardsley@arm.com 54110259SAndrew.Bardsley@arm.com if (skipped) { 54210259SAndrew.Bardsley@arm.com /* Skip because we already knew the request had faulted or been 54310259SAndrew.Bardsley@arm.com * skipped */ 54410259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Skipping this fragment\n"); 54510259SAndrew.Bardsley@arm.com } else if (response->isError()) { 54610259SAndrew.Bardsley@arm.com /* Mark up the error and leave to execute to handle it */ 54710259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Fragment has an error, skipping\n"); 54810259SAndrew.Bardsley@arm.com setSkipped(); 54910259SAndrew.Bardsley@arm.com packet->copyError(response); 55010259SAndrew.Bardsley@arm.com } else { 55110259SAndrew.Bardsley@arm.com if (isLoad) { 55210259SAndrew.Bardsley@arm.com if (!data) { 55310259SAndrew.Bardsley@arm.com /* For a split transfer, a Packet must be constructed 55410259SAndrew.Bardsley@arm.com * to contain all returning data. This is that packet's 55510259SAndrew.Bardsley@arm.com * data */ 55610259SAndrew.Bardsley@arm.com data = new uint8_t[request.getSize()]; 55710259SAndrew.Bardsley@arm.com } 55810259SAndrew.Bardsley@arm.com 55910259SAndrew.Bardsley@arm.com /* Populate the portion of the overall response data represented 56010259SAndrew.Bardsley@arm.com * by the response fragment */ 56110259SAndrew.Bardsley@arm.com std::memcpy( 56210259SAndrew.Bardsley@arm.com data + (response->req->getVaddr() - request.getVaddr()), 56310563Sandreas.hansson@arm.com response->getConstPtr<uint8_t>(), 56410259SAndrew.Bardsley@arm.com response->req->getSize()); 56510259SAndrew.Bardsley@arm.com } 56610259SAndrew.Bardsley@arm.com } 56710259SAndrew.Bardsley@arm.com 56810259SAndrew.Bardsley@arm.com /* Complete early if we're skipping are no more in-flight accesses */ 56910259SAndrew.Bardsley@arm.com if (skipped && !hasPacketsInMemSystem()) { 57010259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Completed skipped burst\n"); 57110259SAndrew.Bardsley@arm.com setState(Complete); 57210259SAndrew.Bardsley@arm.com if (packet->needsResponse()) 57310259SAndrew.Bardsley@arm.com packet->makeResponse(); 57410259SAndrew.Bardsley@arm.com } 57510259SAndrew.Bardsley@arm.com 57610259SAndrew.Bardsley@arm.com if (numRetiredFragments == numFragments) 57710259SAndrew.Bardsley@arm.com setState(Complete); 57810259SAndrew.Bardsley@arm.com 57910259SAndrew.Bardsley@arm.com if (!skipped && isComplete()) { 58010259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Completed burst %d\n", packet != NULL); 58110259SAndrew.Bardsley@arm.com 58210259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Retired packet isRead: %d isWrite: %d" 58310259SAndrew.Bardsley@arm.com " needsResponse: %d packetSize: %s requestSize: %s responseSize:" 58410259SAndrew.Bardsley@arm.com " %s\n", packet->isRead(), packet->isWrite(), 58510259SAndrew.Bardsley@arm.com packet->needsResponse(), packet->getSize(), request.getSize(), 58610259SAndrew.Bardsley@arm.com response->getSize()); 58710259SAndrew.Bardsley@arm.com 58810259SAndrew.Bardsley@arm.com /* A request can become complete by several paths, this is a sanity 58910259SAndrew.Bardsley@arm.com * check to make sure the packet's data is created */ 59010259SAndrew.Bardsley@arm.com if (!data) { 59110259SAndrew.Bardsley@arm.com data = new uint8_t[request.getSize()]; 59210259SAndrew.Bardsley@arm.com } 59310259SAndrew.Bardsley@arm.com 59410259SAndrew.Bardsley@arm.com if (isLoad) { 59510259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Copying read data\n"); 59610259SAndrew.Bardsley@arm.com std::memcpy(packet->getPtr<uint8_t>(), data, request.getSize()); 59710259SAndrew.Bardsley@arm.com } 59810259SAndrew.Bardsley@arm.com packet->makeResponse(); 59910259SAndrew.Bardsley@arm.com } 60010259SAndrew.Bardsley@arm.com 60110259SAndrew.Bardsley@arm.com /* Packets are all deallocated together in ~SplitLSQRequest */ 60210259SAndrew.Bardsley@arm.com} 60310259SAndrew.Bardsley@arm.com 60410259SAndrew.Bardsley@arm.comvoid 60510259SAndrew.Bardsley@arm.comLSQ::SplitDataRequest::sendNextFragmentToTranslation() 60610259SAndrew.Bardsley@arm.com{ 60710259SAndrew.Bardsley@arm.com unsigned int fragment_index = numTranslatedFragments; 60810259SAndrew.Bardsley@arm.com 60910259SAndrew.Bardsley@arm.com ThreadContext *thread = port.cpu.getContext( 61010259SAndrew.Bardsley@arm.com inst->id.threadId); 61110259SAndrew.Bardsley@arm.com 61210259SAndrew.Bardsley@arm.com DPRINTFS(MinorMem, (&port), "Submitting DTLB request for fragment: %d\n", 61310259SAndrew.Bardsley@arm.com fragment_index); 61410259SAndrew.Bardsley@arm.com 61510259SAndrew.Bardsley@arm.com port.numAccessesInDTLB++; 61610259SAndrew.Bardsley@arm.com numInTranslationFragments++; 61710259SAndrew.Bardsley@arm.com 61810259SAndrew.Bardsley@arm.com thread->getDTBPtr()->translateTiming( 61910259SAndrew.Bardsley@arm.com fragmentRequests[fragment_index], thread, this, (isLoad ? 62010259SAndrew.Bardsley@arm.com BaseTLB::Read : BaseTLB::Write)); 62110259SAndrew.Bardsley@arm.com} 62210259SAndrew.Bardsley@arm.com 62310259SAndrew.Bardsley@arm.combool 62410259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::canInsert() const 62510259SAndrew.Bardsley@arm.com{ 62610259SAndrew.Bardsley@arm.com /* @todo, support store amalgamation */ 62710259SAndrew.Bardsley@arm.com return slots.size() < numSlots; 62810259SAndrew.Bardsley@arm.com} 62910259SAndrew.Bardsley@arm.com 63010259SAndrew.Bardsley@arm.comvoid 63110259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::deleteRequest(LSQRequestPtr request) 63210259SAndrew.Bardsley@arm.com{ 63310259SAndrew.Bardsley@arm.com auto found = std::find(slots.begin(), slots.end(), request); 63410259SAndrew.Bardsley@arm.com 63510259SAndrew.Bardsley@arm.com if (found != slots.end()) { 63610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Deleting request: %s %s %s from StoreBuffer\n", 63710259SAndrew.Bardsley@arm.com request, *found, *(request->inst)); 63810259SAndrew.Bardsley@arm.com slots.erase(found); 63910259SAndrew.Bardsley@arm.com 64010259SAndrew.Bardsley@arm.com delete request; 64110259SAndrew.Bardsley@arm.com } 64210259SAndrew.Bardsley@arm.com} 64310259SAndrew.Bardsley@arm.com 64410259SAndrew.Bardsley@arm.comvoid 64510259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::insert(LSQRequestPtr request) 64610259SAndrew.Bardsley@arm.com{ 64710259SAndrew.Bardsley@arm.com if (!canInsert()) { 64810259SAndrew.Bardsley@arm.com warn("%s: store buffer insertion without space to insert from" 64910259SAndrew.Bardsley@arm.com " inst: %s\n", name(), *(request->inst)); 65010259SAndrew.Bardsley@arm.com } 65110259SAndrew.Bardsley@arm.com 65210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Pushing store: %s into store buffer\n", request); 65310259SAndrew.Bardsley@arm.com 65410259SAndrew.Bardsley@arm.com numUnissuedAccesses++; 65510259SAndrew.Bardsley@arm.com 65610259SAndrew.Bardsley@arm.com if (request->state != LSQRequest::Complete) 65710259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreInStoreBuffer); 65810259SAndrew.Bardsley@arm.com 65910259SAndrew.Bardsley@arm.com slots.push_back(request); 66010259SAndrew.Bardsley@arm.com 66110259SAndrew.Bardsley@arm.com /* Let's try and wake up the processor for the next cycle to step 66210259SAndrew.Bardsley@arm.com * the store buffer */ 66310259SAndrew.Bardsley@arm.com lsq.cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 66410259SAndrew.Bardsley@arm.com} 66510259SAndrew.Bardsley@arm.com 66610259SAndrew.Bardsley@arm.comLSQ::AddrRangeCoverage 66710259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::canForwardDataToLoad(LSQRequestPtr request, 66810259SAndrew.Bardsley@arm.com unsigned int &found_slot) 66910259SAndrew.Bardsley@arm.com{ 67010259SAndrew.Bardsley@arm.com unsigned int slot_index = slots.size() - 1; 67110259SAndrew.Bardsley@arm.com auto i = slots.rbegin(); 67210259SAndrew.Bardsley@arm.com AddrRangeCoverage ret = NoAddrRangeCoverage; 67310259SAndrew.Bardsley@arm.com 67410259SAndrew.Bardsley@arm.com /* Traverse the store buffer in reverse order (most to least recent) 67510259SAndrew.Bardsley@arm.com * and try to find a slot whose address range overlaps this request */ 67610259SAndrew.Bardsley@arm.com while (ret == NoAddrRangeCoverage && i != slots.rend()) { 67710259SAndrew.Bardsley@arm.com LSQRequestPtr slot = *i; 67810259SAndrew.Bardsley@arm.com 67910259SAndrew.Bardsley@arm.com if (slot->packet) { 68010259SAndrew.Bardsley@arm.com AddrRangeCoverage coverage = slot->containsAddrRangeOf(request); 68110259SAndrew.Bardsley@arm.com 68210259SAndrew.Bardsley@arm.com if (coverage != NoAddrRangeCoverage) { 68310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Forwarding: slot: %d result: %s thisAddr:" 68410259SAndrew.Bardsley@arm.com " 0x%x thisSize: %d slotAddr: 0x%x slotSize: %d\n", 68510259SAndrew.Bardsley@arm.com slot_index, coverage, 68610259SAndrew.Bardsley@arm.com request->request.getPaddr(), request->request.getSize(), 68710259SAndrew.Bardsley@arm.com slot->request.getPaddr(), slot->request.getSize()); 68810259SAndrew.Bardsley@arm.com 68910259SAndrew.Bardsley@arm.com found_slot = slot_index; 69010259SAndrew.Bardsley@arm.com ret = coverage; 69110259SAndrew.Bardsley@arm.com } 69210259SAndrew.Bardsley@arm.com } 69310259SAndrew.Bardsley@arm.com 69410259SAndrew.Bardsley@arm.com i++; 69510259SAndrew.Bardsley@arm.com slot_index--; 69610259SAndrew.Bardsley@arm.com } 69710259SAndrew.Bardsley@arm.com 69810259SAndrew.Bardsley@arm.com return ret; 69910259SAndrew.Bardsley@arm.com} 70010259SAndrew.Bardsley@arm.com 70110259SAndrew.Bardsley@arm.com/** Fill the given packet with appropriate date from slot slot_number */ 70210259SAndrew.Bardsley@arm.comvoid 70310259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::forwardStoreData(LSQRequestPtr load, 70410259SAndrew.Bardsley@arm.com unsigned int slot_number) 70510259SAndrew.Bardsley@arm.com{ 70610259SAndrew.Bardsley@arm.com assert(slot_number < slots.size()); 70710259SAndrew.Bardsley@arm.com assert(load->packet); 70810259SAndrew.Bardsley@arm.com assert(load->isLoad); 70910259SAndrew.Bardsley@arm.com 71010259SAndrew.Bardsley@arm.com LSQRequestPtr store = slots[slot_number]; 71110259SAndrew.Bardsley@arm.com 71210259SAndrew.Bardsley@arm.com assert(store->packet); 71310259SAndrew.Bardsley@arm.com assert(store->containsAddrRangeOf(load) == FullAddrRangeCoverage); 71410259SAndrew.Bardsley@arm.com 71510259SAndrew.Bardsley@arm.com Addr load_addr = load->request.getPaddr(); 71610259SAndrew.Bardsley@arm.com Addr store_addr = store->request.getPaddr(); 71710259SAndrew.Bardsley@arm.com Addr addr_offset = load_addr - store_addr; 71810259SAndrew.Bardsley@arm.com 71910259SAndrew.Bardsley@arm.com unsigned int load_size = load->request.getSize(); 72010259SAndrew.Bardsley@arm.com 72110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Forwarding %d bytes for addr: 0x%x from store buffer" 72210259SAndrew.Bardsley@arm.com " slot: %d addr: 0x%x addressOffset: 0x%x\n", 72310259SAndrew.Bardsley@arm.com load_size, load_addr, slot_number, 72410259SAndrew.Bardsley@arm.com store_addr, addr_offset); 72510259SAndrew.Bardsley@arm.com 72610259SAndrew.Bardsley@arm.com void *load_packet_data = load->packet->getPtr<void>(); 72710259SAndrew.Bardsley@arm.com void *store_packet_data = store->packet->getPtr<uint8_t>() + addr_offset; 72810259SAndrew.Bardsley@arm.com 72910259SAndrew.Bardsley@arm.com std::memcpy(load_packet_data, store_packet_data, load_size); 73010259SAndrew.Bardsley@arm.com} 73110259SAndrew.Bardsley@arm.com 73210259SAndrew.Bardsley@arm.comvoid 73310581SAndrew.Bardsley@arm.comLSQ::StoreBuffer::countIssuedStore(LSQRequestPtr request) 73410581SAndrew.Bardsley@arm.com{ 73510581SAndrew.Bardsley@arm.com /* Barriers are accounted for as they are cleared from 73610581SAndrew.Bardsley@arm.com * the queue, not after their transfers are complete */ 73710581SAndrew.Bardsley@arm.com if (!request->isBarrier()) 73810581SAndrew.Bardsley@arm.com numUnissuedAccesses--; 73910581SAndrew.Bardsley@arm.com} 74010581SAndrew.Bardsley@arm.com 74110581SAndrew.Bardsley@arm.comvoid 74210259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::step() 74310259SAndrew.Bardsley@arm.com{ 74410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "StoreBuffer step numUnissuedAccesses: %d\n", 74510259SAndrew.Bardsley@arm.com numUnissuedAccesses); 74610259SAndrew.Bardsley@arm.com 74710259SAndrew.Bardsley@arm.com if (numUnissuedAccesses != 0 && lsq.state == LSQ::MemoryRunning) { 74810259SAndrew.Bardsley@arm.com /* Clear all the leading barriers */ 74910259SAndrew.Bardsley@arm.com while (!slots.empty() && 75010259SAndrew.Bardsley@arm.com slots.front()->isComplete() && slots.front()->isBarrier()) 75110259SAndrew.Bardsley@arm.com { 75210259SAndrew.Bardsley@arm.com LSQRequestPtr barrier = slots.front(); 75310259SAndrew.Bardsley@arm.com 75410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Clearing barrier for inst: %s\n", 75510259SAndrew.Bardsley@arm.com *(barrier->inst)); 75610259SAndrew.Bardsley@arm.com 75710259SAndrew.Bardsley@arm.com numUnissuedAccesses--; 75810259SAndrew.Bardsley@arm.com lsq.clearMemBarrier(barrier->inst); 75910259SAndrew.Bardsley@arm.com slots.pop_front(); 76010259SAndrew.Bardsley@arm.com 76110259SAndrew.Bardsley@arm.com delete barrier; 76210259SAndrew.Bardsley@arm.com } 76310259SAndrew.Bardsley@arm.com 76410259SAndrew.Bardsley@arm.com auto i = slots.begin(); 76510259SAndrew.Bardsley@arm.com bool issued = true; 76610259SAndrew.Bardsley@arm.com unsigned int issue_count = 0; 76710259SAndrew.Bardsley@arm.com 76810259SAndrew.Bardsley@arm.com /* Skip trying if the memory system is busy */ 76910259SAndrew.Bardsley@arm.com if (lsq.state == LSQ::MemoryNeedsRetry) 77010259SAndrew.Bardsley@arm.com issued = false; 77110259SAndrew.Bardsley@arm.com 77210259SAndrew.Bardsley@arm.com /* Try to issue all stores in order starting from the head 77310259SAndrew.Bardsley@arm.com * of the queue. Responses are allowed to be retired 77410259SAndrew.Bardsley@arm.com * out of order */ 77510259SAndrew.Bardsley@arm.com while (issued && 77610259SAndrew.Bardsley@arm.com issue_count < storeLimitPerCycle && 77710259SAndrew.Bardsley@arm.com lsq.canSendToMemorySystem() && 77810259SAndrew.Bardsley@arm.com i != slots.end()) 77910259SAndrew.Bardsley@arm.com { 78010259SAndrew.Bardsley@arm.com LSQRequestPtr request = *i; 78110259SAndrew.Bardsley@arm.com 78210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Considering request: %s, sentAllPackets: %d" 78310259SAndrew.Bardsley@arm.com " state: %s\n", 78410259SAndrew.Bardsley@arm.com *(request->inst), request->sentAllPackets(), 78510259SAndrew.Bardsley@arm.com request->state); 78610259SAndrew.Bardsley@arm.com 78710259SAndrew.Bardsley@arm.com if (request->isBarrier() && request->isComplete()) { 78810259SAndrew.Bardsley@arm.com /* Give up at barriers */ 78910259SAndrew.Bardsley@arm.com issued = false; 79010259SAndrew.Bardsley@arm.com } else if (!(request->state == LSQRequest::StoreBufferIssuing && 79110259SAndrew.Bardsley@arm.com request->sentAllPackets())) 79210259SAndrew.Bardsley@arm.com { 79310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Trying to send request: %s to memory" 79410259SAndrew.Bardsley@arm.com " system\n", *(request->inst)); 79510259SAndrew.Bardsley@arm.com 79610259SAndrew.Bardsley@arm.com if (lsq.tryToSend(request)) { 79710581SAndrew.Bardsley@arm.com countIssuedStore(request); 79810259SAndrew.Bardsley@arm.com issue_count++; 79910259SAndrew.Bardsley@arm.com } else { 80010259SAndrew.Bardsley@arm.com /* Don't step on to the next store buffer entry if this 80110259SAndrew.Bardsley@arm.com * one hasn't issued all its packets as the store 80210259SAndrew.Bardsley@arm.com * buffer must still enforce ordering */ 80310259SAndrew.Bardsley@arm.com issued = false; 80410259SAndrew.Bardsley@arm.com } 80510259SAndrew.Bardsley@arm.com } 80610259SAndrew.Bardsley@arm.com i++; 80710259SAndrew.Bardsley@arm.com } 80810259SAndrew.Bardsley@arm.com } 80910259SAndrew.Bardsley@arm.com} 81010259SAndrew.Bardsley@arm.com 81110259SAndrew.Bardsley@arm.comvoid 81210259SAndrew.Bardsley@arm.comLSQ::completeMemBarrierInst(MinorDynInstPtr inst, 81310259SAndrew.Bardsley@arm.com bool committed) 81410259SAndrew.Bardsley@arm.com{ 81510259SAndrew.Bardsley@arm.com if (committed) { 81610259SAndrew.Bardsley@arm.com /* Not already sent to the store buffer as a store request? */ 81710259SAndrew.Bardsley@arm.com if (!inst->inStoreBuffer) { 81810259SAndrew.Bardsley@arm.com /* Insert an entry into the store buffer to tick off barriers 81910259SAndrew.Bardsley@arm.com * until there are none in flight */ 82010259SAndrew.Bardsley@arm.com storeBuffer.insert(new BarrierDataRequest(*this, inst)); 82110259SAndrew.Bardsley@arm.com } 82210259SAndrew.Bardsley@arm.com } else { 82310259SAndrew.Bardsley@arm.com /* Clear the barrier anyway if it wasn't actually committed */ 82410259SAndrew.Bardsley@arm.com clearMemBarrier(inst); 82510259SAndrew.Bardsley@arm.com } 82610259SAndrew.Bardsley@arm.com} 82710259SAndrew.Bardsley@arm.com 82810259SAndrew.Bardsley@arm.comvoid 82910259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::minorTrace() const 83010259SAndrew.Bardsley@arm.com{ 83110259SAndrew.Bardsley@arm.com unsigned int size = slots.size(); 83210259SAndrew.Bardsley@arm.com unsigned int i = 0; 83310259SAndrew.Bardsley@arm.com std::ostringstream os; 83410259SAndrew.Bardsley@arm.com 83510259SAndrew.Bardsley@arm.com while (i < size) { 83610259SAndrew.Bardsley@arm.com LSQRequestPtr request = slots[i]; 83710259SAndrew.Bardsley@arm.com 83810259SAndrew.Bardsley@arm.com request->reportData(os); 83910259SAndrew.Bardsley@arm.com 84010259SAndrew.Bardsley@arm.com i++; 84110259SAndrew.Bardsley@arm.com if (i < numSlots) 84210259SAndrew.Bardsley@arm.com os << ','; 84310259SAndrew.Bardsley@arm.com } 84410259SAndrew.Bardsley@arm.com 84510259SAndrew.Bardsley@arm.com while (i < numSlots) { 84610259SAndrew.Bardsley@arm.com os << '-'; 84710259SAndrew.Bardsley@arm.com 84810259SAndrew.Bardsley@arm.com i++; 84910259SAndrew.Bardsley@arm.com if (i < numSlots) 85010259SAndrew.Bardsley@arm.com os << ','; 85110259SAndrew.Bardsley@arm.com } 85210259SAndrew.Bardsley@arm.com 85310259SAndrew.Bardsley@arm.com MINORTRACE("addr=%s num_unissued_stores=%d\n", os.str(), 85410259SAndrew.Bardsley@arm.com numUnissuedAccesses); 85510259SAndrew.Bardsley@arm.com} 85610259SAndrew.Bardsley@arm.com 85710259SAndrew.Bardsley@arm.comvoid 85810259SAndrew.Bardsley@arm.comLSQ::tryToSendToTransfers(LSQRequestPtr request) 85910259SAndrew.Bardsley@arm.com{ 86010259SAndrew.Bardsley@arm.com if (state == MemoryNeedsRetry) { 86110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request needs retry, not issuing to" 86210259SAndrew.Bardsley@arm.com " memory until retry arrives\n"); 86310259SAndrew.Bardsley@arm.com return; 86410259SAndrew.Bardsley@arm.com } 86510259SAndrew.Bardsley@arm.com 86610259SAndrew.Bardsley@arm.com if (request->state == LSQRequest::InTranslation) { 86710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request still in translation, not issuing to" 86810259SAndrew.Bardsley@arm.com " memory\n"); 86910259SAndrew.Bardsley@arm.com return; 87010259SAndrew.Bardsley@arm.com } 87110259SAndrew.Bardsley@arm.com 87210259SAndrew.Bardsley@arm.com assert(request->state == LSQRequest::Translated || 87310259SAndrew.Bardsley@arm.com request->state == LSQRequest::RequestIssuing || 87410259SAndrew.Bardsley@arm.com request->state == LSQRequest::Failed || 87510259SAndrew.Bardsley@arm.com request->state == LSQRequest::Complete); 87610259SAndrew.Bardsley@arm.com 87710259SAndrew.Bardsley@arm.com if (requests.empty() || requests.front() != request) { 87810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request not at front of requests queue, can't" 87910259SAndrew.Bardsley@arm.com " issue to memory\n"); 88010259SAndrew.Bardsley@arm.com return; 88110259SAndrew.Bardsley@arm.com } 88210259SAndrew.Bardsley@arm.com 88310259SAndrew.Bardsley@arm.com if (transfers.unreservedRemainingSpace() == 0) { 88410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "No space to insert request into transfers" 88510259SAndrew.Bardsley@arm.com " queue\n"); 88610259SAndrew.Bardsley@arm.com return; 88710259SAndrew.Bardsley@arm.com } 88810259SAndrew.Bardsley@arm.com 88910259SAndrew.Bardsley@arm.com if (request->isComplete() || request->state == LSQRequest::Failed) { 89010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Passing a %s transfer on to transfers" 89110259SAndrew.Bardsley@arm.com " queue\n", (request->isComplete() ? "completed" : "failed")); 89210259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 89310259SAndrew.Bardsley@arm.com request->setSkipped(); 89410259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 89510259SAndrew.Bardsley@arm.com return; 89610259SAndrew.Bardsley@arm.com } 89710259SAndrew.Bardsley@arm.com 89810259SAndrew.Bardsley@arm.com if (!execute.instIsRightStream(request->inst)) { 89910259SAndrew.Bardsley@arm.com /* Wrong stream, try to abort the transfer but only do so if 90010259SAndrew.Bardsley@arm.com * there are no packets in flight */ 90110259SAndrew.Bardsley@arm.com if (request->hasPacketsInMemSystem()) { 90210259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request's inst. is from the wrong stream," 90310259SAndrew.Bardsley@arm.com " waiting for responses before aborting request\n"); 90410259SAndrew.Bardsley@arm.com } else { 90510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Request's inst. is from the wrong stream," 90610259SAndrew.Bardsley@arm.com " aborting request\n"); 90710259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 90810259SAndrew.Bardsley@arm.com request->setSkipped(); 90910259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 91010259SAndrew.Bardsley@arm.com } 91110259SAndrew.Bardsley@arm.com return; 91210259SAndrew.Bardsley@arm.com } 91310259SAndrew.Bardsley@arm.com 91410259SAndrew.Bardsley@arm.com if (request->fault != NoFault) { 91510259SAndrew.Bardsley@arm.com if (request->inst->staticInst->isPrefetch()) { 91610259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Not signalling fault for faulting prefetch\n"); 91710259SAndrew.Bardsley@arm.com } 91810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Moving faulting request into the transfers" 91910259SAndrew.Bardsley@arm.com " queue\n"); 92010259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 92110259SAndrew.Bardsley@arm.com request->setSkipped(); 92210259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 92310259SAndrew.Bardsley@arm.com return; 92410259SAndrew.Bardsley@arm.com } 92510259SAndrew.Bardsley@arm.com 92610259SAndrew.Bardsley@arm.com bool is_load = request->isLoad; 92710259SAndrew.Bardsley@arm.com bool is_llsc = request->request.isLLSC(); 92810259SAndrew.Bardsley@arm.com bool is_swap = request->request.isSwap(); 92910824SAndreas.Sandberg@ARM.com bool bufferable = !(request->request.isStrictlyOrdered() || 93010259SAndrew.Bardsley@arm.com is_llsc || is_swap); 93110259SAndrew.Bardsley@arm.com 93210259SAndrew.Bardsley@arm.com if (is_load) { 93310259SAndrew.Bardsley@arm.com if (numStoresInTransfers != 0) { 93410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Load request with stores still in transfers" 93510259SAndrew.Bardsley@arm.com " queue, stalling\n"); 93610259SAndrew.Bardsley@arm.com return; 93710259SAndrew.Bardsley@arm.com } 93810259SAndrew.Bardsley@arm.com } else { 93910259SAndrew.Bardsley@arm.com /* Store. Can it be sent to the store buffer? */ 94010259SAndrew.Bardsley@arm.com if (bufferable && !request->request.isMmappedIpr()) { 94110259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreToStoreBuffer); 94210259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 94310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Moving store into transfers queue\n"); 94410259SAndrew.Bardsley@arm.com return; 94510259SAndrew.Bardsley@arm.com } 94610259SAndrew.Bardsley@arm.com } 94710259SAndrew.Bardsley@arm.com 94810259SAndrew.Bardsley@arm.com /* Check if this is the head instruction (and so must be executable as 94910259SAndrew.Bardsley@arm.com * its stream sequence number was checked above) for loads which must 95010259SAndrew.Bardsley@arm.com * not be speculatively issued and stores which must be issued here */ 95110259SAndrew.Bardsley@arm.com if (!bufferable) { 95210259SAndrew.Bardsley@arm.com if (!execute.instIsHeadInst(request->inst)) { 95310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Memory access not the head inst., can't be" 95410259SAndrew.Bardsley@arm.com " sure it can be performed, not issuing\n"); 95510259SAndrew.Bardsley@arm.com return; 95610259SAndrew.Bardsley@arm.com } 95710259SAndrew.Bardsley@arm.com 95810259SAndrew.Bardsley@arm.com unsigned int forwarding_slot = 0; 95910259SAndrew.Bardsley@arm.com 96010259SAndrew.Bardsley@arm.com if (storeBuffer.canForwardDataToLoad(request, forwarding_slot) != 96110259SAndrew.Bardsley@arm.com NoAddrRangeCoverage) 96210259SAndrew.Bardsley@arm.com { 96310259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Memory access can receive forwarded data" 96410259SAndrew.Bardsley@arm.com " from the store buffer, need to wait for store buffer to" 96510259SAndrew.Bardsley@arm.com " drain\n"); 96610259SAndrew.Bardsley@arm.com return; 96710259SAndrew.Bardsley@arm.com } 96810259SAndrew.Bardsley@arm.com } 96910259SAndrew.Bardsley@arm.com 97010259SAndrew.Bardsley@arm.com /* True: submit this packet to the transfers queue to be sent to the 97110259SAndrew.Bardsley@arm.com * memory system. 97210259SAndrew.Bardsley@arm.com * False: skip the memory and push a packet for this request onto 97310259SAndrew.Bardsley@arm.com * requests */ 97410259SAndrew.Bardsley@arm.com bool do_access = true; 97510259SAndrew.Bardsley@arm.com 97610259SAndrew.Bardsley@arm.com if (!is_llsc) { 97710259SAndrew.Bardsley@arm.com /* Check for match in the store buffer */ 97810259SAndrew.Bardsley@arm.com if (is_load) { 97910259SAndrew.Bardsley@arm.com unsigned int forwarding_slot = 0; 98010259SAndrew.Bardsley@arm.com AddrRangeCoverage forwarding_result = 98110259SAndrew.Bardsley@arm.com storeBuffer.canForwardDataToLoad(request, 98210259SAndrew.Bardsley@arm.com forwarding_slot); 98310259SAndrew.Bardsley@arm.com 98410259SAndrew.Bardsley@arm.com switch (forwarding_result) { 98510259SAndrew.Bardsley@arm.com case FullAddrRangeCoverage: 98610259SAndrew.Bardsley@arm.com /* Forward data from the store buffer into this request and 98710259SAndrew.Bardsley@arm.com * repurpose this request's packet into a response packet */ 98810259SAndrew.Bardsley@arm.com storeBuffer.forwardStoreData(request, forwarding_slot); 98910259SAndrew.Bardsley@arm.com request->packet->makeResponse(); 99010259SAndrew.Bardsley@arm.com 99110259SAndrew.Bardsley@arm.com /* Just move between queues, no access */ 99210259SAndrew.Bardsley@arm.com do_access = false; 99310259SAndrew.Bardsley@arm.com break; 99410259SAndrew.Bardsley@arm.com case PartialAddrRangeCoverage: 99510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Load partly satisfied by store buffer" 99610259SAndrew.Bardsley@arm.com " data. Must wait for the store to complete\n"); 99710259SAndrew.Bardsley@arm.com return; 99810259SAndrew.Bardsley@arm.com break; 99910259SAndrew.Bardsley@arm.com case NoAddrRangeCoverage: 100010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "No forwardable data from store buffer\n"); 100110259SAndrew.Bardsley@arm.com /* Fall through to try access */ 100210259SAndrew.Bardsley@arm.com break; 100310259SAndrew.Bardsley@arm.com } 100410259SAndrew.Bardsley@arm.com } 100510259SAndrew.Bardsley@arm.com } else { 100610259SAndrew.Bardsley@arm.com if (!canSendToMemorySystem()) { 100710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Can't send request to memory system yet\n"); 100810259SAndrew.Bardsley@arm.com return; 100910259SAndrew.Bardsley@arm.com } 101010259SAndrew.Bardsley@arm.com 101110259SAndrew.Bardsley@arm.com SimpleThread &thread = *cpu.threads[request->inst->id.threadId]; 101210259SAndrew.Bardsley@arm.com 101310259SAndrew.Bardsley@arm.com TheISA::PCState old_pc = thread.pcState(); 101410259SAndrew.Bardsley@arm.com ExecContext context(cpu, thread, execute, request->inst); 101510259SAndrew.Bardsley@arm.com 101610259SAndrew.Bardsley@arm.com /* Handle LLSC requests and tests */ 101710259SAndrew.Bardsley@arm.com if (is_load) { 101810259SAndrew.Bardsley@arm.com TheISA::handleLockedRead(&context, &request->request); 101910259SAndrew.Bardsley@arm.com } else { 102010259SAndrew.Bardsley@arm.com do_access = TheISA::handleLockedWrite(&context, 102110259SAndrew.Bardsley@arm.com &request->request, cacheBlockMask); 102210259SAndrew.Bardsley@arm.com 102310259SAndrew.Bardsley@arm.com if (!do_access) { 102410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Not perfoming a memory " 102510259SAndrew.Bardsley@arm.com "access for store conditional\n"); 102610259SAndrew.Bardsley@arm.com } 102710259SAndrew.Bardsley@arm.com } 102810259SAndrew.Bardsley@arm.com thread.pcState(old_pc); 102910259SAndrew.Bardsley@arm.com } 103010259SAndrew.Bardsley@arm.com 103110259SAndrew.Bardsley@arm.com /* See the do_access comment above */ 103210259SAndrew.Bardsley@arm.com if (do_access) { 103310259SAndrew.Bardsley@arm.com if (!canSendToMemorySystem()) { 103410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Can't send request to memory system yet\n"); 103510259SAndrew.Bardsley@arm.com return; 103610259SAndrew.Bardsley@arm.com } 103710259SAndrew.Bardsley@arm.com 103810259SAndrew.Bardsley@arm.com /* Remember if this is an access which can't be idly 103910259SAndrew.Bardsley@arm.com * discarded by an interrupt */ 104010368SAndrew.Bardsley@arm.com if (!bufferable && !request->issuedToMemory) { 104110259SAndrew.Bardsley@arm.com numAccessesIssuedToMemory++; 104210259SAndrew.Bardsley@arm.com request->issuedToMemory = true; 104310259SAndrew.Bardsley@arm.com } 104410259SAndrew.Bardsley@arm.com 104510259SAndrew.Bardsley@arm.com if (tryToSend(request)) 104610259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 104710259SAndrew.Bardsley@arm.com } else { 104810259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 104910259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(request); 105010259SAndrew.Bardsley@arm.com } 105110259SAndrew.Bardsley@arm.com} 105210259SAndrew.Bardsley@arm.com 105310259SAndrew.Bardsley@arm.combool 105410259SAndrew.Bardsley@arm.comLSQ::tryToSend(LSQRequestPtr request) 105510259SAndrew.Bardsley@arm.com{ 105610259SAndrew.Bardsley@arm.com bool ret = false; 105710259SAndrew.Bardsley@arm.com 105810259SAndrew.Bardsley@arm.com if (!canSendToMemorySystem()) { 105910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Can't send request: %s yet, no space in memory\n", 106010259SAndrew.Bardsley@arm.com *(request->inst)); 106110259SAndrew.Bardsley@arm.com } else { 106210259SAndrew.Bardsley@arm.com PacketPtr packet = request->getHeadPacket(); 106310259SAndrew.Bardsley@arm.com 106410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Trying to send request: %s addr: 0x%x\n", 106510259SAndrew.Bardsley@arm.com *(request->inst), packet->req->getVaddr()); 106610259SAndrew.Bardsley@arm.com 106710259SAndrew.Bardsley@arm.com /* The sender state of the packet *must* be an LSQRequest 106810259SAndrew.Bardsley@arm.com * so the response can be correctly handled */ 106910259SAndrew.Bardsley@arm.com assert(packet->findNextSenderState<LSQRequest>()); 107010259SAndrew.Bardsley@arm.com 107110259SAndrew.Bardsley@arm.com if (request->request.isMmappedIpr()) { 107210259SAndrew.Bardsley@arm.com ThreadContext *thread = 107311435Smitch.hayenga@arm.com cpu.getContext(cpu.contextToThread( 107411435Smitch.hayenga@arm.com request->request.contextId())); 107510259SAndrew.Bardsley@arm.com 107610259SAndrew.Bardsley@arm.com if (request->isLoad) { 107710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "IPR read inst: %s\n", *(request->inst)); 107810259SAndrew.Bardsley@arm.com TheISA::handleIprRead(thread, packet); 107910259SAndrew.Bardsley@arm.com } else { 108010259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "IPR write inst: %s\n", *(request->inst)); 108110259SAndrew.Bardsley@arm.com TheISA::handleIprWrite(thread, packet); 108210259SAndrew.Bardsley@arm.com } 108310259SAndrew.Bardsley@arm.com 108410259SAndrew.Bardsley@arm.com request->stepToNextPacket(); 108510259SAndrew.Bardsley@arm.com ret = request->sentAllPackets(); 108610259SAndrew.Bardsley@arm.com 108710259SAndrew.Bardsley@arm.com if (!ret) { 108810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "IPR access has another packet: %s\n", 108910259SAndrew.Bardsley@arm.com *(request->inst)); 109010259SAndrew.Bardsley@arm.com } 109110259SAndrew.Bardsley@arm.com 109210259SAndrew.Bardsley@arm.com if (ret) 109310259SAndrew.Bardsley@arm.com request->setState(LSQRequest::Complete); 109410259SAndrew.Bardsley@arm.com else 109510259SAndrew.Bardsley@arm.com request->setState(LSQRequest::RequestIssuing); 109610259SAndrew.Bardsley@arm.com } else if (dcachePort.sendTimingReq(packet)) { 109710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Sent data memory request\n"); 109810259SAndrew.Bardsley@arm.com 109910259SAndrew.Bardsley@arm.com numAccessesInMemorySystem++; 110010259SAndrew.Bardsley@arm.com 110110259SAndrew.Bardsley@arm.com request->stepToNextPacket(); 110210259SAndrew.Bardsley@arm.com 110310259SAndrew.Bardsley@arm.com ret = request->sentAllPackets(); 110410259SAndrew.Bardsley@arm.com 110510259SAndrew.Bardsley@arm.com switch (request->state) { 110610259SAndrew.Bardsley@arm.com case LSQRequest::Translated: 110710259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 110810259SAndrew.Bardsley@arm.com /* Fully or partially issued a request in the transfers 110910259SAndrew.Bardsley@arm.com * queue */ 111010259SAndrew.Bardsley@arm.com request->setState(LSQRequest::RequestIssuing); 111110259SAndrew.Bardsley@arm.com break; 111210259SAndrew.Bardsley@arm.com case LSQRequest::StoreInStoreBuffer: 111310259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 111410259SAndrew.Bardsley@arm.com /* Fully or partially issued a request in the store 111510259SAndrew.Bardsley@arm.com * buffer */ 111610259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreBufferIssuing); 111710259SAndrew.Bardsley@arm.com break; 111810259SAndrew.Bardsley@arm.com default: 111910259SAndrew.Bardsley@arm.com assert(false); 112010259SAndrew.Bardsley@arm.com break; 112110259SAndrew.Bardsley@arm.com } 112210259SAndrew.Bardsley@arm.com 112310259SAndrew.Bardsley@arm.com state = MemoryRunning; 112410259SAndrew.Bardsley@arm.com } else { 112510259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, 112610259SAndrew.Bardsley@arm.com "Sending data memory request - needs retry\n"); 112710259SAndrew.Bardsley@arm.com 112810259SAndrew.Bardsley@arm.com /* Needs to be resent, wait for that */ 112910259SAndrew.Bardsley@arm.com state = MemoryNeedsRetry; 113010259SAndrew.Bardsley@arm.com retryRequest = request; 113110259SAndrew.Bardsley@arm.com 113210259SAndrew.Bardsley@arm.com switch (request->state) { 113310259SAndrew.Bardsley@arm.com case LSQRequest::Translated: 113410259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 113510259SAndrew.Bardsley@arm.com request->setState(LSQRequest::RequestNeedsRetry); 113610259SAndrew.Bardsley@arm.com break; 113710259SAndrew.Bardsley@arm.com case LSQRequest::StoreInStoreBuffer: 113810259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 113910259SAndrew.Bardsley@arm.com request->setState(LSQRequest::StoreBufferNeedsRetry); 114010259SAndrew.Bardsley@arm.com break; 114110259SAndrew.Bardsley@arm.com default: 114210259SAndrew.Bardsley@arm.com assert(false); 114310259SAndrew.Bardsley@arm.com break; 114410259SAndrew.Bardsley@arm.com } 114510259SAndrew.Bardsley@arm.com } 114610259SAndrew.Bardsley@arm.com } 114710259SAndrew.Bardsley@arm.com 114810259SAndrew.Bardsley@arm.com return ret; 114910259SAndrew.Bardsley@arm.com} 115010259SAndrew.Bardsley@arm.com 115110259SAndrew.Bardsley@arm.comvoid 115210259SAndrew.Bardsley@arm.comLSQ::moveFromRequestsToTransfers(LSQRequestPtr request) 115310259SAndrew.Bardsley@arm.com{ 115410259SAndrew.Bardsley@arm.com assert(!requests.empty() && requests.front() == request); 115510259SAndrew.Bardsley@arm.com assert(transfers.unreservedRemainingSpace() != 0); 115610259SAndrew.Bardsley@arm.com 115710259SAndrew.Bardsley@arm.com /* Need to count the number of stores in the transfers 115810259SAndrew.Bardsley@arm.com * queue so that loads know when their store buffer forwarding 115910259SAndrew.Bardsley@arm.com * results will be correct (only when all those stores 116010259SAndrew.Bardsley@arm.com * have reached the store buffer) */ 116110259SAndrew.Bardsley@arm.com if (!request->isLoad) 116210259SAndrew.Bardsley@arm.com numStoresInTransfers++; 116310259SAndrew.Bardsley@arm.com 116410259SAndrew.Bardsley@arm.com requests.pop(); 116510259SAndrew.Bardsley@arm.com transfers.push(request); 116610259SAndrew.Bardsley@arm.com} 116710259SAndrew.Bardsley@arm.com 116810259SAndrew.Bardsley@arm.combool 116910259SAndrew.Bardsley@arm.comLSQ::canSendToMemorySystem() 117010259SAndrew.Bardsley@arm.com{ 117110259SAndrew.Bardsley@arm.com return state == MemoryRunning && 117210259SAndrew.Bardsley@arm.com numAccessesInMemorySystem < inMemorySystemLimit; 117310259SAndrew.Bardsley@arm.com} 117410259SAndrew.Bardsley@arm.com 117510259SAndrew.Bardsley@arm.combool 117610259SAndrew.Bardsley@arm.comLSQ::recvTimingResp(PacketPtr response) 117710259SAndrew.Bardsley@arm.com{ 117810259SAndrew.Bardsley@arm.com LSQRequestPtr request = 117910259SAndrew.Bardsley@arm.com safe_cast<LSQRequestPtr>(response->popSenderState()); 118010259SAndrew.Bardsley@arm.com 118110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Received response packet inst: %s" 118210259SAndrew.Bardsley@arm.com " addr: 0x%x cmd: %s\n", 118310259SAndrew.Bardsley@arm.com *(request->inst), response->getAddr(), 118410259SAndrew.Bardsley@arm.com response->cmd.toString()); 118510259SAndrew.Bardsley@arm.com 118610259SAndrew.Bardsley@arm.com numAccessesInMemorySystem--; 118710259SAndrew.Bardsley@arm.com 118810259SAndrew.Bardsley@arm.com if (response->isError()) { 118910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Received error response packet: %s\n", 119010259SAndrew.Bardsley@arm.com *request->inst); 119110259SAndrew.Bardsley@arm.com } 119210259SAndrew.Bardsley@arm.com 119310259SAndrew.Bardsley@arm.com switch (request->state) { 119410259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 119510259SAndrew.Bardsley@arm.com case LSQRequest::RequestNeedsRetry: 119610259SAndrew.Bardsley@arm.com /* Response to a request from the transfers queue */ 119710259SAndrew.Bardsley@arm.com request->retireResponse(response); 119810259SAndrew.Bardsley@arm.com 119910259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Has outstanding packets?: %d %d\n", 120010259SAndrew.Bardsley@arm.com request->hasPacketsInMemSystem(), request->isComplete()); 120110259SAndrew.Bardsley@arm.com 120210259SAndrew.Bardsley@arm.com break; 120310259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 120410259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferNeedsRetry: 120510259SAndrew.Bardsley@arm.com /* Response to a request from the store buffer */ 120610259SAndrew.Bardsley@arm.com request->retireResponse(response); 120710259SAndrew.Bardsley@arm.com 120810581SAndrew.Bardsley@arm.com /* Remove completed requests unless they are barriers (which will 120910259SAndrew.Bardsley@arm.com * need to be removed in order */ 121010259SAndrew.Bardsley@arm.com if (request->isComplete()) { 121110259SAndrew.Bardsley@arm.com if (!request->isBarrier()) { 121210259SAndrew.Bardsley@arm.com storeBuffer.deleteRequest(request); 121310259SAndrew.Bardsley@arm.com } else { 121410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Completed transfer for barrier: %s" 121510259SAndrew.Bardsley@arm.com " leaving the request as it is also a barrier\n", 121610259SAndrew.Bardsley@arm.com *(request->inst)); 121710259SAndrew.Bardsley@arm.com } 121810259SAndrew.Bardsley@arm.com } 121910259SAndrew.Bardsley@arm.com break; 122010259SAndrew.Bardsley@arm.com default: 122110259SAndrew.Bardsley@arm.com /* Shouldn't be allowed to receive a response from another 122210259SAndrew.Bardsley@arm.com * state */ 122310259SAndrew.Bardsley@arm.com assert(false); 122410259SAndrew.Bardsley@arm.com break; 122510259SAndrew.Bardsley@arm.com } 122610259SAndrew.Bardsley@arm.com 122710259SAndrew.Bardsley@arm.com /* We go to idle even if there are more things in the requests queue 122810259SAndrew.Bardsley@arm.com * as it's the job of step to actually step us on to the next 122910259SAndrew.Bardsley@arm.com * transaction */ 123010259SAndrew.Bardsley@arm.com 123110259SAndrew.Bardsley@arm.com /* Let's try and wake up the processor for the next cycle */ 123210259SAndrew.Bardsley@arm.com cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 123310259SAndrew.Bardsley@arm.com 123410259SAndrew.Bardsley@arm.com /* Never busy */ 123510259SAndrew.Bardsley@arm.com return true; 123610259SAndrew.Bardsley@arm.com} 123710259SAndrew.Bardsley@arm.com 123810259SAndrew.Bardsley@arm.comvoid 123910713Sandreas.hansson@arm.comLSQ::recvReqRetry() 124010259SAndrew.Bardsley@arm.com{ 124110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Received retry request\n"); 124210259SAndrew.Bardsley@arm.com 124310259SAndrew.Bardsley@arm.com assert(state == MemoryNeedsRetry); 124410259SAndrew.Bardsley@arm.com 124510259SAndrew.Bardsley@arm.com switch (retryRequest->state) { 124610259SAndrew.Bardsley@arm.com case LSQRequest::RequestNeedsRetry: 124710259SAndrew.Bardsley@arm.com /* Retry in the requests queue */ 124810259SAndrew.Bardsley@arm.com retryRequest->setState(LSQRequest::Translated); 124910259SAndrew.Bardsley@arm.com break; 125010259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferNeedsRetry: 125110259SAndrew.Bardsley@arm.com /* Retry in the store buffer */ 125210259SAndrew.Bardsley@arm.com retryRequest->setState(LSQRequest::StoreInStoreBuffer); 125310259SAndrew.Bardsley@arm.com break; 125410259SAndrew.Bardsley@arm.com default: 125510259SAndrew.Bardsley@arm.com assert(false); 125610259SAndrew.Bardsley@arm.com } 125710259SAndrew.Bardsley@arm.com 125810259SAndrew.Bardsley@arm.com /* Set state back to MemoryRunning so that the following 125910259SAndrew.Bardsley@arm.com * tryToSend can actually send. Note that this won't 126010259SAndrew.Bardsley@arm.com * allow another transfer in as tryToSend should 126110259SAndrew.Bardsley@arm.com * issue a memory request and either succeed for this 126210259SAndrew.Bardsley@arm.com * request or return the LSQ back to MemoryNeedsRetry */ 126310259SAndrew.Bardsley@arm.com state = MemoryRunning; 126410259SAndrew.Bardsley@arm.com 126510259SAndrew.Bardsley@arm.com /* Try to resend the request */ 126610259SAndrew.Bardsley@arm.com if (tryToSend(retryRequest)) { 126710259SAndrew.Bardsley@arm.com /* Successfully sent, need to move the request */ 126810259SAndrew.Bardsley@arm.com switch (retryRequest->state) { 126910259SAndrew.Bardsley@arm.com case LSQRequest::RequestIssuing: 127010259SAndrew.Bardsley@arm.com /* In the requests queue */ 127110259SAndrew.Bardsley@arm.com moveFromRequestsToTransfers(retryRequest); 127210259SAndrew.Bardsley@arm.com break; 127310259SAndrew.Bardsley@arm.com case LSQRequest::StoreBufferIssuing: 127410259SAndrew.Bardsley@arm.com /* In the store buffer */ 127510581SAndrew.Bardsley@arm.com storeBuffer.countIssuedStore(retryRequest); 127610259SAndrew.Bardsley@arm.com break; 127710259SAndrew.Bardsley@arm.com default: 127810259SAndrew.Bardsley@arm.com assert(false); 127910259SAndrew.Bardsley@arm.com break; 128010259SAndrew.Bardsley@arm.com } 128110647Sandreas.hansson@arm.com 128210647Sandreas.hansson@arm.com retryRequest = NULL; 128310259SAndrew.Bardsley@arm.com } 128410259SAndrew.Bardsley@arm.com} 128510259SAndrew.Bardsley@arm.com 128610259SAndrew.Bardsley@arm.comLSQ::LSQ(std::string name_, std::string dcache_port_name_, 128710259SAndrew.Bardsley@arm.com MinorCPU &cpu_, Execute &execute_, 128810259SAndrew.Bardsley@arm.com unsigned int in_memory_system_limit, unsigned int line_width, 128910259SAndrew.Bardsley@arm.com unsigned int requests_queue_size, unsigned int transfers_queue_size, 129010259SAndrew.Bardsley@arm.com unsigned int store_buffer_size, 129110259SAndrew.Bardsley@arm.com unsigned int store_buffer_cycle_store_limit) : 129210259SAndrew.Bardsley@arm.com Named(name_), 129310259SAndrew.Bardsley@arm.com cpu(cpu_), 129410259SAndrew.Bardsley@arm.com execute(execute_), 129510259SAndrew.Bardsley@arm.com dcachePort(dcache_port_name_, *this, cpu_), 129610259SAndrew.Bardsley@arm.com lastMemBarrier(0), 129710259SAndrew.Bardsley@arm.com state(MemoryRunning), 129810259SAndrew.Bardsley@arm.com inMemorySystemLimit(in_memory_system_limit), 129910259SAndrew.Bardsley@arm.com lineWidth((line_width == 0 ? cpu.cacheLineSize() : line_width)), 130010259SAndrew.Bardsley@arm.com requests(name_ + ".requests", "addr", requests_queue_size), 130110259SAndrew.Bardsley@arm.com transfers(name_ + ".transfers", "addr", transfers_queue_size), 130210259SAndrew.Bardsley@arm.com storeBuffer(name_ + ".storeBuffer", 130310259SAndrew.Bardsley@arm.com *this, store_buffer_size, store_buffer_cycle_store_limit), 130410259SAndrew.Bardsley@arm.com numAccessesInMemorySystem(0), 130510259SAndrew.Bardsley@arm.com numAccessesInDTLB(0), 130610259SAndrew.Bardsley@arm.com numStoresInTransfers(0), 130710259SAndrew.Bardsley@arm.com numAccessesIssuedToMemory(0), 130810259SAndrew.Bardsley@arm.com retryRequest(NULL), 130910259SAndrew.Bardsley@arm.com cacheBlockMask(~(cpu_.cacheLineSize() - 1)) 131010259SAndrew.Bardsley@arm.com{ 131110259SAndrew.Bardsley@arm.com if (in_memory_system_limit < 1) { 131210259SAndrew.Bardsley@arm.com fatal("%s: executeMaxAccessesInMemory must be >= 1 (%d)\n", name_, 131310259SAndrew.Bardsley@arm.com in_memory_system_limit); 131410259SAndrew.Bardsley@arm.com } 131510259SAndrew.Bardsley@arm.com 131610259SAndrew.Bardsley@arm.com if (store_buffer_cycle_store_limit < 1) { 131710259SAndrew.Bardsley@arm.com fatal("%s: executeLSQMaxStoreBufferStoresPerCycle must be" 131810259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, store_buffer_cycle_store_limit); 131910259SAndrew.Bardsley@arm.com } 132010259SAndrew.Bardsley@arm.com 132110259SAndrew.Bardsley@arm.com if (requests_queue_size < 1) { 132210259SAndrew.Bardsley@arm.com fatal("%s: executeLSQRequestsQueueSize must be" 132310259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, requests_queue_size); 132410259SAndrew.Bardsley@arm.com } 132510259SAndrew.Bardsley@arm.com 132610259SAndrew.Bardsley@arm.com if (transfers_queue_size < 1) { 132710259SAndrew.Bardsley@arm.com fatal("%s: executeLSQTransfersQueueSize must be" 132810259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, transfers_queue_size); 132910259SAndrew.Bardsley@arm.com } 133010259SAndrew.Bardsley@arm.com 133110259SAndrew.Bardsley@arm.com if (store_buffer_size < 1) { 133210259SAndrew.Bardsley@arm.com fatal("%s: executeLSQStoreBufferSize must be" 133310259SAndrew.Bardsley@arm.com " >= 1 (%d)\n", name_, store_buffer_size); 133410259SAndrew.Bardsley@arm.com } 133510259SAndrew.Bardsley@arm.com 133610259SAndrew.Bardsley@arm.com if ((lineWidth & (lineWidth - 1)) != 0) { 133710259SAndrew.Bardsley@arm.com fatal("%s: lineWidth: %d must be a power of 2\n", name(), lineWidth); 133810259SAndrew.Bardsley@arm.com } 133910259SAndrew.Bardsley@arm.com} 134010259SAndrew.Bardsley@arm.com 134110259SAndrew.Bardsley@arm.comLSQ::~LSQ() 134210259SAndrew.Bardsley@arm.com{ } 134310259SAndrew.Bardsley@arm.com 134410259SAndrew.Bardsley@arm.comLSQ::LSQRequest::~LSQRequest() 134510259SAndrew.Bardsley@arm.com{ 134610259SAndrew.Bardsley@arm.com if (packet) 134710259SAndrew.Bardsley@arm.com delete packet; 134810259SAndrew.Bardsley@arm.com if (data) 134910259SAndrew.Bardsley@arm.com delete [] data; 135010259SAndrew.Bardsley@arm.com} 135110259SAndrew.Bardsley@arm.com 135210259SAndrew.Bardsley@arm.com/** 135310259SAndrew.Bardsley@arm.com * Step the memory access mechanism on to its next state. In reality, most 135410259SAndrew.Bardsley@arm.com * of the stepping is done by the callbacks on the LSQ but this 135510259SAndrew.Bardsley@arm.com * function is responsible for issuing memory requests lodged in the 135610259SAndrew.Bardsley@arm.com * requests queue. 135710259SAndrew.Bardsley@arm.com */ 135810259SAndrew.Bardsley@arm.comvoid 135910259SAndrew.Bardsley@arm.comLSQ::step() 136010259SAndrew.Bardsley@arm.com{ 136110259SAndrew.Bardsley@arm.com /* Try to move address-translated requests between queues and issue 136210259SAndrew.Bardsley@arm.com * them */ 136310259SAndrew.Bardsley@arm.com if (!requests.empty()) 136410259SAndrew.Bardsley@arm.com tryToSendToTransfers(requests.front()); 136510259SAndrew.Bardsley@arm.com 136610259SAndrew.Bardsley@arm.com storeBuffer.step(); 136710259SAndrew.Bardsley@arm.com} 136810259SAndrew.Bardsley@arm.com 136910259SAndrew.Bardsley@arm.comLSQ::LSQRequestPtr 137010259SAndrew.Bardsley@arm.comLSQ::findResponse(MinorDynInstPtr inst) 137110259SAndrew.Bardsley@arm.com{ 137210259SAndrew.Bardsley@arm.com LSQ::LSQRequestPtr ret = NULL; 137310259SAndrew.Bardsley@arm.com 137410259SAndrew.Bardsley@arm.com if (!transfers.empty()) { 137510259SAndrew.Bardsley@arm.com LSQRequestPtr request = transfers.front(); 137610259SAndrew.Bardsley@arm.com 137710259SAndrew.Bardsley@arm.com /* Same instruction and complete access or a store that's 137810259SAndrew.Bardsley@arm.com * capable of being moved to the store buffer */ 137910259SAndrew.Bardsley@arm.com if (request->inst->id == inst->id) { 138010504SAndrew.Bardsley@arm.com bool complete = request->isComplete(); 138110504SAndrew.Bardsley@arm.com bool can_store = storeBuffer.canInsert(); 138210504SAndrew.Bardsley@arm.com bool to_store_buffer = request->state == 138310504SAndrew.Bardsley@arm.com LSQRequest::StoreToStoreBuffer; 138410504SAndrew.Bardsley@arm.com 138510504SAndrew.Bardsley@arm.com if ((complete && !(request->isBarrier() && !can_store)) || 138610504SAndrew.Bardsley@arm.com (to_store_buffer && can_store)) 138710259SAndrew.Bardsley@arm.com { 138810259SAndrew.Bardsley@arm.com ret = request; 138910259SAndrew.Bardsley@arm.com } 139010259SAndrew.Bardsley@arm.com } 139110259SAndrew.Bardsley@arm.com } 139210259SAndrew.Bardsley@arm.com 139310259SAndrew.Bardsley@arm.com if (ret) { 139410259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Found matching memory response for inst: %s\n", 139510259SAndrew.Bardsley@arm.com *inst); 139610259SAndrew.Bardsley@arm.com } else { 139710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "No matching memory response for inst: %s\n", 139810259SAndrew.Bardsley@arm.com *inst); 139910259SAndrew.Bardsley@arm.com } 140010259SAndrew.Bardsley@arm.com 140110259SAndrew.Bardsley@arm.com return ret; 140210259SAndrew.Bardsley@arm.com} 140310259SAndrew.Bardsley@arm.com 140410259SAndrew.Bardsley@arm.comvoid 140510259SAndrew.Bardsley@arm.comLSQ::popResponse(LSQ::LSQRequestPtr response) 140610259SAndrew.Bardsley@arm.com{ 140710259SAndrew.Bardsley@arm.com assert(!transfers.empty() && transfers.front() == response); 140810259SAndrew.Bardsley@arm.com 140910259SAndrew.Bardsley@arm.com transfers.pop(); 141010259SAndrew.Bardsley@arm.com 141110259SAndrew.Bardsley@arm.com if (!response->isLoad) 141210259SAndrew.Bardsley@arm.com numStoresInTransfers--; 141310259SAndrew.Bardsley@arm.com 141410259SAndrew.Bardsley@arm.com if (response->issuedToMemory) 141510259SAndrew.Bardsley@arm.com numAccessesIssuedToMemory--; 141610259SAndrew.Bardsley@arm.com 141710259SAndrew.Bardsley@arm.com if (response->state != LSQRequest::StoreInStoreBuffer) { 141810259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Deleting %s request: %s\n", 141910259SAndrew.Bardsley@arm.com (response->isLoad ? "load" : "store"), 142010259SAndrew.Bardsley@arm.com *(response->inst)); 142110259SAndrew.Bardsley@arm.com 142210259SAndrew.Bardsley@arm.com delete response; 142310259SAndrew.Bardsley@arm.com } 142410259SAndrew.Bardsley@arm.com} 142510259SAndrew.Bardsley@arm.com 142610259SAndrew.Bardsley@arm.comvoid 142710259SAndrew.Bardsley@arm.comLSQ::sendStoreToStoreBuffer(LSQRequestPtr request) 142810259SAndrew.Bardsley@arm.com{ 142910259SAndrew.Bardsley@arm.com assert(request->state == LSQRequest::StoreToStoreBuffer); 143010259SAndrew.Bardsley@arm.com 143110259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Sending store: %s to store buffer\n", 143210259SAndrew.Bardsley@arm.com *(request->inst)); 143310259SAndrew.Bardsley@arm.com 143410259SAndrew.Bardsley@arm.com request->inst->inStoreBuffer = true; 143510259SAndrew.Bardsley@arm.com 143610259SAndrew.Bardsley@arm.com storeBuffer.insert(request); 143710259SAndrew.Bardsley@arm.com} 143810259SAndrew.Bardsley@arm.com 143910259SAndrew.Bardsley@arm.combool 144010259SAndrew.Bardsley@arm.comLSQ::isDrained() 144110259SAndrew.Bardsley@arm.com{ 144210259SAndrew.Bardsley@arm.com return requests.empty() && transfers.empty() && 144310259SAndrew.Bardsley@arm.com storeBuffer.isDrained(); 144410259SAndrew.Bardsley@arm.com} 144510259SAndrew.Bardsley@arm.com 144610259SAndrew.Bardsley@arm.combool 144710259SAndrew.Bardsley@arm.comLSQ::needsToTick() 144810259SAndrew.Bardsley@arm.com{ 144910259SAndrew.Bardsley@arm.com bool ret = false; 145010259SAndrew.Bardsley@arm.com 145110259SAndrew.Bardsley@arm.com if (canSendToMemorySystem()) { 145210259SAndrew.Bardsley@arm.com bool have_translated_requests = !requests.empty() && 145310259SAndrew.Bardsley@arm.com requests.front()->state != LSQRequest::InTranslation && 145410259SAndrew.Bardsley@arm.com transfers.unreservedRemainingSpace() != 0; 145510259SAndrew.Bardsley@arm.com 145610259SAndrew.Bardsley@arm.com ret = have_translated_requests || 145710259SAndrew.Bardsley@arm.com storeBuffer.numUnissuedStores() != 0; 145810259SAndrew.Bardsley@arm.com } 145910259SAndrew.Bardsley@arm.com 146010259SAndrew.Bardsley@arm.com if (ret) 146110259SAndrew.Bardsley@arm.com DPRINTF(Activity, "Need to tick\n"); 146210259SAndrew.Bardsley@arm.com 146310259SAndrew.Bardsley@arm.com return ret; 146410259SAndrew.Bardsley@arm.com} 146510259SAndrew.Bardsley@arm.com 146610259SAndrew.Bardsley@arm.comvoid 146710259SAndrew.Bardsley@arm.comLSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, 146810259SAndrew.Bardsley@arm.com unsigned int size, Addr addr, unsigned int flags, uint64_t *res) 146910259SAndrew.Bardsley@arm.com{ 147010259SAndrew.Bardsley@arm.com bool needs_burst = transferNeedsBurst(addr, size, lineWidth); 147110259SAndrew.Bardsley@arm.com LSQRequestPtr request; 147210259SAndrew.Bardsley@arm.com 147310259SAndrew.Bardsley@arm.com /* Copy given data into the request. The request will pass this to the 147410259SAndrew.Bardsley@arm.com * packet and then it will own the data */ 147510259SAndrew.Bardsley@arm.com uint8_t *request_data = NULL; 147610259SAndrew.Bardsley@arm.com 147710259SAndrew.Bardsley@arm.com DPRINTF(MinorMem, "Pushing request (%s) addr: 0x%x size: %d flags:" 147810259SAndrew.Bardsley@arm.com " 0x%x%s lineWidth : 0x%x\n", 147910259SAndrew.Bardsley@arm.com (isLoad ? "load" : "store"), addr, size, flags, 148010259SAndrew.Bardsley@arm.com (needs_burst ? " (needs burst)" : ""), lineWidth); 148110259SAndrew.Bardsley@arm.com 148210259SAndrew.Bardsley@arm.com if (!isLoad) { 148310259SAndrew.Bardsley@arm.com /* request_data becomes the property of a ...DataRequest (see below) 148410259SAndrew.Bardsley@arm.com * and destroyed by its destructor */ 148510259SAndrew.Bardsley@arm.com request_data = new uint8_t[size]; 148610259SAndrew.Bardsley@arm.com if (flags & Request::CACHE_BLOCK_ZERO) { 148710259SAndrew.Bardsley@arm.com /* For cache zeroing, just use zeroed data */ 148810259SAndrew.Bardsley@arm.com std::memset(request_data, 0, size); 148910259SAndrew.Bardsley@arm.com } else { 149010259SAndrew.Bardsley@arm.com std::memcpy(request_data, data, size); 149110259SAndrew.Bardsley@arm.com } 149210259SAndrew.Bardsley@arm.com } 149310259SAndrew.Bardsley@arm.com 149410259SAndrew.Bardsley@arm.com if (needs_burst) { 149510259SAndrew.Bardsley@arm.com request = new SplitDataRequest( 149610259SAndrew.Bardsley@arm.com *this, inst, isLoad, request_data, res); 149710259SAndrew.Bardsley@arm.com } else { 149810259SAndrew.Bardsley@arm.com request = new SingleDataRequest( 149910259SAndrew.Bardsley@arm.com *this, inst, isLoad, request_data, res); 150010259SAndrew.Bardsley@arm.com } 150110259SAndrew.Bardsley@arm.com 150210259SAndrew.Bardsley@arm.com if (inst->traceData) 150310665SAli.Saidi@ARM.com inst->traceData->setMem(addr, size, flags); 150410259SAndrew.Bardsley@arm.com 150511148Smitch.hayenga@arm.com int cid = cpu.threads[inst->id.threadId]->getTC()->contextId(); 150611435Smitch.hayenga@arm.com request->request.setContext(cid); 150710259SAndrew.Bardsley@arm.com request->request.setVirt(0 /* asid */, 150810634Slukefahr@umich.edu addr, size, flags, cpu.dataMasterId(), 150910259SAndrew.Bardsley@arm.com /* I've no idea why we need the PC, but give it */ 151010259SAndrew.Bardsley@arm.com inst->pc.instAddr()); 151110259SAndrew.Bardsley@arm.com 151210259SAndrew.Bardsley@arm.com requests.push(request); 151310259SAndrew.Bardsley@arm.com request->startAddrTranslation(); 151410259SAndrew.Bardsley@arm.com} 151510259SAndrew.Bardsley@arm.com 151610259SAndrew.Bardsley@arm.comvoid 151710259SAndrew.Bardsley@arm.comLSQ::pushFailedRequest(MinorDynInstPtr inst) 151810259SAndrew.Bardsley@arm.com{ 151910259SAndrew.Bardsley@arm.com LSQRequestPtr request = new FailedDataRequest(*this, inst); 152010259SAndrew.Bardsley@arm.com requests.push(request); 152110259SAndrew.Bardsley@arm.com} 152210259SAndrew.Bardsley@arm.com 152310259SAndrew.Bardsley@arm.comvoid 152410259SAndrew.Bardsley@arm.comLSQ::minorTrace() const 152510259SAndrew.Bardsley@arm.com{ 152610259SAndrew.Bardsley@arm.com MINORTRACE("state=%s in_tlb_mem=%d/%d stores_in_transfers=%d" 152710259SAndrew.Bardsley@arm.com " lastMemBarrier=%d\n", 152810259SAndrew.Bardsley@arm.com state, numAccessesInDTLB, numAccessesInMemorySystem, 152910259SAndrew.Bardsley@arm.com numStoresInTransfers, lastMemBarrier); 153010259SAndrew.Bardsley@arm.com requests.minorTrace(); 153110259SAndrew.Bardsley@arm.com transfers.minorTrace(); 153210259SAndrew.Bardsley@arm.com storeBuffer.minorTrace(); 153310259SAndrew.Bardsley@arm.com} 153410259SAndrew.Bardsley@arm.com 153510259SAndrew.Bardsley@arm.comLSQ::StoreBuffer::StoreBuffer(std::string name_, LSQ &lsq_, 153610259SAndrew.Bardsley@arm.com unsigned int store_buffer_size, 153710259SAndrew.Bardsley@arm.com unsigned int store_limit_per_cycle) : 153810259SAndrew.Bardsley@arm.com Named(name_), lsq(lsq_), 153910259SAndrew.Bardsley@arm.com numSlots(store_buffer_size), 154010259SAndrew.Bardsley@arm.com storeLimitPerCycle(store_limit_per_cycle), 154110259SAndrew.Bardsley@arm.com slots(), 154210259SAndrew.Bardsley@arm.com numUnissuedAccesses(0) 154310259SAndrew.Bardsley@arm.com{ 154410259SAndrew.Bardsley@arm.com} 154510259SAndrew.Bardsley@arm.com 154610259SAndrew.Bardsley@arm.comPacketPtr 154710259SAndrew.Bardsley@arm.commakePacketForRequest(Request &request, bool isLoad, 154810259SAndrew.Bardsley@arm.com Packet::SenderState *sender_state, PacketDataPtr data) 154910259SAndrew.Bardsley@arm.com{ 155010739Ssteve.reinhardt@amd.com PacketPtr ret = isLoad ? Packet::createRead(&request) 155110739Ssteve.reinhardt@amd.com : Packet::createWrite(&request); 155210259SAndrew.Bardsley@arm.com 155310259SAndrew.Bardsley@arm.com if (sender_state) 155410259SAndrew.Bardsley@arm.com ret->pushSenderState(sender_state); 155510259SAndrew.Bardsley@arm.com 155610259SAndrew.Bardsley@arm.com if (isLoad) 155710259SAndrew.Bardsley@arm.com ret->allocate(); 155810259SAndrew.Bardsley@arm.com else 155910566Sandreas.hansson@arm.com ret->dataDynamic(data); 156010259SAndrew.Bardsley@arm.com 156110259SAndrew.Bardsley@arm.com return ret; 156210259SAndrew.Bardsley@arm.com} 156310259SAndrew.Bardsley@arm.com 156410259SAndrew.Bardsley@arm.comvoid 156510259SAndrew.Bardsley@arm.comLSQ::issuedMemBarrierInst(MinorDynInstPtr inst) 156610259SAndrew.Bardsley@arm.com{ 156710259SAndrew.Bardsley@arm.com assert(inst->isInst() && inst->staticInst->isMemBarrier()); 156810259SAndrew.Bardsley@arm.com assert(inst->id.execSeqNum > lastMemBarrier); 156910259SAndrew.Bardsley@arm.com 157010259SAndrew.Bardsley@arm.com /* Remember the barrier. We only have a notion of one 157110259SAndrew.Bardsley@arm.com * barrier so this may result in some mem refs being 157210259SAndrew.Bardsley@arm.com * delayed if they are between barriers */ 157310259SAndrew.Bardsley@arm.com lastMemBarrier = inst->id.execSeqNum; 157410259SAndrew.Bardsley@arm.com} 157510259SAndrew.Bardsley@arm.com 157610259SAndrew.Bardsley@arm.comvoid 157710259SAndrew.Bardsley@arm.comLSQ::LSQRequest::makePacket() 157810259SAndrew.Bardsley@arm.com{ 157910259SAndrew.Bardsley@arm.com /* Make the function idempotent */ 158010259SAndrew.Bardsley@arm.com if (packet) 158110259SAndrew.Bardsley@arm.com return; 158210259SAndrew.Bardsley@arm.com 158311056Sandreas.hansson@arm.com // if the translation faulted, do not create a packet 158411056Sandreas.hansson@arm.com if (fault != NoFault) { 158511056Sandreas.hansson@arm.com assert(packet == NULL); 158611056Sandreas.hansson@arm.com return; 158711056Sandreas.hansson@arm.com } 158811056Sandreas.hansson@arm.com 158910259SAndrew.Bardsley@arm.com packet = makePacketForRequest(request, isLoad, this, data); 159010259SAndrew.Bardsley@arm.com /* Null the ret data so we know not to deallocate it when the 159110259SAndrew.Bardsley@arm.com * ret is destroyed. The data now belongs to the ret and 159210259SAndrew.Bardsley@arm.com * the ret is responsible for its destruction */ 159310259SAndrew.Bardsley@arm.com data = NULL; 159410259SAndrew.Bardsley@arm.com} 159510259SAndrew.Bardsley@arm.com 159610259SAndrew.Bardsley@arm.comstd::ostream & 159710259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, LSQ::MemoryState state) 159810259SAndrew.Bardsley@arm.com{ 159910259SAndrew.Bardsley@arm.com switch (state) { 160010259SAndrew.Bardsley@arm.com case LSQ::MemoryRunning: 160110259SAndrew.Bardsley@arm.com os << "MemoryRunning"; 160210259SAndrew.Bardsley@arm.com break; 160310259SAndrew.Bardsley@arm.com case LSQ::MemoryNeedsRetry: 160410259SAndrew.Bardsley@arm.com os << "MemoryNeedsRetry"; 160510259SAndrew.Bardsley@arm.com break; 160610259SAndrew.Bardsley@arm.com default: 160710259SAndrew.Bardsley@arm.com os << "MemoryState-" << static_cast<int>(state); 160810259SAndrew.Bardsley@arm.com break; 160910259SAndrew.Bardsley@arm.com } 161010259SAndrew.Bardsley@arm.com return os; 161110259SAndrew.Bardsley@arm.com} 161210259SAndrew.Bardsley@arm.com 161310259SAndrew.Bardsley@arm.comvoid 161410259SAndrew.Bardsley@arm.comLSQ::recvTimingSnoopReq(PacketPtr pkt) 161510259SAndrew.Bardsley@arm.com{ 161610259SAndrew.Bardsley@arm.com /* LLSC operations in Minor can't be speculative and are executed from 161710259SAndrew.Bardsley@arm.com * the head of the requests queue. We shouldn't need to do more than 161810259SAndrew.Bardsley@arm.com * this action on snoops. */ 161910259SAndrew.Bardsley@arm.com 162010259SAndrew.Bardsley@arm.com /* THREAD */ 162111356Skrinat01@arm.com if (pkt->isInvalidate() || pkt->isWrite()) { 162211356Skrinat01@arm.com TheISA::handleLockedSnoop(cpu.getContext(0), pkt, cacheBlockMask); 162311356Skrinat01@arm.com } 162410259SAndrew.Bardsley@arm.com} 162510259SAndrew.Bardsley@arm.com 162610259SAndrew.Bardsley@arm.com} 1627