fetch2.hh revision 13652:45d94ac03a27
114049Snikos.nikoleris@arm.com/* 28839Sandreas.hansson@arm.com * Copyright (c) 2013-2014 ARM Limited 38839Sandreas.hansson@arm.com * All rights reserved 48839Sandreas.hansson@arm.com * 58839Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68839Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78839Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88839Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98839Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108839Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118839Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128839Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 133101Sstever@eecs.umich.edu * 148579Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 153101Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 163101Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 173101Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 183101Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 193101Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 203101Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 213101Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 223101Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 233101Sstever@eecs.umich.edu * this software without specific prior written permission. 243101Sstever@eecs.umich.edu * 253101Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 263101Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 273101Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 283101Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 293101Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 303101Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 313101Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 323101Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 333101Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 343101Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 353101Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 363101Sstever@eecs.umich.edu * 373101Sstever@eecs.umich.edu * Authors: Andrew Bardsley 383101Sstever@eecs.umich.edu */ 393101Sstever@eecs.umich.edu 403101Sstever@eecs.umich.edu/** 413101Sstever@eecs.umich.edu * @file 427778Sgblack@eecs.umich.edu * 438839Sandreas.hansson@arm.com * Fetch2 receives lines of data from Fetch1, separates them into 443101Sstever@eecs.umich.edu * instructions and passes them to Decode 453101Sstever@eecs.umich.edu */ 463101Sstever@eecs.umich.edu 473101Sstever@eecs.umich.edu#ifndef __CPU_MINOR_FETCH2_HH__ 483101Sstever@eecs.umich.edu#define __CPU_MINOR_FETCH2_HH__ 493101Sstever@eecs.umich.edu 503101Sstever@eecs.umich.edu#include "cpu/minor/buffers.hh" 513101Sstever@eecs.umich.edu#include "cpu/minor/cpu.hh" 523101Sstever@eecs.umich.edu#include "cpu/minor/pipe_data.hh" 533101Sstever@eecs.umich.edu#include "cpu/pred/bpred_unit.hh" 543101Sstever@eecs.umich.edu#include "params/MinorCPU.hh" 553101Sstever@eecs.umich.edu 563101Sstever@eecs.umich.edunamespace Minor 573101Sstever@eecs.umich.edu{ 583101Sstever@eecs.umich.edu 593101Sstever@eecs.umich.edu/** This stage receives lines of data from Fetch1, separates them into 603101Sstever@eecs.umich.edu * instructions and passes them to Decode */ 613101Sstever@eecs.umich.educlass Fetch2 : public Named 6212563Sgabeblack@google.com{ 6313719Sandreas.sandberg@arm.com protected: 6413719Sandreas.sandberg@arm.com /** Pointer back to the containing CPU */ 6513719Sandreas.sandberg@arm.com MinorCPU &cpu; 6612563Sgabeblack@google.com 673885Sbinkertn@umich.edu /** Input port carrying lines from Fetch1 */ 683885Sbinkertn@umich.edu Latch<ForwardLineData>::Output inp; 694762Snate@binkert.org 703885Sbinkertn@umich.edu /** Input port carrying branches from Execute. This is a snoop of the 713885Sbinkertn@umich.edu * data provided to F1. */ 727528Ssteve.reinhardt@amd.com Latch<BranchData>::Output branchInp; 733885Sbinkertn@umich.edu 7413714Sandreas.sandberg@arm.com /** Output port carrying predictions back to Fetch1 */ 7513714Sandreas.sandberg@arm.com Latch<BranchData>::Input predictionOut; 7613714Sandreas.sandberg@arm.com 773101Sstever@eecs.umich.edu /** Output port carrying instructions into Decode */ 784762Snate@binkert.org Latch<ForwardInstData>::Input out; 7913716Sandreas.sandberg@arm.com 804762Snate@binkert.org /** Interface to reserve space in the next stage */ 814762Snate@binkert.org std::vector<InputBuffer<ForwardInstData>> &nextStageReserve; 824762Snate@binkert.org 8313716Sandreas.sandberg@arm.com /** Width of output of this stage/input of next in instructions */ 844762Snate@binkert.org unsigned int outputWidth; 854762Snate@binkert.org 864762Snate@binkert.org /** If true, more than one input word can be processed each cycle if 8713716Sandreas.sandberg@arm.com * there is room in the output to contain its processed data */ 884762Snate@binkert.org bool processMoreThanOneInput; 894762Snate@binkert.org 905033Smilesck@eecs.umich.edu /** Branch predictor passed from Python configuration */ 915033Smilesck@eecs.umich.edu BPredUnit &branchPredictor; 925033Smilesck@eecs.umich.edu 935033Smilesck@eecs.umich.edu public: 945033Smilesck@eecs.umich.edu /* Public so that Pipeline can pass it to Fetch1 */ 955033Smilesck@eecs.umich.edu std::vector<InputBuffer<ForwardLineData>> inputBuffer; 965033Smilesck@eecs.umich.edu 975033Smilesck@eecs.umich.edu protected: 985033Smilesck@eecs.umich.edu /** Data members after this line are cycle-to-cycle state */ 995033Smilesck@eecs.umich.edu 1003101Sstever@eecs.umich.edu struct Fetch2ThreadInfo { 1013101Sstever@eecs.umich.edu 1023101Sstever@eecs.umich.edu /** Default constructor */ 1035033Smilesck@eecs.umich.edu Fetch2ThreadInfo() : 10410267SGeoffrey.Blake@arm.com inputIndex(0), 1058596Ssteve.reinhardt@amd.com pc(TheISA::PCState(0)), 1068596Ssteve.reinhardt@amd.com havePC(false), 1078596Ssteve.reinhardt@amd.com lastStreamSeqNum(InstId::firstStreamSeqNum), 1088596Ssteve.reinhardt@amd.com fetchSeqNum(InstId::firstFetchSeqNum), 1097673Snate@binkert.org expectedStreamSeqNum(InstId::firstStreamSeqNum), 1107673Snate@binkert.org predictionSeqNum(InstId::firstPredictionSeqNum), 1117673Snate@binkert.org blocked(false) 1127673Snate@binkert.org { } 11311988Sandreas.sandberg@arm.com 11411988Sandreas.sandberg@arm.com Fetch2ThreadInfo(const Fetch2ThreadInfo& other) : 11511988Sandreas.sandberg@arm.com inputIndex(other.inputIndex), 11611988Sandreas.sandberg@arm.com pc(other.pc), 1173101Sstever@eecs.umich.edu havePC(other.havePC), 1183101Sstever@eecs.umich.edu lastStreamSeqNum(other.lastStreamSeqNum), 1193101Sstever@eecs.umich.edu expectedStreamSeqNum(other.expectedStreamSeqNum), 1203101Sstever@eecs.umich.edu predictionSeqNum(other.predictionSeqNum), 1213101Sstever@eecs.umich.edu blocked(other.blocked) 12210380SAndrew.Bardsley@arm.com { } 12310380SAndrew.Bardsley@arm.com 12410380SAndrew.Bardsley@arm.com /** Index into an incompletely processed input line that instructions 12510380SAndrew.Bardsley@arm.com * are to be extracted from */ 12610380SAndrew.Bardsley@arm.com unsigned int inputIndex; 12710380SAndrew.Bardsley@arm.com 12810458Sandreas.hansson@arm.com 12910458Sandreas.hansson@arm.com /** Remembered program counter value. Between contiguous lines, this 13010458Sandreas.hansson@arm.com * is just updated with advancePC. For lines following changes of 13110458Sandreas.hansson@arm.com * stream, a new PC must be loaded and havePC be set. 13210458Sandreas.hansson@arm.com * havePC is needed to accomodate instructions which span across 13310458Sandreas.hansson@arm.com * lines meaning that Fetch2 and the decoder need to remember a PC 13410458Sandreas.hansson@arm.com * value and a partially-offered instruction from the previous line */ 13510458Sandreas.hansson@arm.com TheISA::PCState pc; 13610458Sandreas.hansson@arm.com 13710458Sandreas.hansson@arm.com /** PC is currently valid. Initially false, gets set to true when a 13810458Sandreas.hansson@arm.com * change-of-stream line is received and false again when lines are 13910458Sandreas.hansson@arm.com * discarded for any reason */ 1403101Sstever@eecs.umich.edu bool havePC; 1413101Sstever@eecs.umich.edu 1423101Sstever@eecs.umich.edu /** Stream sequence number of the last seen line used to identify 1433101Sstever@eecs.umich.edu * changes of instruction stream */ 1443101Sstever@eecs.umich.edu InstSeqNum lastStreamSeqNum; 14510267SGeoffrey.Blake@arm.com 14610267SGeoffrey.Blake@arm.com /** Fetch2 is the source of fetch sequence numbers. These represent the 14710267SGeoffrey.Blake@arm.com * sequence that instructions were extracted from fetched lines. */ 14810267SGeoffrey.Blake@arm.com InstSeqNum fetchSeqNum; 1493101Sstever@eecs.umich.edu 1503101Sstever@eecs.umich.edu /** Stream sequence number remembered from last time the 1513101Sstever@eecs.umich.edu * predictionSeqNum changed. Lines should only be discarded when their 1523101Sstever@eecs.umich.edu * predictionSeqNums disagree with Fetch2::predictionSeqNum *and* they 1533101Sstever@eecs.umich.edu * are from the same stream that bore that prediction number */ 1543101Sstever@eecs.umich.edu InstSeqNum expectedStreamSeqNum; 1553101Sstever@eecs.umich.edu 1563101Sstever@eecs.umich.edu /** Fetch2 is the source of prediction sequence numbers. These 1573101Sstever@eecs.umich.edu * represent predicted changes of control flow sources from branch 1583101Sstever@eecs.umich.edu * prediction in Fetch2. */ 1593101Sstever@eecs.umich.edu InstSeqNum predictionSeqNum; 1603101Sstever@eecs.umich.edu 1613101Sstever@eecs.umich.edu /** Blocked indication for report */ 1623101Sstever@eecs.umich.edu bool blocked; 1633101Sstever@eecs.umich.edu }; 16413663Sandreas.sandberg@arm.com 1653101Sstever@eecs.umich.edu std::vector<Fetch2ThreadInfo> fetchInfo; 16613675Sandreas.sandberg@arm.com ThreadID threadPriority; 1673101Sstever@eecs.umich.edu 1683101Sstever@eecs.umich.edu /** Stats */ 1693101Sstever@eecs.umich.edu Stats::Scalar intInstructions; 1703101Sstever@eecs.umich.edu Stats::Scalar fpInstructions; 17113675Sandreas.sandberg@arm.com Stats::Scalar vecInstructions; 1723101Sstever@eecs.umich.edu Stats::Scalar loadInstructions; 1733101Sstever@eecs.umich.edu Stats::Scalar storeInstructions; 1743101Sstever@eecs.umich.edu Stats::Scalar amoInstructions; 1753101Sstever@eecs.umich.edu 1763101Sstever@eecs.umich.edu public: 17713663Sandreas.sandberg@arm.com /** Dump the whole contents of the input buffer. Useful after a 1783101Sstever@eecs.umich.edu * prediction changes control flow */ 1793101Sstever@eecs.umich.edu void dumpAllInput(ThreadID tid); 18013663Sandreas.sandberg@arm.com 1813101Sstever@eecs.umich.edu protected: 1823101Sstever@eecs.umich.edu /** Get a piece of data to work on from the inputBuffer, or 0 if there 1833101Sstever@eecs.umich.edu * is no data. */ 18413716Sandreas.sandberg@arm.com const ForwardLineData *getInput(ThreadID tid); 1855033Smilesck@eecs.umich.edu 1866656Snate@binkert.org /** Pop an element off the input buffer, if there are any */ 1875033Smilesck@eecs.umich.edu void popInput(ThreadID tid); 1885033Smilesck@eecs.umich.edu 1895033Smilesck@eecs.umich.edu /** Update local branch prediction structures from feedback from 19013663Sandreas.sandberg@arm.com * Execute. */ 19113663Sandreas.sandberg@arm.com void updateBranchPrediction(const BranchData &branch); 1923101Sstever@eecs.umich.edu 19310267SGeoffrey.Blake@arm.com /** Predicts branches for the given instruction. Updates the 19410267SGeoffrey.Blake@arm.com * instruction's predicted... fields and also the branch which 19510267SGeoffrey.Blake@arm.com * carries the prediction to Fetch1 */ 19610267SGeoffrey.Blake@arm.com void predictBranch(MinorDynInstPtr inst, BranchData &branch); 19710267SGeoffrey.Blake@arm.com 19810267SGeoffrey.Blake@arm.com /** Use the current threading policy to determine the next thread to 19910267SGeoffrey.Blake@arm.com * fetch from. */ 20010267SGeoffrey.Blake@arm.com ThreadID getScheduledThread(); 20110267SGeoffrey.Blake@arm.com 20210267SGeoffrey.Blake@arm.com public: 20310267SGeoffrey.Blake@arm.com Fetch2(const std::string &name, 20410267SGeoffrey.Blake@arm.com MinorCPU &cpu_, 20510267SGeoffrey.Blake@arm.com MinorCPUParams ¶ms, 2063101Sstever@eecs.umich.edu Latch<ForwardLineData>::Output inp_, 2073101Sstever@eecs.umich.edu Latch<BranchData>::Output branchInp_, 2083101Sstever@eecs.umich.edu Latch<BranchData>::Input predictionOut_, 2093101Sstever@eecs.umich.edu Latch<ForwardInstData>::Input out_, 21013699Sandreas.sandberg@arm.com std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer); 2113101Sstever@eecs.umich.edu 2123101Sstever@eecs.umich.edu public: 2133101Sstever@eecs.umich.edu /** Pass on input/buffer data to the output if you can */ 2143101Sstever@eecs.umich.edu void evaluate(); 2153101Sstever@eecs.umich.edu 2163102Sstever@eecs.umich.edu void minorTrace() const; 2173101Sstever@eecs.umich.edu 2183101Sstever@eecs.umich.edu void regStats(); 2193101Sstever@eecs.umich.edu 22010267SGeoffrey.Blake@arm.com /** Is this stage drained? For Fetch2, draining is initiated by 22110267SGeoffrey.Blake@arm.com * Execute halting Fetch1 causing Fetch2 to naturally drain. 22210267SGeoffrey.Blake@arm.com * Branch predictions are ignored by Fetch1 during halt */ 22310267SGeoffrey.Blake@arm.com bool isDrained(); 22410267SGeoffrey.Blake@arm.com}; 22510267SGeoffrey.Blake@arm.com 22610267SGeoffrey.Blake@arm.com} 2277673Snate@binkert.org 2288607Sgblack@eecs.umich.edu#endif /* __CPU_MINOR_FETCH2_HH__ */ 2297673Snate@binkert.org