execute.cc revision 13966
1/* 2 * Copyright (c) 2013-2014,2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andrew Bardsley 38 */ 39 40#include "cpu/minor/execute.hh" 41 42#include "arch/locked_mem.hh" 43#include "arch/registers.hh" 44#include "arch/utility.hh" 45#include "cpu/minor/cpu.hh" 46#include "cpu/minor/exec_context.hh" 47#include "cpu/minor/fetch1.hh" 48#include "cpu/minor/lsq.hh" 49#include "cpu/op_class.hh" 50#include "debug/Activity.hh" 51#include "debug/Branch.hh" 52#include "debug/Drain.hh" 53#include "debug/MinorExecute.hh" 54#include "debug/MinorInterrupt.hh" 55#include "debug/MinorMem.hh" 56#include "debug/MinorTrace.hh" 57#include "debug/PCEvent.hh" 58 59namespace Minor 60{ 61 62Execute::Execute(const std::string &name_, 63 MinorCPU &cpu_, 64 MinorCPUParams ¶ms, 65 Latch<ForwardInstData>::Output inp_, 66 Latch<BranchData>::Input out_) : 67 Named(name_), 68 inp(inp_), 69 out(out_), 70 cpu(cpu_), 71 issueLimit(params.executeIssueLimit), 72 memoryIssueLimit(params.executeMemoryIssueLimit), 73 commitLimit(params.executeCommitLimit), 74 memoryCommitLimit(params.executeMemoryCommitLimit), 75 processMoreThanOneInput(params.executeCycleInput), 76 fuDescriptions(*params.executeFuncUnits), 77 numFuncUnits(fuDescriptions.funcUnits.size()), 78 setTraceTimeOnCommit(params.executeSetTraceTimeOnCommit), 79 setTraceTimeOnIssue(params.executeSetTraceTimeOnIssue), 80 allowEarlyMemIssue(params.executeAllowEarlyMemoryIssue), 81 noCostFUIndex(fuDescriptions.funcUnits.size() + 1), 82 lsq(name_ + ".lsq", name_ + ".dcache_port", 83 cpu_, *this, 84 params.executeMaxAccessesInMemory, 85 params.executeMemoryWidth, 86 params.executeLSQRequestsQueueSize, 87 params.executeLSQTransfersQueueSize, 88 params.executeLSQStoreBufferSize, 89 params.executeLSQMaxStoreBufferStoresPerCycle), 90 executeInfo(params.numThreads, ExecuteThreadInfo(params.executeCommitLimit)), 91 interruptPriority(0), 92 issuePriority(0), 93 commitPriority(0) 94{ 95 if (commitLimit < 1) { 96 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_, 97 commitLimit); 98 } 99 100 if (issueLimit < 1) { 101 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_, 102 issueLimit); 103 } 104 105 if (memoryIssueLimit < 1) { 106 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_, 107 memoryIssueLimit); 108 } 109 110 if (memoryCommitLimit > commitLimit) { 111 fatal("%s: executeMemoryCommitLimit (%d) must be <=" 112 " executeCommitLimit (%d)\n", 113 name_, memoryCommitLimit, commitLimit); 114 } 115 116 if (params.executeInputBufferSize < 1) { 117 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_, 118 params.executeInputBufferSize); 119 } 120 121 if (params.executeInputBufferSize < 1) { 122 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_, 123 params.executeInputBufferSize); 124 } 125 126 /* This should be large enough to count all the in-FU instructions 127 * which need to be accounted for in the inFlightInsts 128 * queue */ 129 unsigned int total_slots = 0; 130 131 /* Make FUPipelines for each MinorFU */ 132 for (unsigned int i = 0; i < numFuncUnits; i++) { 133 std::ostringstream fu_name; 134 MinorFU *fu_description = fuDescriptions.funcUnits[i]; 135 136 /* Note the total number of instruction slots (for sizing 137 * the inFlightInst queue) and the maximum latency of any FU 138 * (for sizing the activity recorder) */ 139 total_slots += fu_description->opLat; 140 141 fu_name << name_ << ".fu." << i; 142 143 FUPipeline *fu = new FUPipeline(fu_name.str(), *fu_description, cpu); 144 145 funcUnits.push_back(fu); 146 } 147 148 /** Check that there is a functional unit for all operation classes */ 149 for (int op_class = No_OpClass + 1; op_class < Num_OpClasses; op_class++) { 150 bool found_fu = false; 151 unsigned int fu_index = 0; 152 153 while (fu_index < numFuncUnits && !found_fu) 154 { 155 if (funcUnits[fu_index]->provides( 156 static_cast<OpClass>(op_class))) 157 { 158 found_fu = true; 159 } 160 fu_index++; 161 } 162 163 if (!found_fu) { 164 warn("No functional unit for OpClass %s\n", 165 Enums::OpClassStrings[op_class]); 166 } 167 } 168 169 /* Per-thread structures */ 170 for (ThreadID tid = 0; tid < params.numThreads; tid++) { 171 std::string tid_str = std::to_string(tid); 172 173 /* Input Buffers */ 174 inputBuffer.push_back( 175 InputBuffer<ForwardInstData>( 176 name_ + ".inputBuffer" + tid_str, "insts", 177 params.executeInputBufferSize)); 178 179 /* Scoreboards */ 180 scoreboard.push_back(Scoreboard(name_ + ".scoreboard" + tid_str)); 181 182 /* In-flight instruction records */ 183 executeInfo[tid].inFlightInsts = new Queue<QueuedInst, 184 ReportTraitsAdaptor<QueuedInst> >( 185 name_ + ".inFlightInsts" + tid_str, "insts", total_slots); 186 187 executeInfo[tid].inFUMemInsts = new Queue<QueuedInst, 188 ReportTraitsAdaptor<QueuedInst> >( 189 name_ + ".inFUMemInsts" + tid_str, "insts", total_slots); 190 } 191} 192 193const ForwardInstData * 194Execute::getInput(ThreadID tid) 195{ 196 /* Get a line from the inputBuffer to work with */ 197 if (!inputBuffer[tid].empty()) { 198 const ForwardInstData &head = inputBuffer[tid].front(); 199 200 return (head.isBubble() ? NULL : &(inputBuffer[tid].front())); 201 } else { 202 return NULL; 203 } 204} 205 206void 207Execute::popInput(ThreadID tid) 208{ 209 if (!inputBuffer[tid].empty()) 210 inputBuffer[tid].pop(); 211 212 executeInfo[tid].inputIndex = 0; 213} 214 215void 216Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch) 217{ 218 ThreadContext *thread = cpu.getContext(inst->id.threadId); 219 const TheISA::PCState &pc_before = inst->pc; 220 TheISA::PCState target = thread->pcState(); 221 222 /* Force a branch for SerializeAfter/SquashAfter instructions 223 * at the end of micro-op sequence when we're not suspended */ 224 bool force_branch = thread->status() != ThreadContext::Suspended && 225 !inst->isFault() && 226 inst->isLastOpInInst() && 227 (inst->staticInst->isSerializeAfter() || 228 inst->staticInst->isSquashAfter() || 229 inst->staticInst->isIprAccess()); 230 231 DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n", 232 pc_before, target, (force_branch ? " (forcing)" : "")); 233 234 /* Will we change the PC to something other than the next instruction? */ 235 bool must_branch = pc_before != target || 236 fault != NoFault || 237 force_branch; 238 239 /* The reason for the branch data we're about to generate, set below */ 240 BranchData::Reason reason = BranchData::NoBranch; 241 242 if (fault == NoFault) 243 { 244 TheISA::advancePC(target, inst->staticInst); 245 thread->pcState(target); 246 247 DPRINTF(Branch, "Advancing current PC from: %s to: %s\n", 248 pc_before, target); 249 } 250 251 if (inst->predictedTaken && !force_branch) { 252 /* Predicted to branch */ 253 if (!must_branch) { 254 /* No branch was taken, change stream to get us back to the 255 * intended PC value */ 256 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x but" 257 " none happened inst: %s\n", 258 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst); 259 260 reason = BranchData::BadlyPredictedBranch; 261 } else if (inst->predictedTarget == target) { 262 /* Branch prediction got the right target, kill the branch and 263 * carry on. 264 * Note that this information to the branch predictor might get 265 * overwritten by a "real" branch during this cycle */ 266 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x correctly" 267 " inst: %s\n", 268 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst); 269 270 reason = BranchData::CorrectlyPredictedBranch; 271 } else { 272 /* Branch prediction got the wrong target */ 273 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x" 274 " but got the wrong target (actual: 0x%x) inst: %s\n", 275 inst->pc.instAddr(), inst->predictedTarget.instAddr(), 276 target.instAddr(), *inst); 277 278 reason = BranchData::BadlyPredictedBranchTarget; 279 } 280 } else if (must_branch) { 281 /* Unpredicted branch */ 282 DPRINTF(Branch, "Unpredicted branch from 0x%x to 0x%x inst: %s\n", 283 inst->pc.instAddr(), target.instAddr(), *inst); 284 285 reason = BranchData::UnpredictedBranch; 286 } else { 287 /* No branch at all */ 288 reason = BranchData::NoBranch; 289 } 290 291 updateBranchData(inst->id.threadId, reason, inst, target, branch); 292} 293 294void 295Execute::updateBranchData( 296 ThreadID tid, 297 BranchData::Reason reason, 298 MinorDynInstPtr inst, const TheISA::PCState &target, 299 BranchData &branch) 300{ 301 if (reason != BranchData::NoBranch) { 302 /* Bump up the stream sequence number on a real branch*/ 303 if (BranchData::isStreamChange(reason)) 304 executeInfo[tid].streamSeqNum++; 305 306 /* Branches (even mis-predictions) don't change the predictionSeqNum, 307 * just the streamSeqNum */ 308 branch = BranchData(reason, tid, 309 executeInfo[tid].streamSeqNum, 310 /* Maintaining predictionSeqNum if there's no inst is just a 311 * courtesy and looks better on minorview */ 312 (inst->isBubble() ? executeInfo[tid].lastPredictionSeqNum 313 : inst->id.predictionSeqNum), 314 target, inst); 315 316 DPRINTF(Branch, "Branch data signalled: %s\n", branch); 317 } 318} 319 320void 321Execute::handleMemResponse(MinorDynInstPtr inst, 322 LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault) 323{ 324 ThreadID thread_id = inst->id.threadId; 325 ThreadContext *thread = cpu.getContext(thread_id); 326 327 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst); 328 329 PacketPtr packet = response->packet; 330 331 bool is_load = inst->staticInst->isLoad(); 332 bool is_store = inst->staticInst->isStore(); 333 bool is_atomic = inst->staticInst->isAtomic(); 334 bool is_prefetch = inst->staticInst->isDataPrefetch(); 335 336 /* If true, the trace's predicate value will be taken from the exec 337 * context predicate, otherwise, it will be set to false */ 338 bool use_context_predicate = true; 339 340 if (response->fault != NoFault) { 341 /* Invoke memory faults. */ 342 DPRINTF(MinorMem, "Completing fault from DTLB access: %s\n", 343 response->fault->name()); 344 345 if (inst->staticInst->isPrefetch()) { 346 DPRINTF(MinorMem, "Not taking fault on prefetch: %s\n", 347 response->fault->name()); 348 349 /* Don't assign to fault */ 350 } else { 351 /* Take the fault raised during the TLB/memory access */ 352 fault = response->fault; 353 354 fault->invoke(thread, inst->staticInst); 355 } 356 } else if (!packet) { 357 DPRINTF(MinorMem, "Completing failed request inst: %s\n", 358 *inst); 359 use_context_predicate = false; 360 if (!context.readMemAccPredicate()) 361 inst->staticInst->completeAcc(nullptr, &context, inst->traceData); 362 } else if (packet->isError()) { 363 DPRINTF(MinorMem, "Trying to commit error response: %s\n", 364 *inst); 365 366 fatal("Received error response packet for inst: %s\n", *inst); 367 } else if (is_store || is_load || is_prefetch || is_atomic) { 368 assert(packet); 369 370 DPRINTF(MinorMem, "Memory response inst: %s addr: 0x%x size: %d\n", 371 *inst, packet->getAddr(), packet->getSize()); 372 373 if (is_load && packet->getSize() > 0) { 374 DPRINTF(MinorMem, "Memory data[0]: 0x%x\n", 375 static_cast<unsigned int>(packet->getConstPtr<uint8_t>()[0])); 376 } 377 378 /* Complete the memory access instruction */ 379 fault = inst->staticInst->completeAcc(packet, &context, 380 inst->traceData); 381 382 if (fault != NoFault) { 383 /* Invoke fault created by instruction completion */ 384 DPRINTF(MinorMem, "Fault in memory completeAcc: %s\n", 385 fault->name()); 386 fault->invoke(thread, inst->staticInst); 387 } else { 388 /* Stores need to be pushed into the store buffer to finish 389 * them off */ 390 if (response->needsToBeSentToStoreBuffer()) 391 lsq.sendStoreToStoreBuffer(response); 392 } 393 } else { 394 fatal("There should only ever be reads, " 395 "writes or faults at this point\n"); 396 } 397 398 lsq.popResponse(response); 399 400 if (inst->traceData) { 401 inst->traceData->setPredicate((use_context_predicate ? 402 context.readPredicate() : false)); 403 } 404 405 doInstCommitAccounting(inst); 406 407 /* Generate output to account for branches */ 408 tryToBranch(inst, fault, branch); 409} 410 411bool 412Execute::isInterrupted(ThreadID thread_id) const 413{ 414 return cpu.checkInterrupts(cpu.getContext(thread_id)); 415} 416 417bool 418Execute::takeInterrupt(ThreadID thread_id, BranchData &branch) 419{ 420 DPRINTF(MinorInterrupt, "Considering interrupt status from PC: %s\n", 421 cpu.getContext(thread_id)->pcState()); 422 423 Fault interrupt = cpu.getInterruptController(thread_id)->getInterrupt 424 (cpu.getContext(thread_id)); 425 426 if (interrupt != NoFault) { 427 /* The interrupt *must* set pcState */ 428 cpu.getInterruptController(thread_id)->updateIntrInfo 429 (cpu.getContext(thread_id)); 430 interrupt->invoke(cpu.getContext(thread_id)); 431 432 assert(!lsq.accessesInFlight()); 433 434 DPRINTF(MinorInterrupt, "Invoking interrupt: %s to PC: %s\n", 435 interrupt->name(), cpu.getContext(thread_id)->pcState()); 436 437 /* Assume that an interrupt *must* cause a branch. Assert this? */ 438 439 updateBranchData(thread_id, BranchData::Interrupt, 440 MinorDynInst::bubble(), cpu.getContext(thread_id)->pcState(), 441 branch); 442 } 443 444 return interrupt != NoFault; 445} 446 447bool 448Execute::executeMemRefInst(MinorDynInstPtr inst, BranchData &branch, 449 bool &passed_predicate, Fault &fault) 450{ 451 bool issued = false; 452 453 /* Set to true if the mem op. is issued and sent to the mem system */ 454 passed_predicate = false; 455 456 if (!lsq.canRequest()) { 457 /* Not acting on instruction yet as the memory 458 * queues are full */ 459 issued = false; 460 } else { 461 ThreadContext *thread = cpu.getContext(inst->id.threadId); 462 TheISA::PCState old_pc = thread->pcState(); 463 464 ExecContext context(cpu, *cpu.threads[inst->id.threadId], 465 *this, inst); 466 467 DPRINTF(MinorExecute, "Initiating memRef inst: %s\n", *inst); 468 469 Fault init_fault = inst->staticInst->initiateAcc(&context, 470 inst->traceData); 471 472 if (init_fault != NoFault) { 473 DPRINTF(MinorExecute, "Fault on memory inst: %s" 474 " initiateAcc: %s\n", *inst, init_fault->name()); 475 fault = init_fault; 476 } else { 477 /* Only set this if the instruction passed its 478 * predicate */ 479 if (!context.readMemAccPredicate()) { 480 DPRINTF(MinorMem, "No memory access for inst: %s\n", *inst); 481 assert(context.readPredicate()); 482 } 483 passed_predicate = context.readPredicate(); 484 485 /* Set predicate in tracing */ 486 if (inst->traceData) 487 inst->traceData->setPredicate(passed_predicate); 488 489 /* If the instruction didn't pass its predicate (and so will not 490 * progress from here) Try to branch to correct and branch 491 * mis-prediction. */ 492 if (!passed_predicate) { 493 /* Leave it up to commit to handle the fault */ 494 lsq.pushFailedRequest(inst); 495 } 496 } 497 498 /* Restore thread PC */ 499 thread->pcState(old_pc); 500 issued = true; 501 } 502 503 return issued; 504} 505 506/** Increment a cyclic buffer index for indices [0, cycle_size-1] */ 507inline unsigned int 508cyclicIndexInc(unsigned int index, unsigned int cycle_size) 509{ 510 unsigned int ret = index + 1; 511 512 if (ret == cycle_size) 513 ret = 0; 514 515 return ret; 516} 517 518/** Decrement a cyclic buffer index for indices [0, cycle_size-1] */ 519inline unsigned int 520cyclicIndexDec(unsigned int index, unsigned int cycle_size) 521{ 522 int ret = index - 1; 523 524 if (ret < 0) 525 ret = cycle_size - 1; 526 527 return ret; 528} 529 530unsigned int 531Execute::issue(ThreadID thread_id) 532{ 533 const ForwardInstData *insts_in = getInput(thread_id); 534 ExecuteThreadInfo &thread = executeInfo[thread_id]; 535 536 /* Early termination if we have no instructions */ 537 if (!insts_in) 538 return 0; 539 540 /* Start from the first FU */ 541 unsigned int fu_index = 0; 542 543 /* Remains true while instructions are still being issued. If any 544 * instruction fails to issue, this is set to false and we exit issue. 545 * This strictly enforces in-order issue. For other issue behaviours, 546 * a more complicated test in the outer while loop below is needed. */ 547 bool issued = true; 548 549 /* Number of insts issues this cycle to check for issueLimit */ 550 unsigned num_insts_issued = 0; 551 552 /* Number of memory ops issues this cycle to check for memoryIssueLimit */ 553 unsigned num_mem_insts_issued = 0; 554 555 /* Number of instructions discarded this cycle in order to enforce a 556 * discardLimit. @todo, add that parameter? */ 557 unsigned num_insts_discarded = 0; 558 559 do { 560 MinorDynInstPtr inst = insts_in->insts[thread.inputIndex]; 561 Fault fault = inst->fault; 562 bool discarded = false; 563 bool issued_mem_ref = false; 564 565 if (inst->isBubble()) { 566 /* Skip */ 567 issued = true; 568 } else if (cpu.getContext(thread_id)->status() == 569 ThreadContext::Suspended) 570 { 571 DPRINTF(MinorExecute, "Discarding inst: %s from suspended" 572 " thread\n", *inst); 573 574 issued = true; 575 discarded = true; 576 } else if (inst->id.streamSeqNum != thread.streamSeqNum) { 577 DPRINTF(MinorExecute, "Discarding inst: %s as its stream" 578 " state was unexpected, expected: %d\n", 579 *inst, thread.streamSeqNum); 580 issued = true; 581 discarded = true; 582 } else { 583 /* Try and issue an instruction into an FU, assume we didn't and 584 * fix that in the loop */ 585 issued = false; 586 587 /* Try FU from 0 each instruction */ 588 fu_index = 0; 589 590 /* Try and issue a single instruction stepping through the 591 * available FUs */ 592 do { 593 FUPipeline *fu = funcUnits[fu_index]; 594 595 DPRINTF(MinorExecute, "Trying to issue inst: %s to FU: %d\n", 596 *inst, fu_index); 597 598 /* Does the examined fu have the OpClass-related capability 599 * needed to execute this instruction? Faults can always 600 * issue to any FU but probably should just 'live' in the 601 * inFlightInsts queue rather than having an FU. */ 602 bool fu_is_capable = (!inst->isFault() ? 603 fu->provides(inst->staticInst->opClass()) : true); 604 605 if (inst->isNoCostInst()) { 606 /* Issue free insts. to a fake numbered FU */ 607 fu_index = noCostFUIndex; 608 609 /* And start the countdown on activity to allow 610 * this instruction to get to the end of its FU */ 611 cpu.activityRecorder->activity(); 612 613 /* Mark the destinations for this instruction as 614 * busy */ 615 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() + 616 Cycles(0), cpu.getContext(thread_id), false); 617 618 DPRINTF(MinorExecute, "Issuing %s to %d\n", inst->id, noCostFUIndex); 619 inst->fuIndex = noCostFUIndex; 620 inst->extraCommitDelay = Cycles(0); 621 inst->extraCommitDelayExpr = NULL; 622 623 /* Push the instruction onto the inFlight queue so 624 * it can be committed in order */ 625 QueuedInst fu_inst(inst); 626 thread.inFlightInsts->push(fu_inst); 627 628 issued = true; 629 630 } else if (!fu_is_capable || fu->alreadyPushed()) { 631 /* Skip */ 632 if (!fu_is_capable) { 633 DPRINTF(MinorExecute, "Can't issue as FU: %d isn't" 634 " capable\n", fu_index); 635 } else { 636 DPRINTF(MinorExecute, "Can't issue as FU: %d is" 637 " already busy\n", fu_index); 638 } 639 } else if (fu->stalled) { 640 DPRINTF(MinorExecute, "Can't issue inst: %s into FU: %d," 641 " it's stalled\n", 642 *inst, fu_index); 643 } else if (!fu->canInsert()) { 644 DPRINTF(MinorExecute, "Can't issue inst: %s to busy FU" 645 " for another: %d cycles\n", 646 *inst, fu->cyclesBeforeInsert()); 647 } else { 648 MinorFUTiming *timing = (!inst->isFault() ? 649 fu->findTiming(inst->staticInst) : NULL); 650 651 const std::vector<Cycles> *src_latencies = 652 (timing ? &(timing->srcRegsRelativeLats) 653 : NULL); 654 655 const std::vector<bool> *cant_forward_from_fu_indices = 656 &(fu->cantForwardFromFUIndices); 657 658 if (timing && timing->suppress) { 659 DPRINTF(MinorExecute, "Can't issue inst: %s as extra" 660 " decoding is suppressing it\n", 661 *inst); 662 } else if (!scoreboard[thread_id].canInstIssue(inst, 663 src_latencies, cant_forward_from_fu_indices, 664 cpu.curCycle(), cpu.getContext(thread_id))) 665 { 666 DPRINTF(MinorExecute, "Can't issue inst: %s yet\n", 667 *inst); 668 } else { 669 /* Can insert the instruction into this FU */ 670 DPRINTF(MinorExecute, "Issuing inst: %s" 671 " into FU %d\n", *inst, 672 fu_index); 673 674 Cycles extra_dest_retire_lat = Cycles(0); 675 TimingExpr *extra_dest_retire_lat_expr = NULL; 676 Cycles extra_assumed_lat = Cycles(0); 677 678 /* Add the extraCommitDelay and extraAssumeLat to 679 * the FU pipeline timings */ 680 if (timing) { 681 extra_dest_retire_lat = 682 timing->extraCommitLat; 683 extra_dest_retire_lat_expr = 684 timing->extraCommitLatExpr; 685 extra_assumed_lat = 686 timing->extraAssumedLat; 687 } 688 689 issued_mem_ref = inst->isMemRef(); 690 691 QueuedInst fu_inst(inst); 692 693 /* Decorate the inst with FU details */ 694 inst->fuIndex = fu_index; 695 inst->extraCommitDelay = extra_dest_retire_lat; 696 inst->extraCommitDelayExpr = 697 extra_dest_retire_lat_expr; 698 699 if (issued_mem_ref) { 700 /* Remember which instruction this memory op 701 * depends on so that initiateAcc can be called 702 * early */ 703 if (allowEarlyMemIssue) { 704 inst->instToWaitFor = 705 scoreboard[thread_id].execSeqNumToWaitFor(inst, 706 cpu.getContext(thread_id)); 707 708 if (lsq.getLastMemBarrier(thread_id) > 709 inst->instToWaitFor) 710 { 711 DPRINTF(MinorExecute, "A barrier will" 712 " cause a delay in mem ref issue of" 713 " inst: %s until after inst" 714 " %d(exec)\n", *inst, 715 lsq.getLastMemBarrier(thread_id)); 716 717 inst->instToWaitFor = 718 lsq.getLastMemBarrier(thread_id); 719 } else { 720 DPRINTF(MinorExecute, "Memory ref inst:" 721 " %s must wait for inst %d(exec)" 722 " before issuing\n", 723 *inst, inst->instToWaitFor); 724 } 725 726 inst->canEarlyIssue = true; 727 } 728 /* Also queue this instruction in the memory ref 729 * queue to ensure in-order issue to the LSQ */ 730 DPRINTF(MinorExecute, "Pushing mem inst: %s\n", 731 *inst); 732 thread.inFUMemInsts->push(fu_inst); 733 } 734 735 /* Issue to FU */ 736 fu->push(fu_inst); 737 /* And start the countdown on activity to allow 738 * this instruction to get to the end of its FU */ 739 cpu.activityRecorder->activity(); 740 741 /* Mark the destinations for this instruction as 742 * busy */ 743 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() + 744 fu->description.opLat + 745 extra_dest_retire_lat + 746 extra_assumed_lat, 747 cpu.getContext(thread_id), 748 issued_mem_ref && extra_assumed_lat == Cycles(0)); 749 750 /* Push the instruction onto the inFlight queue so 751 * it can be committed in order */ 752 thread.inFlightInsts->push(fu_inst); 753 754 issued = true; 755 } 756 } 757 758 fu_index++; 759 } while (fu_index != numFuncUnits && !issued); 760 761 if (!issued) 762 DPRINTF(MinorExecute, "Didn't issue inst: %s\n", *inst); 763 } 764 765 if (issued) { 766 /* Generate MinorTrace's MinorInst lines. Do this at commit 767 * to allow better instruction annotation? */ 768 if (DTRACE(MinorTrace) && !inst->isBubble()) 769 inst->minorTraceInst(*this); 770 771 /* Mark up barriers in the LSQ */ 772 if (!discarded && inst->isInst() && 773 inst->staticInst->isMemBarrier()) 774 { 775 DPRINTF(MinorMem, "Issuing memory barrier inst: %s\n", *inst); 776 lsq.issuedMemBarrierInst(inst); 777 } 778 779 if (inst->traceData && setTraceTimeOnIssue) { 780 inst->traceData->setWhen(curTick()); 781 } 782 783 if (issued_mem_ref) 784 num_mem_insts_issued++; 785 786 if (discarded) { 787 num_insts_discarded++; 788 } else if (!inst->isBubble()) { 789 num_insts_issued++; 790 791 if (num_insts_issued == issueLimit) 792 DPRINTF(MinorExecute, "Reached inst issue limit\n"); 793 } 794 795 thread.inputIndex++; 796 DPRINTF(MinorExecute, "Stepping to next inst inputIndex: %d\n", 797 thread.inputIndex); 798 } 799 800 /* Got to the end of a line */ 801 if (thread.inputIndex == insts_in->width()) { 802 popInput(thread_id); 803 /* Set insts_in to null to force us to leave the surrounding 804 * loop */ 805 insts_in = NULL; 806 807 if (processMoreThanOneInput) { 808 DPRINTF(MinorExecute, "Wrapping\n"); 809 insts_in = getInput(thread_id); 810 } 811 } 812 } while (insts_in && thread.inputIndex < insts_in->width() && 813 /* We still have instructions */ 814 fu_index != numFuncUnits && /* Not visited all FUs */ 815 issued && /* We've not yet failed to issue an instruction */ 816 num_insts_issued != issueLimit && /* Still allowed to issue */ 817 num_mem_insts_issued != memoryIssueLimit); 818 819 return num_insts_issued; 820} 821 822bool 823Execute::tryPCEvents(ThreadID thread_id) 824{ 825 ThreadContext *thread = cpu.getContext(thread_id); 826 unsigned int num_pc_event_checks = 0; 827 828 /* Handle PC events on instructions */ 829 Addr oldPC; 830 do { 831 oldPC = thread->instAddr(); 832 cpu.system->pcEventQueue.service(thread); 833 num_pc_event_checks++; 834 } while (oldPC != thread->instAddr()); 835 836 if (num_pc_event_checks > 1) { 837 DPRINTF(PCEvent, "Acting on PC Event to PC: %s\n", 838 thread->pcState()); 839 } 840 841 return num_pc_event_checks > 1; 842} 843 844void 845Execute::doInstCommitAccounting(MinorDynInstPtr inst) 846{ 847 assert(!inst->isFault()); 848 849 MinorThread *thread = cpu.threads[inst->id.threadId]; 850 851 /* Increment the many and various inst and op counts in the 852 * thread and system */ 853 if (!inst->staticInst->isMicroop() || inst->staticInst->isLastMicroop()) 854 { 855 thread->numInst++; 856 thread->numInsts++; 857 cpu.stats.numInsts++; 858 cpu.system->totalNumInsts++; 859 860 /* Act on events related to instruction counts */ 861 cpu.comInstEventQueue[inst->id.threadId]->serviceEvents(thread->numInst); 862 cpu.system->instEventQueue.serviceEvents(cpu.system->totalNumInsts); 863 } 864 thread->numOp++; 865 thread->numOps++; 866 cpu.stats.numOps++; 867 cpu.stats.committedInstType[inst->id.threadId] 868 [inst->staticInst->opClass()]++; 869 870 /* Set the CP SeqNum to the numOps commit number */ 871 if (inst->traceData) 872 inst->traceData->setCPSeq(thread->numOp); 873 874 cpu.probeInstCommit(inst->staticInst, inst->pc.instAddr()); 875} 876 877bool 878Execute::commitInst(MinorDynInstPtr inst, bool early_memory_issue, 879 BranchData &branch, Fault &fault, bool &committed, 880 bool &completed_mem_issue) 881{ 882 ThreadID thread_id = inst->id.threadId; 883 ThreadContext *thread = cpu.getContext(thread_id); 884 885 bool completed_inst = true; 886 fault = NoFault; 887 888 /* Is the thread for this instruction suspended? In that case, just 889 * stall as long as there are no pending interrupts */ 890 if (thread->status() == ThreadContext::Suspended && 891 !isInterrupted(thread_id)) 892 { 893 panic("We should never hit the case where we try to commit from a " 894 "suspended thread as the streamSeqNum should not match"); 895 } else if (inst->isFault()) { 896 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst); 897 898 DPRINTF(MinorExecute, "Fault inst reached Execute: %s\n", 899 inst->fault->name()); 900 901 fault = inst->fault; 902 inst->fault->invoke(thread, NULL); 903 904 tryToBranch(inst, fault, branch); 905 } else if (inst->staticInst->isMemRef()) { 906 /* Memory accesses are executed in two parts: 907 * executeMemRefInst -- calculates the EA and issues the access 908 * to memory. This is done here. 909 * handleMemResponse -- handles the response packet, done by 910 * Execute::commit 911 * 912 * While the memory access is in its FU, the EA is being 913 * calculated. At the end of the FU, when it is ready to 914 * 'commit' (in this function), the access is presented to the 915 * memory queues. When a response comes back from memory, 916 * Execute::commit will commit it. 917 */ 918 bool predicate_passed = false; 919 bool completed_mem_inst = executeMemRefInst(inst, branch, 920 predicate_passed, fault); 921 922 if (completed_mem_inst && fault != NoFault) { 923 if (early_memory_issue) { 924 DPRINTF(MinorExecute, "Fault in early executing inst: %s\n", 925 fault->name()); 926 /* Don't execute the fault, just stall the instruction 927 * until it gets to the head of inFlightInsts */ 928 inst->canEarlyIssue = false; 929 /* Not completed as we'll come here again to pick up 930 * the fault when we get to the end of the FU */ 931 completed_inst = false; 932 } else { 933 DPRINTF(MinorExecute, "Fault in execute: %s\n", 934 fault->name()); 935 fault->invoke(thread, NULL); 936 937 tryToBranch(inst, fault, branch); 938 completed_inst = true; 939 } 940 } else { 941 completed_inst = completed_mem_inst; 942 } 943 completed_mem_issue = completed_inst; 944 } else if (inst->isInst() && inst->staticInst->isMemBarrier() && 945 !lsq.canPushIntoStoreBuffer()) 946 { 947 DPRINTF(MinorExecute, "Can't commit data barrier inst: %s yet as" 948 " there isn't space in the store buffer\n", *inst); 949 950 completed_inst = false; 951 } else if (inst->isInst() && inst->staticInst->isQuiesce() 952 && !branch.isBubble()){ 953 /* This instruction can suspend, need to be able to communicate 954 * backwards, so no other branches may evaluate this cycle*/ 955 completed_inst = false; 956 } else { 957 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst); 958 959 DPRINTF(MinorExecute, "Committing inst: %s\n", *inst); 960 961 fault = inst->staticInst->execute(&context, 962 inst->traceData); 963 964 /* Set the predicate for tracing and dump */ 965 if (inst->traceData) 966 inst->traceData->setPredicate(context.readPredicate()); 967 968 committed = true; 969 970 if (fault != NoFault) { 971 DPRINTF(MinorExecute, "Fault in execute of inst: %s fault: %s\n", 972 *inst, fault->name()); 973 fault->invoke(thread, inst->staticInst); 974 } 975 976 doInstCommitAccounting(inst); 977 tryToBranch(inst, fault, branch); 978 } 979 980 if (completed_inst) { 981 /* Keep a copy of this instruction's predictionSeqNum just in case 982 * we need to issue a branch without an instruction (such as an 983 * interrupt) */ 984 executeInfo[thread_id].lastPredictionSeqNum = inst->id.predictionSeqNum; 985 986 /* Check to see if this instruction suspended the current thread. */ 987 if (!inst->isFault() && 988 thread->status() == ThreadContext::Suspended && 989 branch.isBubble() && /* It didn't branch too */ 990 !isInterrupted(thread_id)) /* Don't suspend if we have 991 interrupts */ 992 { 993 TheISA::PCState resume_pc = cpu.getContext(thread_id)->pcState(); 994 995 assert(resume_pc.microPC() == 0); 996 997 DPRINTF(MinorInterrupt, "Suspending thread: %d from Execute" 998 " inst: %s\n", thread_id, *inst); 999 1000 cpu.stats.numFetchSuspends++; 1001 1002 updateBranchData(thread_id, BranchData::SuspendThread, inst, 1003 resume_pc, branch); 1004 } 1005 } 1006 1007 return completed_inst; 1008} 1009 1010void 1011Execute::commit(ThreadID thread_id, bool only_commit_microops, bool discard, 1012 BranchData &branch) 1013{ 1014 Fault fault = NoFault; 1015 Cycles now = cpu.curCycle(); 1016 ExecuteThreadInfo &ex_info = executeInfo[thread_id]; 1017 1018 /** 1019 * Try and execute as many instructions from the end of FU pipelines as 1020 * possible. This *doesn't* include actually advancing the pipelines. 1021 * 1022 * We do this by looping on the front of the inFlightInsts queue for as 1023 * long as we can find the desired instruction at the end of the 1024 * functional unit it was issued to without seeing a branch or a fault. 1025 * In this function, these terms are used: 1026 * complete -- The instruction has finished its passage through 1027 * its functional unit and its fate has been decided 1028 * (committed, discarded, issued to the memory system) 1029 * commit -- The instruction is complete(d), not discarded and has 1030 * its effects applied to the CPU state 1031 * discard(ed) -- The instruction is complete but not committed 1032 * as its streamSeqNum disagrees with the current 1033 * Execute::streamSeqNum 1034 * 1035 * Commits are also possible from two other places: 1036 * 1037 * 1) Responses returning from the LSQ 1038 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier 1039 * than their position in the inFlightInsts queue, but after all 1040 * their dependencies are resolved. 1041 */ 1042 1043 /* Has an instruction been completed? Once this becomes false, we stop 1044 * trying to complete instructions. */ 1045 bool completed_inst = true; 1046 1047 /* Number of insts committed this cycle to check against commitLimit */ 1048 unsigned int num_insts_committed = 0; 1049 1050 /* Number of memory access instructions committed to check against 1051 * memCommitLimit */ 1052 unsigned int num_mem_refs_committed = 0; 1053 1054 if (only_commit_microops && !ex_info.inFlightInsts->empty()) { 1055 DPRINTF(MinorInterrupt, "Only commit microops %s %d\n", 1056 *(ex_info.inFlightInsts->front().inst), 1057 ex_info.lastCommitWasEndOfMacroop); 1058 } 1059 1060 while (!ex_info.inFlightInsts->empty() && /* Some more instructions to process */ 1061 !branch.isStreamChange() && /* No real branch */ 1062 fault == NoFault && /* No faults */ 1063 completed_inst && /* Still finding instructions to execute */ 1064 num_insts_committed != commitLimit /* Not reached commit limit */ 1065 ) 1066 { 1067 if (only_commit_microops) { 1068 DPRINTF(MinorInterrupt, "Committing tail of insts before" 1069 " interrupt: %s\n", 1070 *(ex_info.inFlightInsts->front().inst)); 1071 } 1072 1073 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front()); 1074 1075 InstSeqNum head_exec_seq_num = 1076 head_inflight_inst->inst->id.execSeqNum; 1077 1078 /* The instruction we actually process if completed_inst 1079 * remains true to the end of the loop body. 1080 * Start by considering the the head of the in flight insts queue */ 1081 MinorDynInstPtr inst = head_inflight_inst->inst; 1082 1083 bool committed_inst = false; 1084 bool discard_inst = false; 1085 bool completed_mem_ref = false; 1086 bool issued_mem_ref = false; 1087 bool early_memory_issue = false; 1088 1089 /* Must set this again to go around the loop */ 1090 completed_inst = false; 1091 1092 /* If we're just completing a macroop before an interrupt or drain, 1093 * can we stil commit another microop (rather than a memory response) 1094 * without crosing into the next full instruction? */ 1095 bool can_commit_insts = !ex_info.inFlightInsts->empty() && 1096 !(only_commit_microops && ex_info.lastCommitWasEndOfMacroop); 1097 1098 /* Can we find a mem response for this inst */ 1099 LSQ::LSQRequestPtr mem_response = 1100 (inst->inLSQ ? lsq.findResponse(inst) : NULL); 1101 1102 DPRINTF(MinorExecute, "Trying to commit canCommitInsts: %d\n", 1103 can_commit_insts); 1104 1105 /* Test for PC events after every instruction */ 1106 if (isInbetweenInsts(thread_id) && tryPCEvents(thread_id)) { 1107 ThreadContext *thread = cpu.getContext(thread_id); 1108 1109 /* Branch as there was a change in PC */ 1110 updateBranchData(thread_id, BranchData::UnpredictedBranch, 1111 MinorDynInst::bubble(), thread->pcState(), branch); 1112 } else if (mem_response && 1113 num_mem_refs_committed < memoryCommitLimit) 1114 { 1115 /* Try to commit from the memory responses next */ 1116 discard_inst = inst->id.streamSeqNum != 1117 ex_info.streamSeqNum || discard; 1118 1119 DPRINTF(MinorExecute, "Trying to commit mem response: %s\n", 1120 *inst); 1121 1122 /* Complete or discard the response */ 1123 if (discard_inst) { 1124 DPRINTF(MinorExecute, "Discarding mem inst: %s as its" 1125 " stream state was unexpected, expected: %d\n", 1126 *inst, ex_info.streamSeqNum); 1127 1128 lsq.popResponse(mem_response); 1129 } else { 1130 handleMemResponse(inst, mem_response, branch, fault); 1131 committed_inst = true; 1132 } 1133 1134 completed_mem_ref = true; 1135 completed_inst = true; 1136 } else if (can_commit_insts) { 1137 /* If true, this instruction will, subject to timing tweaks, 1138 * be considered for completion. try_to_commit flattens 1139 * the `if' tree a bit and allows other tests for inst 1140 * commit to be inserted here. */ 1141 bool try_to_commit = false; 1142 1143 /* Try and issue memory ops early if they: 1144 * - Can push a request into the LSQ 1145 * - Have reached the end of their FUs 1146 * - Have had all their dependencies satisfied 1147 * - Are from the right stream 1148 * 1149 * For any other case, leave it to the normal instruction 1150 * issue below to handle them. 1151 */ 1152 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) { 1153 DPRINTF(MinorExecute, "Trying to commit from mem FUs\n"); 1154 1155 const MinorDynInstPtr head_mem_ref_inst = 1156 ex_info.inFUMemInsts->front().inst; 1157 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex]; 1158 const MinorDynInstPtr &fu_inst = fu->front().inst; 1159 1160 /* Use this, possibly out of order, inst as the one 1161 * to 'commit'/send to the LSQ */ 1162 if (!fu_inst->isBubble() && 1163 !fu_inst->inLSQ && 1164 fu_inst->canEarlyIssue && 1165 ex_info.streamSeqNum == fu_inst->id.streamSeqNum && 1166 head_exec_seq_num > fu_inst->instToWaitFor) 1167 { 1168 DPRINTF(MinorExecute, "Issuing mem ref early" 1169 " inst: %s instToWaitFor: %d\n", 1170 *(fu_inst), fu_inst->instToWaitFor); 1171 1172 inst = fu_inst; 1173 try_to_commit = true; 1174 early_memory_issue = true; 1175 completed_inst = true; 1176 } 1177 } 1178 1179 /* Try and commit FU-less insts */ 1180 if (!completed_inst && inst->isNoCostInst()) { 1181 DPRINTF(MinorExecute, "Committing no cost inst: %s", *inst); 1182 1183 try_to_commit = true; 1184 completed_inst = true; 1185 } 1186 1187 /* Try to issue from the ends of FUs and the inFlightInsts 1188 * queue */ 1189 if (!completed_inst && !inst->inLSQ) { 1190 DPRINTF(MinorExecute, "Trying to commit from FUs\n"); 1191 1192 /* Try to commit from a functional unit */ 1193 /* Is the head inst of the expected inst's FU actually the 1194 * expected inst? */ 1195 QueuedInst &fu_inst = 1196 funcUnits[inst->fuIndex]->front(); 1197 InstSeqNum fu_inst_seq_num = fu_inst.inst->id.execSeqNum; 1198 1199 if (fu_inst.inst->isBubble()) { 1200 /* No instruction ready */ 1201 completed_inst = false; 1202 } else if (fu_inst_seq_num != head_exec_seq_num) { 1203 /* Past instruction: we must have already executed it 1204 * in the same cycle and so the head inst isn't 1205 * actually at the end of its pipeline 1206 * Future instruction: handled above and only for 1207 * mem refs on their way to the LSQ */ 1208 } else if (fu_inst.inst->id == inst->id) { 1209 /* All instructions can be committed if they have the 1210 * right execSeqNum and there are no in-flight 1211 * mem insts before us */ 1212 try_to_commit = true; 1213 completed_inst = true; 1214 } 1215 } 1216 1217 if (try_to_commit) { 1218 discard_inst = inst->id.streamSeqNum != 1219 ex_info.streamSeqNum || discard; 1220 1221 /* Is this instruction discardable as its streamSeqNum 1222 * doesn't match? */ 1223 if (!discard_inst) { 1224 /* Try to commit or discard a non-memory instruction. 1225 * Memory ops are actually 'committed' from this FUs 1226 * and 'issued' into the memory system so we need to 1227 * account for them later (commit_was_mem_issue gets 1228 * set) */ 1229 if (inst->extraCommitDelayExpr) { 1230 DPRINTF(MinorExecute, "Evaluating expression for" 1231 " extra commit delay inst: %s\n", *inst); 1232 1233 ThreadContext *thread = cpu.getContext(thread_id); 1234 1235 TimingExprEvalContext context(inst->staticInst, 1236 thread, NULL); 1237 1238 uint64_t extra_delay = inst->extraCommitDelayExpr-> 1239 eval(context); 1240 1241 DPRINTF(MinorExecute, "Extra commit delay expr" 1242 " result: %d\n", extra_delay); 1243 1244 if (extra_delay < 128) { 1245 inst->extraCommitDelay += Cycles(extra_delay); 1246 } else { 1247 DPRINTF(MinorExecute, "Extra commit delay was" 1248 " very long: %d\n", extra_delay); 1249 } 1250 inst->extraCommitDelayExpr = NULL; 1251 } 1252 1253 /* Move the extraCommitDelay from the instruction 1254 * into the minimumCommitCycle */ 1255 if (inst->extraCommitDelay != Cycles(0)) { 1256 inst->minimumCommitCycle = cpu.curCycle() + 1257 inst->extraCommitDelay; 1258 inst->extraCommitDelay = Cycles(0); 1259 } 1260 1261 /* @todo Think about making lastMemBarrier be 1262 * MAX_UINT_64 to avoid using 0 as a marker value */ 1263 if (!inst->isFault() && inst->isMemRef() && 1264 lsq.getLastMemBarrier(thread_id) < 1265 inst->id.execSeqNum && 1266 lsq.getLastMemBarrier(thread_id) != 0) 1267 { 1268 DPRINTF(MinorExecute, "Not committing inst: %s yet" 1269 " as there are incomplete barriers in flight\n", 1270 *inst); 1271 completed_inst = false; 1272 } else if (inst->minimumCommitCycle > now) { 1273 DPRINTF(MinorExecute, "Not committing inst: %s yet" 1274 " as it wants to be stalled for %d more cycles\n", 1275 *inst, inst->minimumCommitCycle - now); 1276 completed_inst = false; 1277 } else { 1278 completed_inst = commitInst(inst, 1279 early_memory_issue, branch, fault, 1280 committed_inst, issued_mem_ref); 1281 } 1282 } else { 1283 /* Discard instruction */ 1284 completed_inst = true; 1285 } 1286 1287 if (completed_inst) { 1288 /* Allow the pipeline to advance. If the FU head 1289 * instruction wasn't the inFlightInsts head 1290 * but had already been committed, it would have 1291 * unstalled the pipeline before here */ 1292 if (inst->fuIndex != noCostFUIndex) { 1293 DPRINTF(MinorExecute, "Unstalling %d for inst %s\n", inst->fuIndex, inst->id); 1294 funcUnits[inst->fuIndex]->stalled = false; 1295 } 1296 } 1297 } 1298 } else { 1299 DPRINTF(MinorExecute, "No instructions to commit\n"); 1300 completed_inst = false; 1301 } 1302 1303 /* All discardable instructions must also be 'completed' by now */ 1304 assert(!(discard_inst && !completed_inst)); 1305 1306 /* Instruction committed but was discarded due to streamSeqNum 1307 * mismatch */ 1308 if (discard_inst) { 1309 DPRINTF(MinorExecute, "Discarding inst: %s as its stream" 1310 " state was unexpected, expected: %d\n", 1311 *inst, ex_info.streamSeqNum); 1312 1313 if (fault == NoFault) 1314 cpu.stats.numDiscardedOps++; 1315 } 1316 1317 /* Mark the mem inst as being in the LSQ */ 1318 if (issued_mem_ref) { 1319 inst->fuIndex = 0; 1320 inst->inLSQ = true; 1321 } 1322 1323 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts 1324 * as they've *definitely* exited the FUs */ 1325 if (completed_inst && inst->isMemRef()) { 1326 /* The MemRef could have been discarded from the FU or the memory 1327 * queue, so just check an FU instruction */ 1328 if (!ex_info.inFUMemInsts->empty() && 1329 ex_info.inFUMemInsts->front().inst == inst) 1330 { 1331 ex_info.inFUMemInsts->pop(); 1332 } 1333 } 1334 1335 if (completed_inst && !(issued_mem_ref && fault == NoFault)) { 1336 /* Note that this includes discarded insts */ 1337 DPRINTF(MinorExecute, "Completed inst: %s\n", *inst); 1338 1339 /* Got to the end of a full instruction? */ 1340 ex_info.lastCommitWasEndOfMacroop = inst->isFault() || 1341 inst->isLastOpInInst(); 1342 1343 /* lastPredictionSeqNum is kept as a convenience to prevent its 1344 * value from changing too much on the minorview display */ 1345 ex_info.lastPredictionSeqNum = inst->id.predictionSeqNum; 1346 1347 /* Finished with the inst, remove it from the inst queue and 1348 * clear its dependencies */ 1349 ex_info.inFlightInsts->pop(); 1350 1351 /* Complete barriers in the LSQ/move to store buffer */ 1352 if (inst->isInst() && inst->staticInst->isMemBarrier()) { 1353 DPRINTF(MinorMem, "Completing memory barrier" 1354 " inst: %s committed: %d\n", *inst, committed_inst); 1355 lsq.completeMemBarrierInst(inst, committed_inst); 1356 } 1357 1358 scoreboard[thread_id].clearInstDests(inst, inst->isMemRef()); 1359 } 1360 1361 /* Handle per-cycle instruction counting */ 1362 if (committed_inst) { 1363 bool is_no_cost_inst = inst->isNoCostInst(); 1364 1365 /* Don't show no cost instructions as having taken a commit 1366 * slot */ 1367 if (DTRACE(MinorTrace) && !is_no_cost_inst) 1368 ex_info.instsBeingCommitted.insts[num_insts_committed] = inst; 1369 1370 if (!is_no_cost_inst) 1371 num_insts_committed++; 1372 1373 if (num_insts_committed == commitLimit) 1374 DPRINTF(MinorExecute, "Reached inst commit limit\n"); 1375 1376 /* Re-set the time of the instruction if that's required for 1377 * tracing */ 1378 if (inst->traceData) { 1379 if (setTraceTimeOnCommit) 1380 inst->traceData->setWhen(curTick()); 1381 inst->traceData->dump(); 1382 } 1383 1384 if (completed_mem_ref) 1385 num_mem_refs_committed++; 1386 1387 if (num_mem_refs_committed == memoryCommitLimit) 1388 DPRINTF(MinorExecute, "Reached mem ref commit limit\n"); 1389 } 1390 } 1391} 1392 1393bool 1394Execute::isInbetweenInsts(ThreadID thread_id) const 1395{ 1396 return executeInfo[thread_id].lastCommitWasEndOfMacroop && 1397 !lsq.accessesInFlight(); 1398} 1399 1400void 1401Execute::evaluate() 1402{ 1403 if (!inp.outputWire->isBubble()) 1404 inputBuffer[inp.outputWire->threadId].setTail(*inp.outputWire); 1405 1406 BranchData &branch = *out.inputWire; 1407 1408 unsigned int num_issued = 0; 1409 1410 /* Do all the cycle-wise activities for dcachePort here to potentially 1411 * free up input spaces in the LSQ's requests queue */ 1412 lsq.step(); 1413 1414 /* Check interrupts first. Will halt commit if interrupt found */ 1415 bool interrupted = false; 1416 ThreadID interrupt_tid = checkInterrupts(branch, interrupted); 1417 1418 if (interrupt_tid != InvalidThreadID) { 1419 /* Signalling an interrupt this cycle, not issuing/committing from 1420 * any other threads */ 1421 } else if (!branch.isBubble()) { 1422 /* It's important that this is here to carry Fetch1 wakeups to Fetch1 1423 * without overwriting them */ 1424 DPRINTF(MinorInterrupt, "Execute skipping a cycle to allow old" 1425 " branch to complete\n"); 1426 } else { 1427 ThreadID commit_tid = getCommittingThread(); 1428 1429 if (commit_tid != InvalidThreadID) { 1430 ExecuteThreadInfo& commit_info = executeInfo[commit_tid]; 1431 1432 DPRINTF(MinorExecute, "Attempting to commit [tid:%d]\n", 1433 commit_tid); 1434 /* commit can set stalled flags observable to issue and so *must* be 1435 * called first */ 1436 if (commit_info.drainState != NotDraining) { 1437 if (commit_info.drainState == DrainCurrentInst) { 1438 /* Commit only micro-ops, don't kill anything else */ 1439 commit(commit_tid, true, false, branch); 1440 1441 if (isInbetweenInsts(commit_tid)) 1442 setDrainState(commit_tid, DrainHaltFetch); 1443 1444 /* Discard any generated branch */ 1445 branch = BranchData::bubble(); 1446 } else if (commit_info.drainState == DrainAllInsts) { 1447 /* Kill all instructions */ 1448 while (getInput(commit_tid)) 1449 popInput(commit_tid); 1450 commit(commit_tid, false, true, branch); 1451 } 1452 } else { 1453 /* Commit micro-ops only if interrupted. Otherwise, commit 1454 * anything you like */ 1455 DPRINTF(MinorExecute, "Committing micro-ops for interrupt[tid:%d]\n", 1456 commit_tid); 1457 bool only_commit_microops = interrupted && 1458 hasInterrupt(commit_tid); 1459 commit(commit_tid, only_commit_microops, false, branch); 1460 } 1461 1462 /* Halt fetch, but don't do it until we have the current instruction in 1463 * the bag */ 1464 if (commit_info.drainState == DrainHaltFetch) { 1465 updateBranchData(commit_tid, BranchData::HaltFetch, 1466 MinorDynInst::bubble(), TheISA::PCState(0), branch); 1467 1468 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1469 setDrainState(commit_tid, DrainAllInsts); 1470 } 1471 } 1472 ThreadID issue_tid = getIssuingThread(); 1473 /* This will issue merrily even when interrupted in the sure and 1474 * certain knowledge that the interrupt with change the stream */ 1475 if (issue_tid != InvalidThreadID) { 1476 DPRINTF(MinorExecute, "Attempting to issue [tid:%d]\n", 1477 issue_tid); 1478 num_issued = issue(issue_tid); 1479 } 1480 1481 } 1482 1483 /* Run logic to step functional units + decide if we are active on the next 1484 * clock cycle */ 1485 std::vector<MinorDynInstPtr> next_issuable_insts; 1486 bool can_issue_next = false; 1487 1488 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1489 /* Find the next issuable instruction for each thread and see if it can 1490 be issued */ 1491 if (getInput(tid)) { 1492 unsigned int input_index = executeInfo[tid].inputIndex; 1493 MinorDynInstPtr inst = getInput(tid)->insts[input_index]; 1494 if (inst->isFault()) { 1495 can_issue_next = true; 1496 } else if (!inst->isBubble()) { 1497 next_issuable_insts.push_back(inst); 1498 } 1499 } 1500 } 1501 1502 bool becoming_stalled = true; 1503 1504 /* Advance the pipelines and note whether they still need to be 1505 * advanced */ 1506 for (unsigned int i = 0; i < numFuncUnits; i++) { 1507 FUPipeline *fu = funcUnits[i]; 1508 fu->advance(); 1509 1510 /* If we need to tick again, the pipeline will have been left or set 1511 * to be unstalled */ 1512 if (fu->occupancy !=0 && !fu->stalled) 1513 becoming_stalled = false; 1514 1515 /* Could we possibly issue the next instruction from any thread? 1516 * This is quite an expensive test and is only used to determine 1517 * if the CPU should remain active, only run it if we aren't sure 1518 * we are active next cycle yet */ 1519 for (auto inst : next_issuable_insts) { 1520 if (!fu->stalled && fu->provides(inst->staticInst->opClass()) && 1521 scoreboard[inst->id.threadId].canInstIssue(inst, 1522 NULL, NULL, cpu.curCycle() + Cycles(1), 1523 cpu.getContext(inst->id.threadId))) { 1524 can_issue_next = true; 1525 break; 1526 } 1527 } 1528 } 1529 1530 bool head_inst_might_commit = false; 1531 1532 /* Could the head in flight insts be committed */ 1533 for (auto const &info : executeInfo) { 1534 if (!info.inFlightInsts->empty()) { 1535 const QueuedInst &head_inst = info.inFlightInsts->front(); 1536 1537 if (head_inst.inst->isNoCostInst()) { 1538 head_inst_might_commit = true; 1539 } else { 1540 FUPipeline *fu = funcUnits[head_inst.inst->fuIndex]; 1541 if ((fu->stalled && 1542 fu->front().inst->id == head_inst.inst->id) || 1543 lsq.findResponse(head_inst.inst)) 1544 { 1545 head_inst_might_commit = true; 1546 break; 1547 } 1548 } 1549 } 1550 } 1551 1552 DPRINTF(Activity, "Need to tick num issued insts: %s%s%s%s%s%s\n", 1553 (num_issued != 0 ? " (issued some insts)" : ""), 1554 (becoming_stalled ? "(becoming stalled)" : "(not becoming stalled)"), 1555 (can_issue_next ? " (can issued next inst)" : ""), 1556 (head_inst_might_commit ? "(head inst might commit)" : ""), 1557 (lsq.needsToTick() ? " (LSQ needs to tick)" : ""), 1558 (interrupted ? " (interrupted)" : "")); 1559 1560 bool need_to_tick = 1561 num_issued != 0 || /* Issued some insts this cycle */ 1562 !becoming_stalled || /* Some FU pipelines can still move */ 1563 can_issue_next || /* Can still issue a new inst */ 1564 head_inst_might_commit || /* Could possible commit the next inst */ 1565 lsq.needsToTick() || /* Must step the dcache port */ 1566 interrupted; /* There are pending interrupts */ 1567 1568 if (!need_to_tick) { 1569 DPRINTF(Activity, "The next cycle might be skippable as there are no" 1570 " advanceable FUs\n"); 1571 } 1572 1573 /* Wake up if we need to tick again */ 1574 if (need_to_tick) 1575 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1576 1577 /* Note activity of following buffer */ 1578 if (!branch.isBubble()) 1579 cpu.activityRecorder->activity(); 1580 1581 /* Make sure the input (if any left) is pushed */ 1582 if (!inp.outputWire->isBubble()) 1583 inputBuffer[inp.outputWire->threadId].pushTail(); 1584} 1585 1586ThreadID 1587Execute::checkInterrupts(BranchData& branch, bool& interrupted) 1588{ 1589 ThreadID tid = interruptPriority; 1590 /* Evaluate interrupts in round-robin based upon service */ 1591 do { 1592 /* Has an interrupt been signalled? This may not be acted on 1593 * straighaway so this is different from took_interrupt */ 1594 bool thread_interrupted = false; 1595 1596 if (FullSystem && cpu.getInterruptController(tid)) { 1597 /* This is here because it seems that after drainResume the 1598 * interrupt controller isn't always set */ 1599 thread_interrupted = executeInfo[tid].drainState == NotDraining && 1600 isInterrupted(tid); 1601 interrupted = interrupted || thread_interrupted; 1602 } else { 1603 DPRINTF(MinorInterrupt, "No interrupt controller\n"); 1604 } 1605 DPRINTF(MinorInterrupt, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n", 1606 tid, thread_interrupted, isInbetweenInsts(tid)); 1607 /* Act on interrupts */ 1608 if (thread_interrupted && isInbetweenInsts(tid)) { 1609 if (takeInterrupt(tid, branch)) { 1610 interruptPriority = tid; 1611 return tid; 1612 } 1613 } else { 1614 tid = (tid + 1) % cpu.numThreads; 1615 } 1616 } while (tid != interruptPriority); 1617 1618 return InvalidThreadID; 1619} 1620 1621bool 1622Execute::hasInterrupt(ThreadID thread_id) 1623{ 1624 if (FullSystem && cpu.getInterruptController(thread_id)) { 1625 return executeInfo[thread_id].drainState == NotDraining && 1626 isInterrupted(thread_id); 1627 } 1628 1629 return false; 1630} 1631 1632void 1633Execute::minorTrace() const 1634{ 1635 std::ostringstream insts; 1636 std::ostringstream stalled; 1637 1638 executeInfo[0].instsBeingCommitted.reportData(insts); 1639 lsq.minorTrace(); 1640 inputBuffer[0].minorTrace(); 1641 scoreboard[0].minorTrace(); 1642 1643 /* Report functional unit stalling in one string */ 1644 unsigned int i = 0; 1645 while (i < numFuncUnits) 1646 { 1647 stalled << (funcUnits[i]->stalled ? '1' : 'E'); 1648 i++; 1649 if (i != numFuncUnits) 1650 stalled << ','; 1651 } 1652 1653 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d" 1654 " stalled=%s drainState=%d isInbetweenInsts=%d\n", 1655 insts.str(), executeInfo[0].inputIndex, executeInfo[0].streamSeqNum, 1656 stalled.str(), executeInfo[0].drainState, isInbetweenInsts(0)); 1657 1658 std::for_each(funcUnits.begin(), funcUnits.end(), 1659 std::mem_fun(&FUPipeline::minorTrace)); 1660 1661 executeInfo[0].inFlightInsts->minorTrace(); 1662 executeInfo[0].inFUMemInsts->minorTrace(); 1663} 1664 1665inline ThreadID 1666Execute::getCommittingThread() 1667{ 1668 std::vector<ThreadID> priority_list; 1669 1670 switch (cpu.threadPolicy) { 1671 case Enums::SingleThreaded: 1672 return 0; 1673 case Enums::RoundRobin: 1674 priority_list = cpu.roundRobinPriority(commitPriority); 1675 break; 1676 case Enums::Random: 1677 priority_list = cpu.randomPriority(); 1678 break; 1679 default: 1680 panic("Invalid thread policy"); 1681 } 1682 1683 for (auto tid : priority_list) { 1684 ExecuteThreadInfo &ex_info = executeInfo[tid]; 1685 bool can_commit_insts = !ex_info.inFlightInsts->empty(); 1686 if (can_commit_insts) { 1687 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front()); 1688 MinorDynInstPtr inst = head_inflight_inst->inst; 1689 1690 can_commit_insts = can_commit_insts && 1691 (!inst->inLSQ || (lsq.findResponse(inst) != NULL)); 1692 1693 if (!inst->inLSQ) { 1694 bool can_transfer_mem_inst = false; 1695 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) { 1696 const MinorDynInstPtr head_mem_ref_inst = 1697 ex_info.inFUMemInsts->front().inst; 1698 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex]; 1699 const MinorDynInstPtr &fu_inst = fu->front().inst; 1700 can_transfer_mem_inst = 1701 !fu_inst->isBubble() && 1702 fu_inst->id.threadId == tid && 1703 !fu_inst->inLSQ && 1704 fu_inst->canEarlyIssue && 1705 inst->id.execSeqNum > fu_inst->instToWaitFor; 1706 } 1707 1708 bool can_execute_fu_inst = inst->fuIndex == noCostFUIndex; 1709 if (can_commit_insts && !can_transfer_mem_inst && 1710 inst->fuIndex != noCostFUIndex) 1711 { 1712 QueuedInst& fu_inst = funcUnits[inst->fuIndex]->front(); 1713 can_execute_fu_inst = !fu_inst.inst->isBubble() && 1714 fu_inst.inst->id == inst->id; 1715 } 1716 1717 can_commit_insts = can_commit_insts && 1718 (can_transfer_mem_inst || can_execute_fu_inst); 1719 } 1720 } 1721 1722 1723 if (can_commit_insts) { 1724 commitPriority = tid; 1725 return tid; 1726 } 1727 } 1728 1729 return InvalidThreadID; 1730} 1731 1732inline ThreadID 1733Execute::getIssuingThread() 1734{ 1735 std::vector<ThreadID> priority_list; 1736 1737 switch (cpu.threadPolicy) { 1738 case Enums::SingleThreaded: 1739 return 0; 1740 case Enums::RoundRobin: 1741 priority_list = cpu.roundRobinPriority(issuePriority); 1742 break; 1743 case Enums::Random: 1744 priority_list = cpu.randomPriority(); 1745 break; 1746 default: 1747 panic("Invalid thread scheduling policy."); 1748 } 1749 1750 for (auto tid : priority_list) { 1751 if (getInput(tid)) { 1752 issuePriority = tid; 1753 return tid; 1754 } 1755 } 1756 1757 return InvalidThreadID; 1758} 1759 1760void 1761Execute::drainResume() 1762{ 1763 DPRINTF(Drain, "MinorExecute drainResume\n"); 1764 1765 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1766 setDrainState(tid, NotDraining); 1767 } 1768 1769 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1770} 1771 1772std::ostream &operator <<(std::ostream &os, Execute::DrainState state) 1773{ 1774 switch (state) 1775 { 1776 case Execute::NotDraining: 1777 os << "NotDraining"; 1778 break; 1779 case Execute::DrainCurrentInst: 1780 os << "DrainCurrentInst"; 1781 break; 1782 case Execute::DrainHaltFetch: 1783 os << "DrainHaltFetch"; 1784 break; 1785 case Execute::DrainAllInsts: 1786 os << "DrainAllInsts"; 1787 break; 1788 default: 1789 os << "Drain-" << static_cast<int>(state); 1790 break; 1791 } 1792 1793 return os; 1794} 1795 1796void 1797Execute::setDrainState(ThreadID thread_id, DrainState state) 1798{ 1799 DPRINTF(Drain, "setDrainState[%d]: %s\n", thread_id, state); 1800 executeInfo[thread_id].drainState = state; 1801} 1802 1803unsigned int 1804Execute::drain() 1805{ 1806 DPRINTF(Drain, "MinorExecute drain\n"); 1807 1808 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1809 if (executeInfo[tid].drainState == NotDraining) { 1810 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1811 1812 /* Go to DrainCurrentInst if we're between microops 1813 * or waiting on an unbufferable memory operation. 1814 * Otherwise we can go straight to DrainHaltFetch 1815 */ 1816 if (isInbetweenInsts(tid)) 1817 setDrainState(tid, DrainHaltFetch); 1818 else 1819 setDrainState(tid, DrainCurrentInst); 1820 } 1821 } 1822 return (isDrained() ? 0 : 1); 1823} 1824 1825bool 1826Execute::isDrained() 1827{ 1828 if (!lsq.isDrained()) 1829 return false; 1830 1831 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1832 if (!inputBuffer[tid].empty() || 1833 !executeInfo[tid].inFlightInsts->empty()) { 1834 1835 return false; 1836 } 1837 } 1838 1839 return true; 1840} 1841 1842Execute::~Execute() 1843{ 1844 for (unsigned int i = 0; i < numFuncUnits; i++) 1845 delete funcUnits[i]; 1846 1847 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) 1848 delete executeInfo[tid].inFlightInsts; 1849} 1850 1851bool 1852Execute::instIsRightStream(MinorDynInstPtr inst) 1853{ 1854 return inst->id.streamSeqNum == executeInfo[inst->id.threadId].streamSeqNum; 1855} 1856 1857bool 1858Execute::instIsHeadInst(MinorDynInstPtr inst) 1859{ 1860 bool ret = false; 1861 1862 if (!executeInfo[inst->id.threadId].inFlightInsts->empty()) 1863 ret = executeInfo[inst->id.threadId].inFlightInsts->front().inst->id == inst->id; 1864 1865 return ret; 1866} 1867 1868MinorCPU::MinorCPUPort & 1869Execute::getDcachePort() 1870{ 1871 return lsq.getDcachePort(); 1872} 1873 1874} 1875