execute.cc revision 11567
1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andrew Bardsley 38 */ 39 40#include "arch/locked_mem.hh" 41#include "arch/registers.hh" 42#include "arch/utility.hh" 43#include "cpu/minor/cpu.hh" 44#include "cpu/minor/exec_context.hh" 45#include "cpu/minor/execute.hh" 46#include "cpu/minor/fetch1.hh" 47#include "cpu/minor/lsq.hh" 48#include "cpu/op_class.hh" 49#include "debug/Activity.hh" 50#include "debug/Branch.hh" 51#include "debug/Drain.hh" 52#include "debug/MinorExecute.hh" 53#include "debug/MinorInterrupt.hh" 54#include "debug/MinorMem.hh" 55#include "debug/MinorTrace.hh" 56#include "debug/PCEvent.hh" 57 58namespace Minor 59{ 60 61Execute::Execute(const std::string &name_, 62 MinorCPU &cpu_, 63 MinorCPUParams ¶ms, 64 Latch<ForwardInstData>::Output inp_, 65 Latch<BranchData>::Input out_) : 66 Named(name_), 67 inp(inp_), 68 out(out_), 69 cpu(cpu_), 70 issueLimit(params.executeIssueLimit), 71 memoryIssueLimit(params.executeMemoryIssueLimit), 72 commitLimit(params.executeCommitLimit), 73 memoryCommitLimit(params.executeMemoryCommitLimit), 74 processMoreThanOneInput(params.executeCycleInput), 75 fuDescriptions(*params.executeFuncUnits), 76 numFuncUnits(fuDescriptions.funcUnits.size()), 77 setTraceTimeOnCommit(params.executeSetTraceTimeOnCommit), 78 setTraceTimeOnIssue(params.executeSetTraceTimeOnIssue), 79 allowEarlyMemIssue(params.executeAllowEarlyMemoryIssue), 80 noCostFUIndex(fuDescriptions.funcUnits.size() + 1), 81 lsq(name_ + ".lsq", name_ + ".dcache_port", 82 cpu_, *this, 83 params.executeMaxAccessesInMemory, 84 params.executeMemoryWidth, 85 params.executeLSQRequestsQueueSize, 86 params.executeLSQTransfersQueueSize, 87 params.executeLSQStoreBufferSize, 88 params.executeLSQMaxStoreBufferStoresPerCycle), 89 executeInfo(params.numThreads, ExecuteThreadInfo(params.executeCommitLimit)), 90 interruptPriority(0), 91 issuePriority(0), 92 commitPriority(0) 93{ 94 if (commitLimit < 1) { 95 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_, 96 commitLimit); 97 } 98 99 if (issueLimit < 1) { 100 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_, 101 issueLimit); 102 } 103 104 if (memoryIssueLimit < 1) { 105 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_, 106 memoryIssueLimit); 107 } 108 109 if (memoryCommitLimit > commitLimit) { 110 fatal("%s: executeMemoryCommitLimit (%d) must be <=" 111 " executeCommitLimit (%d)\n", 112 name_, memoryCommitLimit, commitLimit); 113 } 114 115 if (params.executeInputBufferSize < 1) { 116 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_, 117 params.executeInputBufferSize); 118 } 119 120 if (params.executeInputBufferSize < 1) { 121 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_, 122 params.executeInputBufferSize); 123 } 124 125 /* This should be large enough to count all the in-FU instructions 126 * which need to be accounted for in the inFlightInsts 127 * queue */ 128 unsigned int total_slots = 0; 129 130 /* Make FUPipelines for each MinorFU */ 131 for (unsigned int i = 0; i < numFuncUnits; i++) { 132 std::ostringstream fu_name; 133 MinorFU *fu_description = fuDescriptions.funcUnits[i]; 134 135 /* Note the total number of instruction slots (for sizing 136 * the inFlightInst queue) and the maximum latency of any FU 137 * (for sizing the activity recorder) */ 138 total_slots += fu_description->opLat; 139 140 fu_name << name_ << ".fu." << i; 141 142 FUPipeline *fu = new FUPipeline(fu_name.str(), *fu_description, cpu); 143 144 funcUnits.push_back(fu); 145 } 146 147 /** Check that there is a functional unit for all operation classes */ 148 for (int op_class = No_OpClass + 1; op_class < Num_OpClasses; op_class++) { 149 bool found_fu = false; 150 unsigned int fu_index = 0; 151 152 while (fu_index < numFuncUnits && !found_fu) 153 { 154 if (funcUnits[fu_index]->provides( 155 static_cast<OpClass>(op_class))) 156 { 157 found_fu = true; 158 } 159 fu_index++; 160 } 161 162 if (!found_fu) { 163 warn("No functional unit for OpClass %s\n", 164 Enums::OpClassStrings[op_class]); 165 } 166 } 167 168 /* Per-thread structures */ 169 for (ThreadID tid = 0; tid < params.numThreads; tid++) { 170 std::string tid_str = std::to_string(tid); 171 172 /* Input Buffers */ 173 inputBuffer.push_back( 174 InputBuffer<ForwardInstData>( 175 name_ + ".inputBuffer" + tid_str, "insts", 176 params.executeInputBufferSize)); 177 178 /* Scoreboards */ 179 scoreboard.push_back(Scoreboard(name_ + ".scoreboard" + tid_str)); 180 181 /* In-flight instruction records */ 182 executeInfo[tid].inFlightInsts = new Queue<QueuedInst, 183 ReportTraitsAdaptor<QueuedInst> >( 184 name_ + ".inFlightInsts" + tid_str, "insts", total_slots); 185 186 executeInfo[tid].inFUMemInsts = new Queue<QueuedInst, 187 ReportTraitsAdaptor<QueuedInst> >( 188 name_ + ".inFUMemInsts" + tid_str, "insts", total_slots); 189 } 190} 191 192const ForwardInstData * 193Execute::getInput(ThreadID tid) 194{ 195 /* Get a line from the inputBuffer to work with */ 196 if (!inputBuffer[tid].empty()) { 197 const ForwardInstData &head = inputBuffer[tid].front(); 198 199 return (head.isBubble() ? NULL : &(inputBuffer[tid].front())); 200 } else { 201 return NULL; 202 } 203} 204 205void 206Execute::popInput(ThreadID tid) 207{ 208 if (!inputBuffer[tid].empty()) 209 inputBuffer[tid].pop(); 210 211 executeInfo[tid].inputIndex = 0; 212} 213 214void 215Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch) 216{ 217 ThreadContext *thread = cpu.getContext(inst->id.threadId); 218 const TheISA::PCState &pc_before = inst->pc; 219 TheISA::PCState target = thread->pcState(); 220 221 /* Force a branch for SerializeAfter instructions at the end of micro-op 222 * sequence when we're not suspended */ 223 bool force_branch = thread->status() != ThreadContext::Suspended && 224 !inst->isFault() && 225 inst->isLastOpInInst() && 226 (inst->staticInst->isSerializeAfter() || 227 inst->staticInst->isIprAccess()); 228 229 DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n", 230 pc_before, target, (force_branch ? " (forcing)" : "")); 231 232 /* Will we change the PC to something other than the next instruction? */ 233 bool must_branch = pc_before != target || 234 fault != NoFault || 235 force_branch; 236 237 /* The reason for the branch data we're about to generate, set below */ 238 BranchData::Reason reason = BranchData::NoBranch; 239 240 if (fault == NoFault) 241 { 242 TheISA::advancePC(target, inst->staticInst); 243 thread->pcState(target); 244 245 DPRINTF(Branch, "Advancing current PC from: %s to: %s\n", 246 pc_before, target); 247 } 248 249 if (inst->predictedTaken && !force_branch) { 250 /* Predicted to branch */ 251 if (!must_branch) { 252 /* No branch was taken, change stream to get us back to the 253 * intended PC value */ 254 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x but" 255 " none happened inst: %s\n", 256 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst); 257 258 reason = BranchData::BadlyPredictedBranch; 259 } else if (inst->predictedTarget == target) { 260 /* Branch prediction got the right target, kill the branch and 261 * carry on. 262 * Note that this information to the branch predictor might get 263 * overwritten by a "real" branch during this cycle */ 264 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x correctly" 265 " inst: %s\n", 266 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst); 267 268 reason = BranchData::CorrectlyPredictedBranch; 269 } else { 270 /* Branch prediction got the wrong target */ 271 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x" 272 " but got the wrong target (actual: 0x%x) inst: %s\n", 273 inst->pc.instAddr(), inst->predictedTarget.instAddr(), 274 target.instAddr(), *inst); 275 276 reason = BranchData::BadlyPredictedBranchTarget; 277 } 278 } else if (must_branch) { 279 /* Unpredicted branch */ 280 DPRINTF(Branch, "Unpredicted branch from 0x%x to 0x%x inst: %s\n", 281 inst->pc.instAddr(), target.instAddr(), *inst); 282 283 reason = BranchData::UnpredictedBranch; 284 } else { 285 /* No branch at all */ 286 reason = BranchData::NoBranch; 287 } 288 289 updateBranchData(inst->id.threadId, reason, inst, target, branch); 290} 291 292void 293Execute::updateBranchData( 294 ThreadID tid, 295 BranchData::Reason reason, 296 MinorDynInstPtr inst, const TheISA::PCState &target, 297 BranchData &branch) 298{ 299 if (reason != BranchData::NoBranch) { 300 /* Bump up the stream sequence number on a real branch*/ 301 if (BranchData::isStreamChange(reason)) 302 executeInfo[tid].streamSeqNum++; 303 304 /* Branches (even mis-predictions) don't change the predictionSeqNum, 305 * just the streamSeqNum */ 306 branch = BranchData(reason, tid, 307 executeInfo[tid].streamSeqNum, 308 /* Maintaining predictionSeqNum if there's no inst is just a 309 * courtesy and looks better on minorview */ 310 (inst->isBubble() ? executeInfo[tid].lastPredictionSeqNum 311 : inst->id.predictionSeqNum), 312 target, inst); 313 314 DPRINTF(Branch, "Branch data signalled: %s\n", branch); 315 } 316} 317 318void 319Execute::handleMemResponse(MinorDynInstPtr inst, 320 LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault) 321{ 322 ThreadID thread_id = inst->id.threadId; 323 ThreadContext *thread = cpu.getContext(thread_id); 324 325 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst); 326 327 PacketPtr packet = response->packet; 328 329 bool is_load = inst->staticInst->isLoad(); 330 bool is_store = inst->staticInst->isStore(); 331 bool is_prefetch = inst->staticInst->isDataPrefetch(); 332 333 /* If true, the trace's predicate value will be taken from the exec 334 * context predicate, otherwise, it will be set to false */ 335 bool use_context_predicate = true; 336 337 if (response->fault != NoFault) { 338 /* Invoke memory faults. */ 339 DPRINTF(MinorMem, "Completing fault from DTLB access: %s\n", 340 response->fault->name()); 341 342 if (inst->staticInst->isPrefetch()) { 343 DPRINTF(MinorMem, "Not taking fault on prefetch: %s\n", 344 response->fault->name()); 345 346 /* Don't assign to fault */ 347 } else { 348 /* Take the fault raised during the TLB/memory access */ 349 fault = response->fault; 350 351 fault->invoke(thread, inst->staticInst); 352 } 353 } else if (!packet) { 354 DPRINTF(MinorMem, "Completing failed request inst: %s\n", 355 *inst); 356 use_context_predicate = false; 357 } else if (packet->isError()) { 358 DPRINTF(MinorMem, "Trying to commit error response: %s\n", 359 *inst); 360 361 fatal("Received error response packet for inst: %s\n", *inst); 362 } else if (is_store || is_load || is_prefetch) { 363 assert(packet); 364 365 DPRINTF(MinorMem, "Memory response inst: %s addr: 0x%x size: %d\n", 366 *inst, packet->getAddr(), packet->getSize()); 367 368 if (is_load && packet->getSize() > 0) { 369 DPRINTF(MinorMem, "Memory data[0]: 0x%x\n", 370 static_cast<unsigned int>(packet->getConstPtr<uint8_t>()[0])); 371 } 372 373 /* Complete the memory access instruction */ 374 fault = inst->staticInst->completeAcc(packet, &context, 375 inst->traceData); 376 377 if (fault != NoFault) { 378 /* Invoke fault created by instruction completion */ 379 DPRINTF(MinorMem, "Fault in memory completeAcc: %s\n", 380 fault->name()); 381 fault->invoke(thread, inst->staticInst); 382 } else { 383 /* Stores need to be pushed into the store buffer to finish 384 * them off */ 385 if (response->needsToBeSentToStoreBuffer()) 386 lsq.sendStoreToStoreBuffer(response); 387 } 388 } else { 389 fatal("There should only ever be reads, " 390 "writes or faults at this point\n"); 391 } 392 393 lsq.popResponse(response); 394 395 if (inst->traceData) { 396 inst->traceData->setPredicate((use_context_predicate ? 397 context.readPredicate() : false)); 398 } 399 400 doInstCommitAccounting(inst); 401 402 /* Generate output to account for branches */ 403 tryToBranch(inst, fault, branch); 404} 405 406bool 407Execute::isInterrupted(ThreadID thread_id) const 408{ 409 return cpu.checkInterrupts(cpu.getContext(thread_id)); 410} 411 412bool 413Execute::takeInterrupt(ThreadID thread_id, BranchData &branch) 414{ 415 DPRINTF(MinorInterrupt, "Considering interrupt status from PC: %s\n", 416 cpu.getContext(thread_id)->pcState()); 417 418 Fault interrupt = cpu.getInterruptController(thread_id)->getInterrupt 419 (cpu.getContext(thread_id)); 420 421 if (interrupt != NoFault) { 422 /* The interrupt *must* set pcState */ 423 cpu.getInterruptController(thread_id)->updateIntrInfo 424 (cpu.getContext(thread_id)); 425 interrupt->invoke(cpu.getContext(thread_id)); 426 427 assert(!lsq.accessesInFlight()); 428 429 DPRINTF(MinorInterrupt, "Invoking interrupt: %s to PC: %s\n", 430 interrupt->name(), cpu.getContext(thread_id)->pcState()); 431 432 /* Assume that an interrupt *must* cause a branch. Assert this? */ 433 434 updateBranchData(thread_id, BranchData::Interrupt, 435 MinorDynInst::bubble(), cpu.getContext(thread_id)->pcState(), 436 branch); 437 } 438 439 return interrupt != NoFault; 440} 441 442bool 443Execute::executeMemRefInst(MinorDynInstPtr inst, BranchData &branch, 444 bool &passed_predicate, Fault &fault) 445{ 446 bool issued = false; 447 448 /* Set to true if the mem op. is issued and sent to the mem system */ 449 passed_predicate = false; 450 451 if (!lsq.canRequest()) { 452 /* Not acting on instruction yet as the memory 453 * queues are full */ 454 issued = false; 455 } else { 456 ThreadContext *thread = cpu.getContext(inst->id.threadId); 457 TheISA::PCState old_pc = thread->pcState(); 458 459 ExecContext context(cpu, *cpu.threads[inst->id.threadId], 460 *this, inst); 461 462 DPRINTF(MinorExecute, "Initiating memRef inst: %s\n", *inst); 463 464 Fault init_fault = inst->staticInst->initiateAcc(&context, 465 inst->traceData); 466 467 if (init_fault != NoFault) { 468 DPRINTF(MinorExecute, "Fault on memory inst: %s" 469 " initiateAcc: %s\n", *inst, init_fault->name()); 470 fault = init_fault; 471 } else { 472 /* Only set this if the instruction passed its 473 * predicate */ 474 passed_predicate = context.readPredicate(); 475 476 /* Set predicate in tracing */ 477 if (inst->traceData) 478 inst->traceData->setPredicate(passed_predicate); 479 480 /* If the instruction didn't pass its predicate (and so will not 481 * progress from here) Try to branch to correct and branch 482 * mis-prediction. */ 483 if (!passed_predicate) { 484 /* Leave it up to commit to handle the fault */ 485 lsq.pushFailedRequest(inst); 486 } 487 } 488 489 /* Restore thread PC */ 490 thread->pcState(old_pc); 491 issued = true; 492 } 493 494 return issued; 495} 496 497/** Increment a cyclic buffer index for indices [0, cycle_size-1] */ 498inline unsigned int 499cyclicIndexInc(unsigned int index, unsigned int cycle_size) 500{ 501 unsigned int ret = index + 1; 502 503 if (ret == cycle_size) 504 ret = 0; 505 506 return ret; 507} 508 509/** Decrement a cyclic buffer index for indices [0, cycle_size-1] */ 510inline unsigned int 511cyclicIndexDec(unsigned int index, unsigned int cycle_size) 512{ 513 int ret = index - 1; 514 515 if (ret < 0) 516 ret = cycle_size - 1; 517 518 return ret; 519} 520 521unsigned int 522Execute::issue(ThreadID thread_id) 523{ 524 const ForwardInstData *insts_in = getInput(thread_id); 525 ExecuteThreadInfo &thread = executeInfo[thread_id]; 526 527 /* Early termination if we have no instructions */ 528 if (!insts_in) 529 return 0; 530 531 /* Start from the first FU */ 532 unsigned int fu_index = 0; 533 534 /* Remains true while instructions are still being issued. If any 535 * instruction fails to issue, this is set to false and we exit issue. 536 * This strictly enforces in-order issue. For other issue behaviours, 537 * a more complicated test in the outer while loop below is needed. */ 538 bool issued = true; 539 540 /* Number of insts issues this cycle to check for issueLimit */ 541 unsigned num_insts_issued = 0; 542 543 /* Number of memory ops issues this cycle to check for memoryIssueLimit */ 544 unsigned num_mem_insts_issued = 0; 545 546 /* Number of instructions discarded this cycle in order to enforce a 547 * discardLimit. @todo, add that parameter? */ 548 unsigned num_insts_discarded = 0; 549 550 do { 551 MinorDynInstPtr inst = insts_in->insts[thread.inputIndex]; 552 Fault fault = inst->fault; 553 bool discarded = false; 554 bool issued_mem_ref = false; 555 556 if (inst->isBubble()) { 557 /* Skip */ 558 issued = true; 559 } else if (cpu.getContext(thread_id)->status() == 560 ThreadContext::Suspended) 561 { 562 DPRINTF(MinorExecute, "Not issuing inst: %s from suspended" 563 " thread\n", *inst); 564 565 issued = false; 566 } else if (inst->id.streamSeqNum != thread.streamSeqNum) { 567 DPRINTF(MinorExecute, "Discarding inst: %s as its stream" 568 " state was unexpected, expected: %d\n", 569 *inst, thread.streamSeqNum); 570 issued = true; 571 discarded = true; 572 } else { 573 /* Try and issue an instruction into an FU, assume we didn't and 574 * fix that in the loop */ 575 issued = false; 576 577 /* Try FU from 0 each instruction */ 578 fu_index = 0; 579 580 /* Try and issue a single instruction stepping through the 581 * available FUs */ 582 do { 583 FUPipeline *fu = funcUnits[fu_index]; 584 585 DPRINTF(MinorExecute, "Trying to issue inst: %s to FU: %d\n", 586 *inst, fu_index); 587 588 /* Does the examined fu have the OpClass-related capability 589 * needed to execute this instruction? Faults can always 590 * issue to any FU but probably should just 'live' in the 591 * inFlightInsts queue rather than having an FU. */ 592 bool fu_is_capable = (!inst->isFault() ? 593 fu->provides(inst->staticInst->opClass()) : true); 594 595 if (inst->isNoCostInst()) { 596 /* Issue free insts. to a fake numbered FU */ 597 fu_index = noCostFUIndex; 598 599 /* And start the countdown on activity to allow 600 * this instruction to get to the end of its FU */ 601 cpu.activityRecorder->activity(); 602 603 /* Mark the destinations for this instruction as 604 * busy */ 605 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() + 606 Cycles(0), cpu.getContext(thread_id), false); 607 608 DPRINTF(MinorExecute, "Issuing %s to %d\n", inst->id, noCostFUIndex); 609 inst->fuIndex = noCostFUIndex; 610 inst->extraCommitDelay = Cycles(0); 611 inst->extraCommitDelayExpr = NULL; 612 613 /* Push the instruction onto the inFlight queue so 614 * it can be committed in order */ 615 QueuedInst fu_inst(inst); 616 thread.inFlightInsts->push(fu_inst); 617 618 issued = true; 619 620 } else if (!fu_is_capable || fu->alreadyPushed()) { 621 /* Skip */ 622 if (!fu_is_capable) { 623 DPRINTF(MinorExecute, "Can't issue as FU: %d isn't" 624 " capable\n", fu_index); 625 } else { 626 DPRINTF(MinorExecute, "Can't issue as FU: %d is" 627 " already busy\n", fu_index); 628 } 629 } else if (fu->stalled) { 630 DPRINTF(MinorExecute, "Can't issue inst: %s into FU: %d," 631 " it's stalled\n", 632 *inst, fu_index); 633 } else if (!fu->canInsert()) { 634 DPRINTF(MinorExecute, "Can't issue inst: %s to busy FU" 635 " for another: %d cycles\n", 636 *inst, fu->cyclesBeforeInsert()); 637 } else { 638 MinorFUTiming *timing = (!inst->isFault() ? 639 fu->findTiming(inst->staticInst) : NULL); 640 641 const std::vector<Cycles> *src_latencies = 642 (timing ? &(timing->srcRegsRelativeLats) 643 : NULL); 644 645 const std::vector<bool> *cant_forward_from_fu_indices = 646 &(fu->cantForwardFromFUIndices); 647 648 if (timing && timing->suppress) { 649 DPRINTF(MinorExecute, "Can't issue inst: %s as extra" 650 " decoding is suppressing it\n", 651 *inst); 652 } else if (!scoreboard[thread_id].canInstIssue(inst, 653 src_latencies, cant_forward_from_fu_indices, 654 cpu.curCycle(), cpu.getContext(thread_id))) 655 { 656 DPRINTF(MinorExecute, "Can't issue inst: %s yet\n", 657 *inst); 658 } else { 659 /* Can insert the instruction into this FU */ 660 DPRINTF(MinorExecute, "Issuing inst: %s" 661 " into FU %d\n", *inst, 662 fu_index); 663 664 Cycles extra_dest_retire_lat = Cycles(0); 665 TimingExpr *extra_dest_retire_lat_expr = NULL; 666 Cycles extra_assumed_lat = Cycles(0); 667 668 /* Add the extraCommitDelay and extraAssumeLat to 669 * the FU pipeline timings */ 670 if (timing) { 671 extra_dest_retire_lat = 672 timing->extraCommitLat; 673 extra_dest_retire_lat_expr = 674 timing->extraCommitLatExpr; 675 extra_assumed_lat = 676 timing->extraAssumedLat; 677 } 678 679 issued_mem_ref = inst->isMemRef(); 680 681 QueuedInst fu_inst(inst); 682 683 /* Decorate the inst with FU details */ 684 inst->fuIndex = fu_index; 685 inst->extraCommitDelay = extra_dest_retire_lat; 686 inst->extraCommitDelayExpr = 687 extra_dest_retire_lat_expr; 688 689 if (issued_mem_ref) { 690 /* Remember which instruction this memory op 691 * depends on so that initiateAcc can be called 692 * early */ 693 if (allowEarlyMemIssue) { 694 inst->instToWaitFor = 695 scoreboard[thread_id].execSeqNumToWaitFor(inst, 696 cpu.getContext(thread_id)); 697 698 if (lsq.getLastMemBarrier(thread_id) > 699 inst->instToWaitFor) 700 { 701 DPRINTF(MinorExecute, "A barrier will" 702 " cause a delay in mem ref issue of" 703 " inst: %s until after inst" 704 " %d(exec)\n", *inst, 705 lsq.getLastMemBarrier(thread_id)); 706 707 inst->instToWaitFor = 708 lsq.getLastMemBarrier(thread_id); 709 } else { 710 DPRINTF(MinorExecute, "Memory ref inst:" 711 " %s must wait for inst %d(exec)" 712 " before issuing\n", 713 *inst, inst->instToWaitFor); 714 } 715 716 inst->canEarlyIssue = true; 717 } 718 /* Also queue this instruction in the memory ref 719 * queue to ensure in-order issue to the LSQ */ 720 DPRINTF(MinorExecute, "Pushing mem inst: %s\n", 721 *inst); 722 thread.inFUMemInsts->push(fu_inst); 723 } 724 725 /* Issue to FU */ 726 fu->push(fu_inst); 727 /* And start the countdown on activity to allow 728 * this instruction to get to the end of its FU */ 729 cpu.activityRecorder->activity(); 730 731 /* Mark the destinations for this instruction as 732 * busy */ 733 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() + 734 fu->description.opLat + 735 extra_dest_retire_lat + 736 extra_assumed_lat, 737 cpu.getContext(thread_id), 738 issued_mem_ref && extra_assumed_lat == Cycles(0)); 739 740 /* Push the instruction onto the inFlight queue so 741 * it can be committed in order */ 742 thread.inFlightInsts->push(fu_inst); 743 744 issued = true; 745 } 746 } 747 748 fu_index++; 749 } while (fu_index != numFuncUnits && !issued); 750 751 if (!issued) 752 DPRINTF(MinorExecute, "Didn't issue inst: %s\n", *inst); 753 } 754 755 if (issued) { 756 /* Generate MinorTrace's MinorInst lines. Do this at commit 757 * to allow better instruction annotation? */ 758 if (DTRACE(MinorTrace) && !inst->isBubble()) 759 inst->minorTraceInst(*this); 760 761 /* Mark up barriers in the LSQ */ 762 if (!discarded && inst->isInst() && 763 inst->staticInst->isMemBarrier()) 764 { 765 DPRINTF(MinorMem, "Issuing memory barrier inst: %s\n", *inst); 766 lsq.issuedMemBarrierInst(inst); 767 } 768 769 if (inst->traceData && setTraceTimeOnIssue) { 770 inst->traceData->setWhen(curTick()); 771 } 772 773 if (issued_mem_ref) 774 num_mem_insts_issued++; 775 776 if (discarded) { 777 num_insts_discarded++; 778 } else if (!inst->isBubble()) { 779 num_insts_issued++; 780 781 if (num_insts_issued == issueLimit) 782 DPRINTF(MinorExecute, "Reached inst issue limit\n"); 783 } 784 785 thread.inputIndex++; 786 DPRINTF(MinorExecute, "Stepping to next inst inputIndex: %d\n", 787 thread.inputIndex); 788 } 789 790 /* Got to the end of a line */ 791 if (thread.inputIndex == insts_in->width()) { 792 popInput(thread_id); 793 /* Set insts_in to null to force us to leave the surrounding 794 * loop */ 795 insts_in = NULL; 796 797 if (processMoreThanOneInput) { 798 DPRINTF(MinorExecute, "Wrapping\n"); 799 insts_in = getInput(thread_id); 800 } 801 } 802 } while (insts_in && thread.inputIndex < insts_in->width() && 803 /* We still have instructions */ 804 fu_index != numFuncUnits && /* Not visited all FUs */ 805 issued && /* We've not yet failed to issue an instruction */ 806 num_insts_issued != issueLimit && /* Still allowed to issue */ 807 num_mem_insts_issued != memoryIssueLimit); 808 809 return num_insts_issued; 810} 811 812bool 813Execute::tryPCEvents(ThreadID thread_id) 814{ 815 ThreadContext *thread = cpu.getContext(thread_id); 816 unsigned int num_pc_event_checks = 0; 817 818 /* Handle PC events on instructions */ 819 Addr oldPC; 820 do { 821 oldPC = thread->instAddr(); 822 cpu.system->pcEventQueue.service(thread); 823 num_pc_event_checks++; 824 } while (oldPC != thread->instAddr()); 825 826 if (num_pc_event_checks > 1) { 827 DPRINTF(PCEvent, "Acting on PC Event to PC: %s\n", 828 thread->pcState()); 829 } 830 831 return num_pc_event_checks > 1; 832} 833 834void 835Execute::doInstCommitAccounting(MinorDynInstPtr inst) 836{ 837 assert(!inst->isFault()); 838 839 MinorThread *thread = cpu.threads[inst->id.threadId]; 840 841 /* Increment the many and various inst and op counts in the 842 * thread and system */ 843 if (!inst->staticInst->isMicroop() || inst->staticInst->isLastMicroop()) 844 { 845 thread->numInst++; 846 thread->numInsts++; 847 cpu.stats.numInsts++; 848 cpu.system->totalNumInsts++; 849 850 /* Act on events related to instruction counts */ 851 cpu.comInstEventQueue[inst->id.threadId]->serviceEvents(thread->numInst); 852 cpu.system->instEventQueue.serviceEvents(cpu.system->totalNumInsts); 853 } 854 thread->numOp++; 855 thread->numOps++; 856 cpu.stats.numOps++; 857 cpu.stats.committedInstType[inst->id.threadId] 858 [inst->staticInst->opClass()]++; 859 860 /* Set the CP SeqNum to the numOps commit number */ 861 if (inst->traceData) 862 inst->traceData->setCPSeq(thread->numOp); 863 864 cpu.probeInstCommit(inst->staticInst); 865} 866 867bool 868Execute::commitInst(MinorDynInstPtr inst, bool early_memory_issue, 869 BranchData &branch, Fault &fault, bool &committed, 870 bool &completed_mem_issue) 871{ 872 ThreadID thread_id = inst->id.threadId; 873 ThreadContext *thread = cpu.getContext(thread_id); 874 875 bool completed_inst = true; 876 fault = NoFault; 877 878 /* Is the thread for this instruction suspended? In that case, just 879 * stall as long as there are no pending interrupts */ 880 if (thread->status() == ThreadContext::Suspended && 881 !isInterrupted(thread_id)) 882 { 883 DPRINTF(MinorExecute, "Not committing inst from suspended thread" 884 " inst: %s\n", *inst); 885 completed_inst = false; 886 } else if (inst->isFault()) { 887 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst); 888 889 DPRINTF(MinorExecute, "Fault inst reached Execute: %s\n", 890 inst->fault->name()); 891 892 fault = inst->fault; 893 inst->fault->invoke(thread, NULL); 894 895 tryToBranch(inst, fault, branch); 896 } else if (inst->staticInst->isMemRef()) { 897 /* Memory accesses are executed in two parts: 898 * executeMemRefInst -- calculates the EA and issues the access 899 * to memory. This is done here. 900 * handleMemResponse -- handles the response packet, done by 901 * Execute::commit 902 * 903 * While the memory access is in its FU, the EA is being 904 * calculated. At the end of the FU, when it is ready to 905 * 'commit' (in this function), the access is presented to the 906 * memory queues. When a response comes back from memory, 907 * Execute::commit will commit it. 908 */ 909 bool predicate_passed = false; 910 bool completed_mem_inst = executeMemRefInst(inst, branch, 911 predicate_passed, fault); 912 913 if (completed_mem_inst && fault != NoFault) { 914 if (early_memory_issue) { 915 DPRINTF(MinorExecute, "Fault in early executing inst: %s\n", 916 fault->name()); 917 /* Don't execute the fault, just stall the instruction 918 * until it gets to the head of inFlightInsts */ 919 inst->canEarlyIssue = false; 920 /* Not completed as we'll come here again to pick up 921 * the fault when we get to the end of the FU */ 922 completed_inst = false; 923 } else { 924 DPRINTF(MinorExecute, "Fault in execute: %s\n", 925 fault->name()); 926 fault->invoke(thread, NULL); 927 928 tryToBranch(inst, fault, branch); 929 completed_inst = true; 930 } 931 } else { 932 completed_inst = completed_mem_inst; 933 } 934 completed_mem_issue = completed_inst; 935 } else if (inst->isInst() && inst->staticInst->isMemBarrier() && 936 !lsq.canPushIntoStoreBuffer()) 937 { 938 DPRINTF(MinorExecute, "Can't commit data barrier inst: %s yet as" 939 " there isn't space in the store buffer\n", *inst); 940 941 completed_inst = false; 942 } else if (inst->isInst() && inst->staticInst->isQuiesce() 943 && !branch.isBubble()){ 944 /* This instruction can suspend, need to be able to communicate 945 * backwards, so no other branches may evaluate this cycle*/ 946 completed_inst = false; 947 } else { 948 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst); 949 950 DPRINTF(MinorExecute, "Committing inst: %s\n", *inst); 951 952 fault = inst->staticInst->execute(&context, 953 inst->traceData); 954 955 /* Set the predicate for tracing and dump */ 956 if (inst->traceData) 957 inst->traceData->setPredicate(context.readPredicate()); 958 959 committed = true; 960 961 if (fault != NoFault) { 962 DPRINTF(MinorExecute, "Fault in execute of inst: %s fault: %s\n", 963 *inst, fault->name()); 964 fault->invoke(thread, inst->staticInst); 965 } 966 967 doInstCommitAccounting(inst); 968 tryToBranch(inst, fault, branch); 969 } 970 971 if (completed_inst) { 972 /* Keep a copy of this instruction's predictionSeqNum just in case 973 * we need to issue a branch without an instruction (such as an 974 * interrupt) */ 975 executeInfo[thread_id].lastPredictionSeqNum = inst->id.predictionSeqNum; 976 977 /* Check to see if this instruction suspended the current thread. */ 978 if (!inst->isFault() && 979 thread->status() == ThreadContext::Suspended && 980 branch.isBubble() && /* It didn't branch too */ 981 !isInterrupted(thread_id)) /* Don't suspend if we have 982 interrupts */ 983 { 984 TheISA::PCState resume_pc = cpu.getContext(thread_id)->pcState(); 985 986 assert(resume_pc.microPC() == 0); 987 988 DPRINTF(MinorInterrupt, "Suspending thread: %d from Execute" 989 " inst: %s\n", thread_id, *inst); 990 991 cpu.stats.numFetchSuspends++; 992 993 updateBranchData(thread_id, BranchData::SuspendThread, inst, 994 resume_pc, branch); 995 } 996 } 997 998 return completed_inst; 999} 1000 1001void 1002Execute::commit(ThreadID thread_id, bool only_commit_microops, bool discard, 1003 BranchData &branch) 1004{ 1005 Fault fault = NoFault; 1006 Cycles now = cpu.curCycle(); 1007 ExecuteThreadInfo &ex_info = executeInfo[thread_id]; 1008 1009 /** 1010 * Try and execute as many instructions from the end of FU pipelines as 1011 * possible. This *doesn't* include actually advancing the pipelines. 1012 * 1013 * We do this by looping on the front of the inFlightInsts queue for as 1014 * long as we can find the desired instruction at the end of the 1015 * functional unit it was issued to without seeing a branch or a fault. 1016 * In this function, these terms are used: 1017 * complete -- The instruction has finished its passage through 1018 * its functional unit and its fate has been decided 1019 * (committed, discarded, issued to the memory system) 1020 * commit -- The instruction is complete(d), not discarded and has 1021 * its effects applied to the CPU state 1022 * discard(ed) -- The instruction is complete but not committed 1023 * as its streamSeqNum disagrees with the current 1024 * Execute::streamSeqNum 1025 * 1026 * Commits are also possible from two other places: 1027 * 1028 * 1) Responses returning from the LSQ 1029 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier 1030 * than their position in the inFlightInsts queue, but after all 1031 * their dependencies are resolved. 1032 */ 1033 1034 /* Has an instruction been completed? Once this becomes false, we stop 1035 * trying to complete instructions. */ 1036 bool completed_inst = true; 1037 1038 /* Number of insts committed this cycle to check against commitLimit */ 1039 unsigned int num_insts_committed = 0; 1040 1041 /* Number of memory access instructions committed to check against 1042 * memCommitLimit */ 1043 unsigned int num_mem_refs_committed = 0; 1044 1045 if (only_commit_microops && !ex_info.inFlightInsts->empty()) { 1046 DPRINTF(MinorInterrupt, "Only commit microops %s %d\n", 1047 *(ex_info.inFlightInsts->front().inst), 1048 ex_info.lastCommitWasEndOfMacroop); 1049 } 1050 1051 while (!ex_info.inFlightInsts->empty() && /* Some more instructions to process */ 1052 !branch.isStreamChange() && /* No real branch */ 1053 fault == NoFault && /* No faults */ 1054 completed_inst && /* Still finding instructions to execute */ 1055 num_insts_committed != commitLimit /* Not reached commit limit */ 1056 ) 1057 { 1058 if (only_commit_microops) { 1059 DPRINTF(MinorInterrupt, "Committing tail of insts before" 1060 " interrupt: %s\n", 1061 *(ex_info.inFlightInsts->front().inst)); 1062 } 1063 1064 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front()); 1065 1066 InstSeqNum head_exec_seq_num = 1067 head_inflight_inst->inst->id.execSeqNum; 1068 1069 /* The instruction we actually process if completed_inst 1070 * remains true to the end of the loop body. 1071 * Start by considering the the head of the in flight insts queue */ 1072 MinorDynInstPtr inst = head_inflight_inst->inst; 1073 1074 bool committed_inst = false; 1075 bool discard_inst = false; 1076 bool completed_mem_ref = false; 1077 bool issued_mem_ref = false; 1078 bool early_memory_issue = false; 1079 1080 /* Must set this again to go around the loop */ 1081 completed_inst = false; 1082 1083 /* If we're just completing a macroop before an interrupt or drain, 1084 * can we stil commit another microop (rather than a memory response) 1085 * without crosing into the next full instruction? */ 1086 bool can_commit_insts = !ex_info.inFlightInsts->empty() && 1087 !(only_commit_microops && ex_info.lastCommitWasEndOfMacroop); 1088 1089 /* Can we find a mem response for this inst */ 1090 LSQ::LSQRequestPtr mem_response = 1091 (inst->inLSQ ? lsq.findResponse(inst) : NULL); 1092 1093 DPRINTF(MinorExecute, "Trying to commit canCommitInsts: %d\n", 1094 can_commit_insts); 1095 1096 /* Test for PC events after every instruction */ 1097 if (isInbetweenInsts(thread_id) && tryPCEvents(thread_id)) { 1098 ThreadContext *thread = cpu.getContext(thread_id); 1099 1100 /* Branch as there was a change in PC */ 1101 updateBranchData(thread_id, BranchData::UnpredictedBranch, 1102 MinorDynInst::bubble(), thread->pcState(), branch); 1103 } else if (mem_response && 1104 num_mem_refs_committed < memoryCommitLimit) 1105 { 1106 /* Try to commit from the memory responses next */ 1107 discard_inst = inst->id.streamSeqNum != 1108 ex_info.streamSeqNum || discard; 1109 1110 DPRINTF(MinorExecute, "Trying to commit mem response: %s\n", 1111 *inst); 1112 1113 /* Complete or discard the response */ 1114 if (discard_inst) { 1115 DPRINTF(MinorExecute, "Discarding mem inst: %s as its" 1116 " stream state was unexpected, expected: %d\n", 1117 *inst, ex_info.streamSeqNum); 1118 1119 lsq.popResponse(mem_response); 1120 } else { 1121 handleMemResponse(inst, mem_response, branch, fault); 1122 committed_inst = true; 1123 } 1124 1125 completed_mem_ref = true; 1126 completed_inst = true; 1127 } else if (can_commit_insts) { 1128 /* If true, this instruction will, subject to timing tweaks, 1129 * be considered for completion. try_to_commit flattens 1130 * the `if' tree a bit and allows other tests for inst 1131 * commit to be inserted here. */ 1132 bool try_to_commit = false; 1133 1134 /* Try and issue memory ops early if they: 1135 * - Can push a request into the LSQ 1136 * - Have reached the end of their FUs 1137 * - Have had all their dependencies satisfied 1138 * - Are from the right stream 1139 * 1140 * For any other case, leave it to the normal instruction 1141 * issue below to handle them. 1142 */ 1143 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) { 1144 DPRINTF(MinorExecute, "Trying to commit from mem FUs\n"); 1145 1146 const MinorDynInstPtr head_mem_ref_inst = 1147 ex_info.inFUMemInsts->front().inst; 1148 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex]; 1149 const MinorDynInstPtr &fu_inst = fu->front().inst; 1150 1151 /* Use this, possibly out of order, inst as the one 1152 * to 'commit'/send to the LSQ */ 1153 if (!fu_inst->isBubble() && 1154 !fu_inst->inLSQ && 1155 fu_inst->canEarlyIssue && 1156 ex_info.streamSeqNum == fu_inst->id.streamSeqNum && 1157 head_exec_seq_num > fu_inst->instToWaitFor) 1158 { 1159 DPRINTF(MinorExecute, "Issuing mem ref early" 1160 " inst: %s instToWaitFor: %d\n", 1161 *(fu_inst), fu_inst->instToWaitFor); 1162 1163 inst = fu_inst; 1164 try_to_commit = true; 1165 early_memory_issue = true; 1166 completed_inst = true; 1167 } 1168 } 1169 1170 /* Try and commit FU-less insts */ 1171 if (!completed_inst && inst->isNoCostInst()) { 1172 DPRINTF(MinorExecute, "Committing no cost inst: %s", *inst); 1173 1174 try_to_commit = true; 1175 completed_inst = true; 1176 } 1177 1178 /* Try to issue from the ends of FUs and the inFlightInsts 1179 * queue */ 1180 if (!completed_inst && !inst->inLSQ) { 1181 DPRINTF(MinorExecute, "Trying to commit from FUs\n"); 1182 1183 /* Try to commit from a functional unit */ 1184 /* Is the head inst of the expected inst's FU actually the 1185 * expected inst? */ 1186 QueuedInst &fu_inst = 1187 funcUnits[inst->fuIndex]->front(); 1188 InstSeqNum fu_inst_seq_num = fu_inst.inst->id.execSeqNum; 1189 1190 if (fu_inst.inst->isBubble()) { 1191 /* No instruction ready */ 1192 completed_inst = false; 1193 } else if (fu_inst_seq_num != head_exec_seq_num) { 1194 /* Past instruction: we must have already executed it 1195 * in the same cycle and so the head inst isn't 1196 * actually at the end of its pipeline 1197 * Future instruction: handled above and only for 1198 * mem refs on their way to the LSQ */ 1199 } else if (fu_inst.inst->id == inst->id) { 1200 /* All instructions can be committed if they have the 1201 * right execSeqNum and there are no in-flight 1202 * mem insts before us */ 1203 try_to_commit = true; 1204 completed_inst = true; 1205 } 1206 } 1207 1208 if (try_to_commit) { 1209 discard_inst = inst->id.streamSeqNum != 1210 ex_info.streamSeqNum || discard; 1211 1212 /* Is this instruction discardable as its streamSeqNum 1213 * doesn't match? */ 1214 if (!discard_inst) { 1215 /* Try to commit or discard a non-memory instruction. 1216 * Memory ops are actually 'committed' from this FUs 1217 * and 'issued' into the memory system so we need to 1218 * account for them later (commit_was_mem_issue gets 1219 * set) */ 1220 if (inst->extraCommitDelayExpr) { 1221 DPRINTF(MinorExecute, "Evaluating expression for" 1222 " extra commit delay inst: %s\n", *inst); 1223 1224 ThreadContext *thread = cpu.getContext(thread_id); 1225 1226 TimingExprEvalContext context(inst->staticInst, 1227 thread, NULL); 1228 1229 uint64_t extra_delay = inst->extraCommitDelayExpr-> 1230 eval(context); 1231 1232 DPRINTF(MinorExecute, "Extra commit delay expr" 1233 " result: %d\n", extra_delay); 1234 1235 if (extra_delay < 128) { 1236 inst->extraCommitDelay += Cycles(extra_delay); 1237 } else { 1238 DPRINTF(MinorExecute, "Extra commit delay was" 1239 " very long: %d\n", extra_delay); 1240 } 1241 inst->extraCommitDelayExpr = NULL; 1242 } 1243 1244 /* Move the extraCommitDelay from the instruction 1245 * into the minimumCommitCycle */ 1246 if (inst->extraCommitDelay != Cycles(0)) { 1247 inst->minimumCommitCycle = cpu.curCycle() + 1248 inst->extraCommitDelay; 1249 inst->extraCommitDelay = Cycles(0); 1250 } 1251 1252 /* @todo Think about making lastMemBarrier be 1253 * MAX_UINT_64 to avoid using 0 as a marker value */ 1254 if (!inst->isFault() && inst->isMemRef() && 1255 lsq.getLastMemBarrier(thread_id) < 1256 inst->id.execSeqNum && 1257 lsq.getLastMemBarrier(thread_id) != 0) 1258 { 1259 DPRINTF(MinorExecute, "Not committing inst: %s yet" 1260 " as there are incomplete barriers in flight\n", 1261 *inst); 1262 completed_inst = false; 1263 } else if (inst->minimumCommitCycle > now) { 1264 DPRINTF(MinorExecute, "Not committing inst: %s yet" 1265 " as it wants to be stalled for %d more cycles\n", 1266 *inst, inst->minimumCommitCycle - now); 1267 completed_inst = false; 1268 } else { 1269 completed_inst = commitInst(inst, 1270 early_memory_issue, branch, fault, 1271 committed_inst, issued_mem_ref); 1272 } 1273 } else { 1274 /* Discard instruction */ 1275 completed_inst = true; 1276 } 1277 1278 if (completed_inst) { 1279 /* Allow the pipeline to advance. If the FU head 1280 * instruction wasn't the inFlightInsts head 1281 * but had already been committed, it would have 1282 * unstalled the pipeline before here */ 1283 if (inst->fuIndex != noCostFUIndex) { 1284 DPRINTF(MinorExecute, "Unstalling %d for inst %s\n", inst->fuIndex, inst->id); 1285 funcUnits[inst->fuIndex]->stalled = false; 1286 } 1287 } 1288 } 1289 } else { 1290 DPRINTF(MinorExecute, "No instructions to commit\n"); 1291 completed_inst = false; 1292 } 1293 1294 /* All discardable instructions must also be 'completed' by now */ 1295 assert(!(discard_inst && !completed_inst)); 1296 1297 /* Instruction committed but was discarded due to streamSeqNum 1298 * mismatch */ 1299 if (discard_inst) { 1300 DPRINTF(MinorExecute, "Discarding inst: %s as its stream" 1301 " state was unexpected, expected: %d\n", 1302 *inst, ex_info.streamSeqNum); 1303 1304 if (fault == NoFault) 1305 cpu.stats.numDiscardedOps++; 1306 } 1307 1308 /* Mark the mem inst as being in the LSQ */ 1309 if (issued_mem_ref) { 1310 inst->fuIndex = 0; 1311 inst->inLSQ = true; 1312 } 1313 1314 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts 1315 * as they've *definitely* exited the FUs */ 1316 if (completed_inst && inst->isMemRef()) { 1317 /* The MemRef could have been discarded from the FU or the memory 1318 * queue, so just check an FU instruction */ 1319 if (!ex_info.inFUMemInsts->empty() && 1320 ex_info.inFUMemInsts->front().inst == inst) 1321 { 1322 ex_info.inFUMemInsts->pop(); 1323 } 1324 } 1325 1326 if (completed_inst && !(issued_mem_ref && fault == NoFault)) { 1327 /* Note that this includes discarded insts */ 1328 DPRINTF(MinorExecute, "Completed inst: %s\n", *inst); 1329 1330 /* Got to the end of a full instruction? */ 1331 ex_info.lastCommitWasEndOfMacroop = inst->isFault() || 1332 inst->isLastOpInInst(); 1333 1334 /* lastPredictionSeqNum is kept as a convenience to prevent its 1335 * value from changing too much on the minorview display */ 1336 ex_info.lastPredictionSeqNum = inst->id.predictionSeqNum; 1337 1338 /* Finished with the inst, remove it from the inst queue and 1339 * clear its dependencies */ 1340 ex_info.inFlightInsts->pop(); 1341 1342 /* Complete barriers in the LSQ/move to store buffer */ 1343 if (inst->isInst() && inst->staticInst->isMemBarrier()) { 1344 DPRINTF(MinorMem, "Completing memory barrier" 1345 " inst: %s committed: %d\n", *inst, committed_inst); 1346 lsq.completeMemBarrierInst(inst, committed_inst); 1347 } 1348 1349 scoreboard[thread_id].clearInstDests(inst, inst->isMemRef()); 1350 } 1351 1352 /* Handle per-cycle instruction counting */ 1353 if (committed_inst) { 1354 bool is_no_cost_inst = inst->isNoCostInst(); 1355 1356 /* Don't show no cost instructions as having taken a commit 1357 * slot */ 1358 if (DTRACE(MinorTrace) && !is_no_cost_inst) 1359 ex_info.instsBeingCommitted.insts[num_insts_committed] = inst; 1360 1361 if (!is_no_cost_inst) 1362 num_insts_committed++; 1363 1364 if (num_insts_committed == commitLimit) 1365 DPRINTF(MinorExecute, "Reached inst commit limit\n"); 1366 1367 /* Re-set the time of the instruction if that's required for 1368 * tracing */ 1369 if (inst->traceData) { 1370 if (setTraceTimeOnCommit) 1371 inst->traceData->setWhen(curTick()); 1372 inst->traceData->dump(); 1373 } 1374 1375 if (completed_mem_ref) 1376 num_mem_refs_committed++; 1377 1378 if (num_mem_refs_committed == memoryCommitLimit) 1379 DPRINTF(MinorExecute, "Reached mem ref commit limit\n"); 1380 } 1381 } 1382} 1383 1384bool 1385Execute::isInbetweenInsts(ThreadID thread_id) const 1386{ 1387 return executeInfo[thread_id].lastCommitWasEndOfMacroop && 1388 !lsq.accessesInFlight(); 1389} 1390 1391void 1392Execute::evaluate() 1393{ 1394 if (!inp.outputWire->isBubble()) 1395 inputBuffer[inp.outputWire->threadId].setTail(*inp.outputWire); 1396 1397 BranchData &branch = *out.inputWire; 1398 1399 unsigned int num_issued = 0; 1400 1401 /* Do all the cycle-wise activities for dcachePort here to potentially 1402 * free up input spaces in the LSQ's requests queue */ 1403 lsq.step(); 1404 1405 /* Check interrupts first. Will halt commit if interrupt found */ 1406 bool interrupted = false; 1407 ThreadID interrupt_tid = checkInterrupts(branch, interrupted); 1408 1409 if (interrupt_tid != InvalidThreadID) { 1410 /* Signalling an interrupt this cycle, not issuing/committing from 1411 * any other threads */ 1412 } else if (!branch.isBubble()) { 1413 /* It's important that this is here to carry Fetch1 wakeups to Fetch1 1414 * without overwriting them */ 1415 DPRINTF(MinorInterrupt, "Execute skipping a cycle to allow old" 1416 " branch to complete\n"); 1417 } else { 1418 ThreadID commit_tid = getCommittingThread(); 1419 1420 if (commit_tid != InvalidThreadID) { 1421 ExecuteThreadInfo& commit_info = executeInfo[commit_tid]; 1422 1423 DPRINTF(MinorExecute, "Attempting to commit [tid:%d]\n", 1424 commit_tid); 1425 /* commit can set stalled flags observable to issue and so *must* be 1426 * called first */ 1427 if (commit_info.drainState != NotDraining) { 1428 if (commit_info.drainState == DrainCurrentInst) { 1429 /* Commit only micro-ops, don't kill anything else */ 1430 commit(commit_tid, true, false, branch); 1431 1432 if (isInbetweenInsts(commit_tid)) 1433 setDrainState(commit_tid, DrainHaltFetch); 1434 1435 /* Discard any generated branch */ 1436 branch = BranchData::bubble(); 1437 } else if (commit_info.drainState == DrainAllInsts) { 1438 /* Kill all instructions */ 1439 while (getInput(commit_tid)) 1440 popInput(commit_tid); 1441 commit(commit_tid, false, true, branch); 1442 } 1443 } else { 1444 /* Commit micro-ops only if interrupted. Otherwise, commit 1445 * anything you like */ 1446 DPRINTF(MinorExecute, "Committing micro-ops for interrupt[tid:%d]\n", 1447 commit_tid); 1448 bool only_commit_microops = interrupted && 1449 hasInterrupt(commit_tid); 1450 commit(commit_tid, only_commit_microops, false, branch); 1451 } 1452 1453 /* Halt fetch, but don't do it until we have the current instruction in 1454 * the bag */ 1455 if (commit_info.drainState == DrainHaltFetch) { 1456 updateBranchData(commit_tid, BranchData::HaltFetch, 1457 MinorDynInst::bubble(), TheISA::PCState(0), branch); 1458 1459 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1460 setDrainState(commit_tid, DrainAllInsts); 1461 } 1462 } 1463 ThreadID issue_tid = getIssuingThread(); 1464 /* This will issue merrily even when interrupted in the sure and 1465 * certain knowledge that the interrupt with change the stream */ 1466 if (issue_tid != InvalidThreadID) { 1467 DPRINTF(MinorExecute, "Attempting to issue [tid:%d]\n", 1468 issue_tid); 1469 num_issued = issue(issue_tid); 1470 } 1471 1472 } 1473 1474 /* Run logic to step functional units + decide if we are active on the next 1475 * clock cycle */ 1476 std::vector<MinorDynInstPtr> next_issuable_insts; 1477 bool can_issue_next = false; 1478 1479 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1480 /* Find the next issuable instruction for each thread and see if it can 1481 be issued */ 1482 if (getInput(tid)) { 1483 unsigned int input_index = executeInfo[tid].inputIndex; 1484 MinorDynInstPtr inst = getInput(tid)->insts[input_index]; 1485 if (inst->isFault()) { 1486 can_issue_next = true; 1487 } else if (!inst->isBubble()) { 1488 if (cpu.getContext(tid)->status() != ThreadContext::Suspended) { 1489 next_issuable_insts.push_back(inst); 1490 } 1491 } 1492 } 1493 } 1494 1495 bool becoming_stalled = true; 1496 1497 /* Advance the pipelines and note whether they still need to be 1498 * advanced */ 1499 for (unsigned int i = 0; i < numFuncUnits; i++) { 1500 FUPipeline *fu = funcUnits[i]; 1501 fu->advance(); 1502 1503 /* If we need to tick again, the pipeline will have been left or set 1504 * to be unstalled */ 1505 if (fu->occupancy !=0 && !fu->stalled) 1506 becoming_stalled = false; 1507 1508 /* Could we possibly issue the next instruction from any thread? 1509 * This is quite an expensive test and is only used to determine 1510 * if the CPU should remain active, only run it if we aren't sure 1511 * we are active next cycle yet */ 1512 for (auto inst : next_issuable_insts) { 1513 if (!fu->stalled && fu->provides(inst->staticInst->opClass()) && 1514 scoreboard[inst->id.threadId].canInstIssue(inst, 1515 NULL, NULL, cpu.curCycle() + Cycles(1), 1516 cpu.getContext(inst->id.threadId))) { 1517 can_issue_next = true; 1518 break; 1519 } 1520 } 1521 } 1522 1523 bool head_inst_might_commit = false; 1524 1525 /* Could the head in flight insts be committed */ 1526 for (auto const &info : executeInfo) { 1527 if (!info.inFlightInsts->empty()) { 1528 const QueuedInst &head_inst = info.inFlightInsts->front(); 1529 1530 if (head_inst.inst->isNoCostInst()) { 1531 head_inst_might_commit = true; 1532 } else { 1533 FUPipeline *fu = funcUnits[head_inst.inst->fuIndex]; 1534 if ((fu->stalled && 1535 fu->front().inst->id == head_inst.inst->id) || 1536 lsq.findResponse(head_inst.inst)) 1537 { 1538 head_inst_might_commit = true; 1539 break; 1540 } 1541 } 1542 } 1543 } 1544 1545 DPRINTF(Activity, "Need to tick num issued insts: %s%s%s%s%s%s\n", 1546 (num_issued != 0 ? " (issued some insts)" : ""), 1547 (becoming_stalled ? "(becoming stalled)" : "(not becoming stalled)"), 1548 (can_issue_next ? " (can issued next inst)" : ""), 1549 (head_inst_might_commit ? "(head inst might commit)" : ""), 1550 (lsq.needsToTick() ? " (LSQ needs to tick)" : ""), 1551 (interrupted ? " (interrupted)" : "")); 1552 1553 bool need_to_tick = 1554 num_issued != 0 || /* Issued some insts this cycle */ 1555 !becoming_stalled || /* Some FU pipelines can still move */ 1556 can_issue_next || /* Can still issue a new inst */ 1557 head_inst_might_commit || /* Could possible commit the next inst */ 1558 lsq.needsToTick() || /* Must step the dcache port */ 1559 interrupted; /* There are pending interrupts */ 1560 1561 if (!need_to_tick) { 1562 DPRINTF(Activity, "The next cycle might be skippable as there are no" 1563 " advanceable FUs\n"); 1564 } 1565 1566 /* Wake up if we need to tick again */ 1567 if (need_to_tick) 1568 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1569 1570 /* Note activity of following buffer */ 1571 if (!branch.isBubble()) 1572 cpu.activityRecorder->activity(); 1573 1574 /* Make sure the input (if any left) is pushed */ 1575 if (!inp.outputWire->isBubble()) 1576 inputBuffer[inp.outputWire->threadId].pushTail(); 1577} 1578 1579ThreadID 1580Execute::checkInterrupts(BranchData& branch, bool& interrupted) 1581{ 1582 ThreadID tid = interruptPriority; 1583 /* Evaluate interrupts in round-robin based upon service */ 1584 do { 1585 /* Has an interrupt been signalled? This may not be acted on 1586 * straighaway so this is different from took_interrupt */ 1587 bool thread_interrupted = false; 1588 1589 if (FullSystem && cpu.getInterruptController(tid)) { 1590 /* This is here because it seems that after drainResume the 1591 * interrupt controller isn't always set */ 1592 thread_interrupted = executeInfo[tid].drainState == NotDraining && 1593 isInterrupted(tid); 1594 interrupted = interrupted || thread_interrupted; 1595 } else { 1596 DPRINTF(MinorInterrupt, "No interrupt controller\n"); 1597 } 1598 DPRINTF(MinorInterrupt, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n", 1599 tid, thread_interrupted, isInbetweenInsts(tid)); 1600 /* Act on interrupts */ 1601 if (thread_interrupted && isInbetweenInsts(tid)) { 1602 if (takeInterrupt(tid, branch)) { 1603 interruptPriority = tid; 1604 return tid; 1605 } 1606 } else { 1607 tid = (tid + 1) % cpu.numThreads; 1608 } 1609 } while (tid != interruptPriority); 1610 1611 return InvalidThreadID; 1612} 1613 1614bool 1615Execute::hasInterrupt(ThreadID thread_id) 1616{ 1617 if (FullSystem && cpu.getInterruptController(thread_id)) { 1618 return executeInfo[thread_id].drainState == NotDraining && 1619 isInterrupted(thread_id); 1620 } 1621 1622 return false; 1623} 1624 1625void 1626Execute::minorTrace() const 1627{ 1628 std::ostringstream insts; 1629 std::ostringstream stalled; 1630 1631 executeInfo[0].instsBeingCommitted.reportData(insts); 1632 lsq.minorTrace(); 1633 inputBuffer[0].minorTrace(); 1634 scoreboard[0].minorTrace(); 1635 1636 /* Report functional unit stalling in one string */ 1637 unsigned int i = 0; 1638 while (i < numFuncUnits) 1639 { 1640 stalled << (funcUnits[i]->stalled ? '1' : 'E'); 1641 i++; 1642 if (i != numFuncUnits) 1643 stalled << ','; 1644 } 1645 1646 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d" 1647 " stalled=%s drainState=%d isInbetweenInsts=%d\n", 1648 insts.str(), executeInfo[0].inputIndex, executeInfo[0].streamSeqNum, 1649 stalled.str(), executeInfo[0].drainState, isInbetweenInsts(0)); 1650 1651 std::for_each(funcUnits.begin(), funcUnits.end(), 1652 std::mem_fun(&FUPipeline::minorTrace)); 1653 1654 executeInfo[0].inFlightInsts->minorTrace(); 1655 executeInfo[0].inFUMemInsts->minorTrace(); 1656} 1657 1658inline ThreadID 1659Execute::getCommittingThread() 1660{ 1661 std::vector<ThreadID> priority_list; 1662 1663 switch (cpu.threadPolicy) { 1664 case Enums::SingleThreaded: 1665 return 0; 1666 case Enums::RoundRobin: 1667 priority_list = cpu.roundRobinPriority(commitPriority); 1668 break; 1669 case Enums::Random: 1670 priority_list = cpu.randomPriority(); 1671 break; 1672 default: 1673 panic("Invalid thread policy"); 1674 } 1675 1676 for (auto tid : priority_list) { 1677 ExecuteThreadInfo &ex_info = executeInfo[tid]; 1678 bool can_commit_insts = !ex_info.inFlightInsts->empty(); 1679 if (can_commit_insts) { 1680 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front()); 1681 MinorDynInstPtr inst = head_inflight_inst->inst; 1682 1683 can_commit_insts = can_commit_insts && 1684 (!inst->inLSQ || (lsq.findResponse(inst) != NULL)); 1685 1686 if (!inst->inLSQ) { 1687 bool can_transfer_mem_inst = false; 1688 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) { 1689 const MinorDynInstPtr head_mem_ref_inst = 1690 ex_info.inFUMemInsts->front().inst; 1691 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex]; 1692 const MinorDynInstPtr &fu_inst = fu->front().inst; 1693 can_transfer_mem_inst = 1694 !fu_inst->isBubble() && 1695 fu_inst->id.threadId == tid && 1696 !fu_inst->inLSQ && 1697 fu_inst->canEarlyIssue && 1698 inst->id.execSeqNum > fu_inst->instToWaitFor; 1699 } 1700 1701 bool can_execute_fu_inst = inst->fuIndex == noCostFUIndex; 1702 if (can_commit_insts && !can_transfer_mem_inst && 1703 inst->fuIndex != noCostFUIndex) 1704 { 1705 QueuedInst& fu_inst = funcUnits[inst->fuIndex]->front(); 1706 can_execute_fu_inst = !fu_inst.inst->isBubble() && 1707 fu_inst.inst->id == inst->id; 1708 } 1709 1710 can_commit_insts = can_commit_insts && 1711 (can_transfer_mem_inst || can_execute_fu_inst); 1712 } 1713 } 1714 1715 1716 if (can_commit_insts) { 1717 commitPriority = tid; 1718 return tid; 1719 } 1720 } 1721 1722 return InvalidThreadID; 1723} 1724 1725inline ThreadID 1726Execute::getIssuingThread() 1727{ 1728 std::vector<ThreadID> priority_list; 1729 1730 switch (cpu.threadPolicy) { 1731 case Enums::SingleThreaded: 1732 return 0; 1733 case Enums::RoundRobin: 1734 priority_list = cpu.roundRobinPriority(issuePriority); 1735 break; 1736 case Enums::Random: 1737 priority_list = cpu.randomPriority(); 1738 break; 1739 default: 1740 panic("Invalid thread scheduling policy."); 1741 } 1742 1743 for (auto tid : priority_list) { 1744 if (cpu.getContext(tid)->status() == ThreadContext::Active && 1745 getInput(tid)) { 1746 issuePriority = tid; 1747 return tid; 1748 } 1749 } 1750 1751 return InvalidThreadID; 1752} 1753 1754void 1755Execute::drainResume() 1756{ 1757 DPRINTF(Drain, "MinorExecute drainResume\n"); 1758 1759 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1760 setDrainState(tid, NotDraining); 1761 } 1762 1763 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1764} 1765 1766std::ostream &operator <<(std::ostream &os, Execute::DrainState state) 1767{ 1768 switch (state) 1769 { 1770 case Execute::NotDraining: 1771 os << "NotDraining"; 1772 break; 1773 case Execute::DrainCurrentInst: 1774 os << "DrainCurrentInst"; 1775 break; 1776 case Execute::DrainHaltFetch: 1777 os << "DrainHaltFetch"; 1778 break; 1779 case Execute::DrainAllInsts: 1780 os << "DrainAllInsts"; 1781 break; 1782 default: 1783 os << "Drain-" << static_cast<int>(state); 1784 break; 1785 } 1786 1787 return os; 1788} 1789 1790void 1791Execute::setDrainState(ThreadID thread_id, DrainState state) 1792{ 1793 DPRINTF(Drain, "setDrainState[%d]: %s\n", thread_id, state); 1794 executeInfo[thread_id].drainState = state; 1795} 1796 1797unsigned int 1798Execute::drain() 1799{ 1800 DPRINTF(Drain, "MinorExecute drain\n"); 1801 1802 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1803 if (executeInfo[tid].drainState == NotDraining) { 1804 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1805 1806 /* Go to DrainCurrentInst if we're between microops 1807 * or waiting on an unbufferable memory operation. 1808 * Otherwise we can go straight to DrainHaltFetch 1809 */ 1810 if (isInbetweenInsts(tid)) 1811 setDrainState(tid, DrainHaltFetch); 1812 else 1813 setDrainState(tid, DrainCurrentInst); 1814 } 1815 } 1816 return (isDrained() ? 0 : 1); 1817} 1818 1819bool 1820Execute::isDrained() 1821{ 1822 if (!lsq.isDrained()) 1823 return false; 1824 1825 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1826 if (executeInfo[tid].drainState != DrainAllInsts || 1827 !inputBuffer[tid].empty() || 1828 !executeInfo[tid].inFlightInsts->empty()) { 1829 1830 return false; 1831 } 1832 } 1833 1834 return true; 1835} 1836 1837Execute::~Execute() 1838{ 1839 for (unsigned int i = 0; i < numFuncUnits; i++) 1840 delete funcUnits[i]; 1841 1842 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) 1843 delete executeInfo[tid].inFlightInsts; 1844} 1845 1846bool 1847Execute::instIsRightStream(MinorDynInstPtr inst) 1848{ 1849 return inst->id.streamSeqNum == executeInfo[inst->id.threadId].streamSeqNum; 1850} 1851 1852bool 1853Execute::instIsHeadInst(MinorDynInstPtr inst) 1854{ 1855 bool ret = false; 1856 1857 if (!executeInfo[inst->id.threadId].inFlightInsts->empty()) 1858 ret = executeInfo[inst->id.threadId].inFlightInsts->front().inst->id == inst->id; 1859 1860 return ret; 1861} 1862 1863MinorCPU::MinorCPUPort & 1864Execute::getDcachePort() 1865{ 1866 return lsq.getDcachePort(); 1867} 1868 1869} 1870