execute.cc revision 13818
110152Satgutier@umich.edu/* 210152Satgutier@umich.edu * Copyright (c) 2013-2014 ARM Limited 310152Satgutier@umich.edu * All rights reserved 410152Satgutier@umich.edu * 510234Syasuko.eckert@amd.com * The license below extends only to copyright in the software and shall 610152Satgutier@umich.edu * not be construed as granting a license to any other intellectual 710152Satgutier@umich.edu * property including but not limited to intellectual property relating 810152Satgutier@umich.edu * to a hardware implementation of the functionality of the software 910152Satgutier@umich.edu * licensed hereunder. You may use the software subject to the license 1010152Satgutier@umich.edu * terms below provided that you ensure that this notice is replicated 1110152Satgutier@umich.edu * unmodified and in its entirety in all distributions of the software, 1210152Satgutier@umich.edu * modified or unmodified, in source code or in binary form. 1310152Satgutier@umich.edu * 1410152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 1510152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 1610152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 1710152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 1810152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1910152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 2010152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 2110152Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 2210152Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 2310152Satgutier@umich.edu * this software without specific prior written permission. 2410152Satgutier@umich.edu * 2510152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910234Syasuko.eckert@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310234Syasuko.eckert@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510152Satgutier@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610152Satgutier@umich.edu * 3710234Syasuko.eckert@amd.com * Authors: Andrew Bardsley 3810234Syasuko.eckert@amd.com */ 3910234Syasuko.eckert@amd.com 4010234Syasuko.eckert@amd.com#include "cpu/minor/execute.hh" 4110234Syasuko.eckert@amd.com 4210234Syasuko.eckert@amd.com#include "arch/locked_mem.hh" 4310234Syasuko.eckert@amd.com#include "arch/registers.hh" 4410234Syasuko.eckert@amd.com#include "arch/utility.hh" 4510234Syasuko.eckert@amd.com#include "cpu/minor/cpu.hh" 4610234Syasuko.eckert@amd.com#include "cpu/minor/exec_context.hh" 4710234Syasuko.eckert@amd.com#include "cpu/minor/fetch1.hh" 4810234Syasuko.eckert@amd.com#include "cpu/minor/lsq.hh" 4910234Syasuko.eckert@amd.com#include "cpu/op_class.hh" 5010234Syasuko.eckert@amd.com#include "debug/Activity.hh" 5110234Syasuko.eckert@amd.com#include "debug/Branch.hh" 5210234Syasuko.eckert@amd.com#include "debug/Drain.hh" 5310152Satgutier@umich.edu#include "debug/MinorExecute.hh" 5410152Satgutier@umich.edu#include "debug/MinorInterrupt.hh" 5510234Syasuko.eckert@amd.com#include "debug/MinorMem.hh" 5610234Syasuko.eckert@amd.com#include "debug/MinorTrace.hh" 5710234Syasuko.eckert@amd.com#include "debug/PCEvent.hh" 5810234Syasuko.eckert@amd.com 5910234Syasuko.eckert@amd.comnamespace Minor 6010234Syasuko.eckert@amd.com{ 6110234Syasuko.eckert@amd.com 6210234Syasuko.eckert@amd.comExecute::Execute(const std::string &name_, 6310234Syasuko.eckert@amd.com MinorCPU &cpu_, 6410234Syasuko.eckert@amd.com MinorCPUParams ¶ms, 6510234Syasuko.eckert@amd.com Latch<ForwardInstData>::Output inp_, 6610234Syasuko.eckert@amd.com Latch<BranchData>::Input out_) : 6710234Syasuko.eckert@amd.com Named(name_), 6810234Syasuko.eckert@amd.com inp(inp_), 6910234Syasuko.eckert@amd.com out(out_), 7010234Syasuko.eckert@amd.com cpu(cpu_), 7110234Syasuko.eckert@amd.com issueLimit(params.executeIssueLimit), 7210234Syasuko.eckert@amd.com memoryIssueLimit(params.executeMemoryIssueLimit), 7310234Syasuko.eckert@amd.com commitLimit(params.executeCommitLimit), 7410234Syasuko.eckert@amd.com memoryCommitLimit(params.executeMemoryCommitLimit), 7510234Syasuko.eckert@amd.com processMoreThanOneInput(params.executeCycleInput), 7610234Syasuko.eckert@amd.com fuDescriptions(*params.executeFuncUnits), 7710234Syasuko.eckert@amd.com numFuncUnits(fuDescriptions.funcUnits.size()), 7810234Syasuko.eckert@amd.com setTraceTimeOnCommit(params.executeSetTraceTimeOnCommit), 7910234Syasuko.eckert@amd.com setTraceTimeOnIssue(params.executeSetTraceTimeOnIssue), 8010234Syasuko.eckert@amd.com allowEarlyMemIssue(params.executeAllowEarlyMemoryIssue), 8110234Syasuko.eckert@amd.com noCostFUIndex(fuDescriptions.funcUnits.size() + 1), 8210234Syasuko.eckert@amd.com lsq(name_ + ".lsq", name_ + ".dcache_port", 8310234Syasuko.eckert@amd.com cpu_, *this, 8410234Syasuko.eckert@amd.com params.executeMaxAccessesInMemory, 8510234Syasuko.eckert@amd.com params.executeMemoryWidth, 8610234Syasuko.eckert@amd.com params.executeLSQRequestsQueueSize, 8710234Syasuko.eckert@amd.com params.executeLSQTransfersQueueSize, 8810234Syasuko.eckert@amd.com params.executeLSQStoreBufferSize, 8910234Syasuko.eckert@amd.com params.executeLSQMaxStoreBufferStoresPerCycle), 9010234Syasuko.eckert@amd.com executeInfo(params.numThreads, ExecuteThreadInfo(params.executeCommitLimit)), 9110234Syasuko.eckert@amd.com interruptPriority(0), 9210234Syasuko.eckert@amd.com issuePriority(0), 9310234Syasuko.eckert@amd.com commitPriority(0) 9410234Syasuko.eckert@amd.com{ 9510234Syasuko.eckert@amd.com if (commitLimit < 1) { 9610234Syasuko.eckert@amd.com fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_, 9710234Syasuko.eckert@amd.com commitLimit); 9810234Syasuko.eckert@amd.com } 9910234Syasuko.eckert@amd.com 10010234Syasuko.eckert@amd.com if (issueLimit < 1) { 10110234Syasuko.eckert@amd.com fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_, 10210234Syasuko.eckert@amd.com issueLimit); 10310234Syasuko.eckert@amd.com } 10410234Syasuko.eckert@amd.com 10510234Syasuko.eckert@amd.com if (memoryIssueLimit < 1) { 10610234Syasuko.eckert@amd.com fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_, 10710234Syasuko.eckert@amd.com memoryIssueLimit); 10810234Syasuko.eckert@amd.com } 10910234Syasuko.eckert@amd.com 11010234Syasuko.eckert@amd.com if (memoryCommitLimit > commitLimit) { 11110234Syasuko.eckert@amd.com fatal("%s: executeMemoryCommitLimit (%d) must be <=" 11210234Syasuko.eckert@amd.com " executeCommitLimit (%d)\n", 11310234Syasuko.eckert@amd.com name_, memoryCommitLimit, commitLimit); 11410234Syasuko.eckert@amd.com } 11510234Syasuko.eckert@amd.com 11610234Syasuko.eckert@amd.com if (params.executeInputBufferSize < 1) { 11710234Syasuko.eckert@amd.com fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_, 11810234Syasuko.eckert@amd.com params.executeInputBufferSize); 11910234Syasuko.eckert@amd.com } 12010234Syasuko.eckert@amd.com 12110234Syasuko.eckert@amd.com if (params.executeInputBufferSize < 1) { 12210234Syasuko.eckert@amd.com fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_, 12310234Syasuko.eckert@amd.com params.executeInputBufferSize); 12410234Syasuko.eckert@amd.com } 12510234Syasuko.eckert@amd.com 12610234Syasuko.eckert@amd.com /* This should be large enough to count all the in-FU instructions 12710234Syasuko.eckert@amd.com * which need to be accounted for in the inFlightInsts 12810234Syasuko.eckert@amd.com * queue */ 12910234Syasuko.eckert@amd.com unsigned int total_slots = 0; 13010234Syasuko.eckert@amd.com 13110234Syasuko.eckert@amd.com /* Make FUPipelines for each MinorFU */ 13210234Syasuko.eckert@amd.com for (unsigned int i = 0; i < numFuncUnits; i++) { 13310234Syasuko.eckert@amd.com std::ostringstream fu_name; 13410234Syasuko.eckert@amd.com MinorFU *fu_description = fuDescriptions.funcUnits[i]; 13510234Syasuko.eckert@amd.com 13610234Syasuko.eckert@amd.com /* Note the total number of instruction slots (for sizing 13710234Syasuko.eckert@amd.com * the inFlightInst queue) and the maximum latency of any FU 13810234Syasuko.eckert@amd.com * (for sizing the activity recorder) */ 13910234Syasuko.eckert@amd.com total_slots += fu_description->opLat; 14010152Satgutier@umich.edu 14110152Satgutier@umich.edu fu_name << name_ << ".fu." << i; 14210234Syasuko.eckert@amd.com 14310234Syasuko.eckert@amd.com FUPipeline *fu = new FUPipeline(fu_name.str(), *fu_description, cpu); 14410234Syasuko.eckert@amd.com 14510234Syasuko.eckert@amd.com funcUnits.push_back(fu); 14610234Syasuko.eckert@amd.com } 14710234Syasuko.eckert@amd.com 14810152Satgutier@umich.edu /** Check that there is a functional unit for all operation classes */ 14910234Syasuko.eckert@amd.com for (int op_class = No_OpClass + 1; op_class < Num_OpClasses; op_class++) { 15010234Syasuko.eckert@amd.com bool found_fu = false; 15110234Syasuko.eckert@amd.com unsigned int fu_index = 0; 15210234Syasuko.eckert@amd.com 15310234Syasuko.eckert@amd.com while (fu_index < numFuncUnits && !found_fu) 15410234Syasuko.eckert@amd.com { 15510234Syasuko.eckert@amd.com if (funcUnits[fu_index]->provides( 15610234Syasuko.eckert@amd.com static_cast<OpClass>(op_class))) 15710234Syasuko.eckert@amd.com { 15810234Syasuko.eckert@amd.com found_fu = true; 15910234Syasuko.eckert@amd.com } 16010234Syasuko.eckert@amd.com fu_index++; 16110234Syasuko.eckert@amd.com } 16210234Syasuko.eckert@amd.com 16310152Satgutier@umich.edu if (!found_fu) { 16410234Syasuko.eckert@amd.com warn("No functional unit for OpClass %s\n", 16510234Syasuko.eckert@amd.com Enums::OpClassStrings[op_class]); 16610234Syasuko.eckert@amd.com } 16710152Satgutier@umich.edu } 16810234Syasuko.eckert@amd.com 16910234Syasuko.eckert@amd.com /* Per-thread structures */ 17010234Syasuko.eckert@amd.com for (ThreadID tid = 0; tid < params.numThreads; tid++) { 17110234Syasuko.eckert@amd.com std::string tid_str = std::to_string(tid); 17210234Syasuko.eckert@amd.com 17310234Syasuko.eckert@amd.com /* Input Buffers */ 17410234Syasuko.eckert@amd.com inputBuffer.push_back( 17510234Syasuko.eckert@amd.com InputBuffer<ForwardInstData>( 17610234Syasuko.eckert@amd.com name_ + ".inputBuffer" + tid_str, "insts", 17710234Syasuko.eckert@amd.com params.executeInputBufferSize)); 17810234Syasuko.eckert@amd.com 17910234Syasuko.eckert@amd.com /* Scoreboards */ 18010152Satgutier@umich.edu scoreboard.push_back(Scoreboard(name_ + ".scoreboard" + tid_str)); 18110152Satgutier@umich.edu 18210152Satgutier@umich.edu /* In-flight instruction records */ 18310234Syasuko.eckert@amd.com executeInfo[tid].inFlightInsts = new Queue<QueuedInst, 18410234Syasuko.eckert@amd.com ReportTraitsAdaptor<QueuedInst> >( 18510234Syasuko.eckert@amd.com name_ + ".inFlightInsts" + tid_str, "insts", total_slots); 18610234Syasuko.eckert@amd.com 18710234Syasuko.eckert@amd.com executeInfo[tid].inFUMemInsts = new Queue<QueuedInst, 18810234Syasuko.eckert@amd.com ReportTraitsAdaptor<QueuedInst> >( 18910234Syasuko.eckert@amd.com name_ + ".inFUMemInsts" + tid_str, "insts", total_slots); 19010152Satgutier@umich.edu } 19110234Syasuko.eckert@amd.com} 19210152Satgutier@umich.edu 19310234Syasuko.eckert@amd.comconst ForwardInstData * 19410234Syasuko.eckert@amd.comExecute::getInput(ThreadID tid) 19510234Syasuko.eckert@amd.com{ 19610234Syasuko.eckert@amd.com /* Get a line from the inputBuffer to work with */ 19710152Satgutier@umich.edu if (!inputBuffer[tid].empty()) { 19810234Syasuko.eckert@amd.com const ForwardInstData &head = inputBuffer[tid].front(); 19910234Syasuko.eckert@amd.com 20010234Syasuko.eckert@amd.com return (head.isBubble() ? NULL : &(inputBuffer[tid].front())); 20110234Syasuko.eckert@amd.com } else { 20210234Syasuko.eckert@amd.com return NULL; 20310234Syasuko.eckert@amd.com } 20410152Satgutier@umich.edu} 20510152Satgutier@umich.edu 20610152Satgutier@umich.eduvoid 20710152Satgutier@umich.eduExecute::popInput(ThreadID tid) 20810152Satgutier@umich.edu{ 20910234Syasuko.eckert@amd.com if (!inputBuffer[tid].empty()) 21010234Syasuko.eckert@amd.com inputBuffer[tid].pop(); 21110152Satgutier@umich.edu 21210234Syasuko.eckert@amd.com executeInfo[tid].inputIndex = 0; 21310234Syasuko.eckert@amd.com} 21410234Syasuko.eckert@amd.com 21510234Syasuko.eckert@amd.comvoid 21610234Syasuko.eckert@amd.comExecute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch) 21710234Syasuko.eckert@amd.com{ 21810234Syasuko.eckert@amd.com ThreadContext *thread = cpu.getContext(inst->id.threadId); 21910152Satgutier@umich.edu const TheISA::PCState &pc_before = inst->pc; 22010234Syasuko.eckert@amd.com TheISA::PCState target = thread->pcState(); 22110234Syasuko.eckert@amd.com 22210234Syasuko.eckert@amd.com /* Force a branch for SerializeAfter/SquashAfter instructions 22310234Syasuko.eckert@amd.com * at the end of micro-op sequence when we're not suspended */ 22410234Syasuko.eckert@amd.com bool force_branch = thread->status() != ThreadContext::Suspended && 22510234Syasuko.eckert@amd.com !inst->isFault() && 22610234Syasuko.eckert@amd.com inst->isLastOpInInst() && 22710234Syasuko.eckert@amd.com (inst->staticInst->isSerializeAfter() || 22810152Satgutier@umich.edu inst->staticInst->isSquashAfter() || 22910152Satgutier@umich.edu inst->staticInst->isIprAccess()); 23010152Satgutier@umich.edu 23110152Satgutier@umich.edu DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n", 23210152Satgutier@umich.edu pc_before, target, (force_branch ? " (forcing)" : "")); 23310152Satgutier@umich.edu 23410234Syasuko.eckert@amd.com /* Will we change the PC to something other than the next instruction? */ 23510152Satgutier@umich.edu bool must_branch = pc_before != target || 23610152Satgutier@umich.edu fault != NoFault || 23710234Syasuko.eckert@amd.com force_branch; 23810234Syasuko.eckert@amd.com 23910234Syasuko.eckert@amd.com /* The reason for the branch data we're about to generate, set below */ 24010234Syasuko.eckert@amd.com BranchData::Reason reason = BranchData::NoBranch; 24110234Syasuko.eckert@amd.com 24210234Syasuko.eckert@amd.com if (fault == NoFault) 24310152Satgutier@umich.edu { 24410234Syasuko.eckert@amd.com TheISA::advancePC(target, inst->staticInst); 24510234Syasuko.eckert@amd.com thread->pcState(target); 24610234Syasuko.eckert@amd.com 24710234Syasuko.eckert@amd.com DPRINTF(Branch, "Advancing current PC from: %s to: %s\n", 24810234Syasuko.eckert@amd.com pc_before, target); 24910234Syasuko.eckert@amd.com } 25010152Satgutier@umich.edu 25110152Satgutier@umich.edu if (thread->status() == ThreadContext::Suspended) { 25210152Satgutier@umich.edu /* Thread got suspended */ 25310152Satgutier@umich.edu DPRINTF(Branch, "Thread got suspended: branch from 0x%x to 0x%x " 25410234Syasuko.eckert@amd.com "inst: %s\n", 25510234Syasuko.eckert@amd.com inst->pc.instAddr(), target.instAddr(), *inst); 25610234Syasuko.eckert@amd.com 25710234Syasuko.eckert@amd.com reason = BranchData::SuspendThread; 25810234Syasuko.eckert@amd.com } else if (inst->predictedTaken && !force_branch) { 25910234Syasuko.eckert@amd.com /* Predicted to branch */ 26010234Syasuko.eckert@amd.com if (!must_branch) { 26110234Syasuko.eckert@amd.com /* No branch was taken, change stream to get us back to the 26210234Syasuko.eckert@amd.com * intended PC value */ 26310234Syasuko.eckert@amd.com DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x but" 26410234Syasuko.eckert@amd.com " none happened inst: %s\n", 26510234Syasuko.eckert@amd.com inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst); 26610234Syasuko.eckert@amd.com 26710234Syasuko.eckert@amd.com reason = BranchData::BadlyPredictedBranch; 26810152Satgutier@umich.edu } else if (inst->predictedTarget == target) { 26910152Satgutier@umich.edu /* Branch prediction got the right target, kill the branch and 27010152Satgutier@umich.edu * carry on. 27110152Satgutier@umich.edu * Note that this information to the branch predictor might get 27210152Satgutier@umich.edu * overwritten by a "real" branch during this cycle */ 27310234Syasuko.eckert@amd.com DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x correctly" 27410234Syasuko.eckert@amd.com " inst: %s\n", 27510152Satgutier@umich.edu inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst); 27610234Syasuko.eckert@amd.com 27710234Syasuko.eckert@amd.com reason = BranchData::CorrectlyPredictedBranch; 27810152Satgutier@umich.edu } else { 27910234Syasuko.eckert@amd.com /* Branch prediction got the wrong target */ 28010234Syasuko.eckert@amd.com DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x" 28110152Satgutier@umich.edu " but got the wrong target (actual: 0x%x) inst: %s\n", 28210234Syasuko.eckert@amd.com inst->pc.instAddr(), inst->predictedTarget.instAddr(), 28310152Satgutier@umich.edu target.instAddr(), *inst); 28410152Satgutier@umich.edu 28510152Satgutier@umich.edu reason = BranchData::BadlyPredictedBranchTarget; 28610234Syasuko.eckert@amd.com } 28710234Syasuko.eckert@amd.com } else if (must_branch) { 28810234Syasuko.eckert@amd.com /* Unpredicted branch */ 28910234Syasuko.eckert@amd.com DPRINTF(Branch, "Unpredicted branch from 0x%x to 0x%x inst: %s\n", 29010234Syasuko.eckert@amd.com inst->pc.instAddr(), target.instAddr(), *inst); 29110234Syasuko.eckert@amd.com 29210234Syasuko.eckert@amd.com reason = BranchData::UnpredictedBranch; 29310152Satgutier@umich.edu } else { 29410234Syasuko.eckert@amd.com /* No branch at all */ 29510234Syasuko.eckert@amd.com reason = BranchData::NoBranch; 29610234Syasuko.eckert@amd.com } 29710234Syasuko.eckert@amd.com 29810152Satgutier@umich.edu updateBranchData(inst->id.threadId, reason, inst, target, branch); 29910234Syasuko.eckert@amd.com} 30010234Syasuko.eckert@amd.com 30110234Syasuko.eckert@amd.comvoid 30210234Syasuko.eckert@amd.comExecute::updateBranchData( 30310234Syasuko.eckert@amd.com ThreadID tid, 30410234Syasuko.eckert@amd.com BranchData::Reason reason, 30510234Syasuko.eckert@amd.com MinorDynInstPtr inst, const TheISA::PCState &target, 30610152Satgutier@umich.edu BranchData &branch) 30710234Syasuko.eckert@amd.com{ 30810234Syasuko.eckert@amd.com if (reason != BranchData::NoBranch) { 30910234Syasuko.eckert@amd.com /* Bump up the stream sequence number on a real branch*/ 31010234Syasuko.eckert@amd.com if (BranchData::isStreamChange(reason)) 31110234Syasuko.eckert@amd.com executeInfo[tid].streamSeqNum++; 31210234Syasuko.eckert@amd.com 31310234Syasuko.eckert@amd.com /* Branches (even mis-predictions) don't change the predictionSeqNum, 31410234Syasuko.eckert@amd.com * just the streamSeqNum */ 31510234Syasuko.eckert@amd.com branch = BranchData(reason, tid, 31610234Syasuko.eckert@amd.com executeInfo[tid].streamSeqNum, 31710234Syasuko.eckert@amd.com /* Maintaining predictionSeqNum if there's no inst is just a 31810152Satgutier@umich.edu * courtesy and looks better on minorview */ 31910152Satgutier@umich.edu (inst->isBubble() ? executeInfo[tid].lastPredictionSeqNum 32010234Syasuko.eckert@amd.com : inst->id.predictionSeqNum), 32110234Syasuko.eckert@amd.com target, inst); 32210234Syasuko.eckert@amd.com 32310234Syasuko.eckert@amd.com DPRINTF(Branch, "Branch data signalled: %s\n", branch); 32410234Syasuko.eckert@amd.com } 32510234Syasuko.eckert@amd.com} 32610234Syasuko.eckert@amd.com 32710234Syasuko.eckert@amd.comvoid 32810234Syasuko.eckert@amd.comExecute::handleMemResponse(MinorDynInstPtr inst, 32910234Syasuko.eckert@amd.com LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault) 33010234Syasuko.eckert@amd.com{ 33110152Satgutier@umich.edu ThreadID thread_id = inst->id.threadId; 33210234Syasuko.eckert@amd.com ThreadContext *thread = cpu.getContext(thread_id); 33310234Syasuko.eckert@amd.com 33410234Syasuko.eckert@amd.com ExecContext context(cpu, *cpu.threads[thread_id], *this, inst); 33510234Syasuko.eckert@amd.com 33610234Syasuko.eckert@amd.com PacketPtr packet = response->packet; 33710234Syasuko.eckert@amd.com 33810234Syasuko.eckert@amd.com bool is_load = inst->staticInst->isLoad(); 33910234Syasuko.eckert@amd.com bool is_store = inst->staticInst->isStore(); 34010234Syasuko.eckert@amd.com bool is_atomic = inst->staticInst->isAtomic(); 34110234Syasuko.eckert@amd.com bool is_prefetch = inst->staticInst->isDataPrefetch(); 34210234Syasuko.eckert@amd.com 34310234Syasuko.eckert@amd.com /* If true, the trace's predicate value will be taken from the exec 34410234Syasuko.eckert@amd.com * context predicate, otherwise, it will be set to false */ 34510152Satgutier@umich.edu bool use_context_predicate = true; 34610152Satgutier@umich.edu 34710152Satgutier@umich.edu if (response->fault != NoFault) { 34810234Syasuko.eckert@amd.com /* Invoke memory faults. */ 34910234Syasuko.eckert@amd.com DPRINTF(MinorMem, "Completing fault from DTLB access: %s\n", 35010234Syasuko.eckert@amd.com response->fault->name()); 35110234Syasuko.eckert@amd.com 35210152Satgutier@umich.edu if (inst->staticInst->isPrefetch()) { 35310234Syasuko.eckert@amd.com DPRINTF(MinorMem, "Not taking fault on prefetch: %s\n", 35410234Syasuko.eckert@amd.com response->fault->name()); 35510234Syasuko.eckert@amd.com 35610234Syasuko.eckert@amd.com /* Don't assign to fault */ 35710234Syasuko.eckert@amd.com } else { 35810234Syasuko.eckert@amd.com /* Take the fault raised during the TLB/memory access */ 35910234Syasuko.eckert@amd.com fault = response->fault; 36010234Syasuko.eckert@amd.com 36110234Syasuko.eckert@amd.com fault->invoke(thread, inst->staticInst); 36210234Syasuko.eckert@amd.com } 36310234Syasuko.eckert@amd.com } else if (!packet) { 36410234Syasuko.eckert@amd.com DPRINTF(MinorMem, "Completing failed request inst: %s\n", 36510234Syasuko.eckert@amd.com *inst); 36610152Satgutier@umich.edu use_context_predicate = false; 36710234Syasuko.eckert@amd.com } else if (packet->isError()) { 36810234Syasuko.eckert@amd.com DPRINTF(MinorMem, "Trying to commit error response: %s\n", 36910234Syasuko.eckert@amd.com *inst); 37010234Syasuko.eckert@amd.com 37110152Satgutier@umich.edu fatal("Received error response packet for inst: %s\n", *inst); 37210152Satgutier@umich.edu } else if (is_store || is_load || is_prefetch || is_atomic) { 37310234Syasuko.eckert@amd.com assert(packet); 37410234Syasuko.eckert@amd.com 37510234Syasuko.eckert@amd.com DPRINTF(MinorMem, "Memory response inst: %s addr: 0x%x size: %d\n", 37610234Syasuko.eckert@amd.com *inst, packet->getAddr(), packet->getSize()); 37710234Syasuko.eckert@amd.com 37810152Satgutier@umich.edu if (is_load && packet->getSize() > 0) { 37910234Syasuko.eckert@amd.com DPRINTF(MinorMem, "Memory data[0]: 0x%x\n", 38010234Syasuko.eckert@amd.com static_cast<unsigned int>(packet->getConstPtr<uint8_t>()[0])); 38110234Syasuko.eckert@amd.com } 38210234Syasuko.eckert@amd.com 38310234Syasuko.eckert@amd.com /* Complete the memory access instruction */ 38410234Syasuko.eckert@amd.com fault = inst->staticInst->completeAcc(packet, &context, 38510234Syasuko.eckert@amd.com inst->traceData); 38610152Satgutier@umich.edu 38710152Satgutier@umich.edu if (fault != NoFault) { 38810234Syasuko.eckert@amd.com /* Invoke fault created by instruction completion */ 38910234Syasuko.eckert@amd.com DPRINTF(MinorMem, "Fault in memory completeAcc: %s\n", 39010234Syasuko.eckert@amd.com fault->name()); 39110234Syasuko.eckert@amd.com fault->invoke(thread, inst->staticInst); 39210152Satgutier@umich.edu } else { 39310234Syasuko.eckert@amd.com /* Stores need to be pushed into the store buffer to finish 39410234Syasuko.eckert@amd.com * them off */ 39510234Syasuko.eckert@amd.com if (response->needsToBeSentToStoreBuffer()) 39610234Syasuko.eckert@amd.com lsq.sendStoreToStoreBuffer(response); 39710234Syasuko.eckert@amd.com } 39810234Syasuko.eckert@amd.com } else { 39910234Syasuko.eckert@amd.com fatal("There should only ever be reads, " 40010234Syasuko.eckert@amd.com "writes or faults at this point\n"); 40110234Syasuko.eckert@amd.com } 40210234Syasuko.eckert@amd.com 40310234Syasuko.eckert@amd.com lsq.popResponse(response); 40410234Syasuko.eckert@amd.com 40510234Syasuko.eckert@amd.com if (inst->traceData) { 40610234Syasuko.eckert@amd.com inst->traceData->setPredicate((use_context_predicate ? 40710234Syasuko.eckert@amd.com context.readPredicate() : false)); 40810234Syasuko.eckert@amd.com } 40910234Syasuko.eckert@amd.com 41010234Syasuko.eckert@amd.com doInstCommitAccounting(inst); 41110234Syasuko.eckert@amd.com 41210234Syasuko.eckert@amd.com /* Generate output to account for branches */ 41310234Syasuko.eckert@amd.com tryToBranch(inst, fault, branch); 41410234Syasuko.eckert@amd.com} 41510234Syasuko.eckert@amd.com 41610234Syasuko.eckert@amd.combool 41710234Syasuko.eckert@amd.comExecute::isInterrupted(ThreadID thread_id) const 41810234Syasuko.eckert@amd.com{ 41910234Syasuko.eckert@amd.com return cpu.checkInterrupts(cpu.getContext(thread_id)); 42010234Syasuko.eckert@amd.com} 42110234Syasuko.eckert@amd.com 42210234Syasuko.eckert@amd.combool 42310234Syasuko.eckert@amd.comExecute::takeInterrupt(ThreadID thread_id, BranchData &branch) 42410234Syasuko.eckert@amd.com{ 42510234Syasuko.eckert@amd.com DPRINTF(MinorInterrupt, "Considering interrupt status from PC: %s\n", 42610234Syasuko.eckert@amd.com cpu.getContext(thread_id)->pcState()); 42710234Syasuko.eckert@amd.com 42810152Satgutier@umich.edu Fault interrupt = cpu.getInterruptController(thread_id)->getInterrupt 42910234Syasuko.eckert@amd.com (cpu.getContext(thread_id)); 43010234Syasuko.eckert@amd.com 43110234Syasuko.eckert@amd.com if (interrupt != NoFault) { 43210234Syasuko.eckert@amd.com /* The interrupt *must* set pcState */ 43310234Syasuko.eckert@amd.com cpu.getInterruptController(thread_id)->updateIntrInfo 43410234Syasuko.eckert@amd.com (cpu.getContext(thread_id)); 43510234Syasuko.eckert@amd.com interrupt->invoke(cpu.getContext(thread_id)); 43610234Syasuko.eckert@amd.com 43710234Syasuko.eckert@amd.com assert(!lsq.accessesInFlight()); 43810234Syasuko.eckert@amd.com 43910234Syasuko.eckert@amd.com DPRINTF(MinorInterrupt, "Invoking interrupt: %s to PC: %s\n", 44010234Syasuko.eckert@amd.com interrupt->name(), cpu.getContext(thread_id)->pcState()); 44110234Syasuko.eckert@amd.com 44210234Syasuko.eckert@amd.com /* Assume that an interrupt *must* cause a branch. Assert this? */ 44310234Syasuko.eckert@amd.com 44410234Syasuko.eckert@amd.com updateBranchData(thread_id, BranchData::Interrupt, 44510234Syasuko.eckert@amd.com MinorDynInst::bubble(), cpu.getContext(thread_id)->pcState(), 44610234Syasuko.eckert@amd.com branch); 44710234Syasuko.eckert@amd.com } 44810234Syasuko.eckert@amd.com 44910234Syasuko.eckert@amd.com return interrupt != NoFault; 45010234Syasuko.eckert@amd.com} 45110234Syasuko.eckert@amd.com 45210152Satgutier@umich.edubool 45310234Syasuko.eckert@amd.comExecute::executeMemRefInst(MinorDynInstPtr inst, BranchData &branch, 45410234Syasuko.eckert@amd.com bool &passed_predicate, Fault &fault) 45510234Syasuko.eckert@amd.com{ 45610234Syasuko.eckert@amd.com bool issued = false; 45710234Syasuko.eckert@amd.com 45810234Syasuko.eckert@amd.com /* Set to true if the mem op. is issued and sent to the mem system */ 45910234Syasuko.eckert@amd.com passed_predicate = false; 46010234Syasuko.eckert@amd.com 46110234Syasuko.eckert@amd.com if (!lsq.canRequest()) { 46210234Syasuko.eckert@amd.com /* Not acting on instruction yet as the memory 46310234Syasuko.eckert@amd.com * queues are full */ 46410234Syasuko.eckert@amd.com issued = false; 46510234Syasuko.eckert@amd.com } else { 46610234Syasuko.eckert@amd.com ThreadContext *thread = cpu.getContext(inst->id.threadId); 46710234Syasuko.eckert@amd.com TheISA::PCState old_pc = thread->pcState(); 46810234Syasuko.eckert@amd.com 46910234Syasuko.eckert@amd.com ExecContext context(cpu, *cpu.threads[inst->id.threadId], 47010234Syasuko.eckert@amd.com *this, inst); 47110234Syasuko.eckert@amd.com 47210234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Initiating memRef inst: %s\n", *inst); 47310234Syasuko.eckert@amd.com 47410234Syasuko.eckert@amd.com Fault init_fault = inst->staticInst->initiateAcc(&context, 47510234Syasuko.eckert@amd.com inst->traceData); 47610234Syasuko.eckert@amd.com 47710234Syasuko.eckert@amd.com if (init_fault != NoFault) { 47810234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Fault on memory inst: %s" 47910234Syasuko.eckert@amd.com " initiateAcc: %s\n", *inst, init_fault->name()); 48010234Syasuko.eckert@amd.com fault = init_fault; 48110152Satgutier@umich.edu } else { 48210152Satgutier@umich.edu /* Only set this if the instruction passed its 48310152Satgutier@umich.edu * predicate */ 48410152Satgutier@umich.edu passed_predicate = context.readPredicate(); 48510152Satgutier@umich.edu 48610234Syasuko.eckert@amd.com /* Set predicate in tracing */ 48710234Syasuko.eckert@amd.com if (inst->traceData) 48810152Satgutier@umich.edu inst->traceData->setPredicate(passed_predicate); 48910234Syasuko.eckert@amd.com 49010234Syasuko.eckert@amd.com /* If the instruction didn't pass its predicate (and so will not 49110234Syasuko.eckert@amd.com * progress from here) Try to branch to correct and branch 49210234Syasuko.eckert@amd.com * mis-prediction. */ 49310234Syasuko.eckert@amd.com if (!passed_predicate) { 49410234Syasuko.eckert@amd.com /* Leave it up to commit to handle the fault */ 49510152Satgutier@umich.edu lsq.pushFailedRequest(inst); 49610234Syasuko.eckert@amd.com } 49710152Satgutier@umich.edu } 49810152Satgutier@umich.edu 49910152Satgutier@umich.edu /* Restore thread PC */ 50010234Syasuko.eckert@amd.com thread->pcState(old_pc); 50110234Syasuko.eckert@amd.com issued = true; 50210234Syasuko.eckert@amd.com } 50310234Syasuko.eckert@amd.com 50410234Syasuko.eckert@amd.com return issued; 50510234Syasuko.eckert@amd.com} 50610234Syasuko.eckert@amd.com 50710234Syasuko.eckert@amd.com/** Increment a cyclic buffer index for indices [0, cycle_size-1] */ 50810234Syasuko.eckert@amd.cominline unsigned int 50910234Syasuko.eckert@amd.comcyclicIndexInc(unsigned int index, unsigned int cycle_size) 51010234Syasuko.eckert@amd.com{ 51110152Satgutier@umich.edu unsigned int ret = index + 1; 51210234Syasuko.eckert@amd.com 51310152Satgutier@umich.edu if (ret == cycle_size) 51410234Syasuko.eckert@amd.com ret = 0; 51510234Syasuko.eckert@amd.com 51610234Syasuko.eckert@amd.com return ret; 51710234Syasuko.eckert@amd.com} 51810234Syasuko.eckert@amd.com 51910234Syasuko.eckert@amd.com/** Decrement a cyclic buffer index for indices [0, cycle_size-1] */ 52010234Syasuko.eckert@amd.cominline unsigned int 52110234Syasuko.eckert@amd.comcyclicIndexDec(unsigned int index, unsigned int cycle_size) 52210234Syasuko.eckert@amd.com{ 52310152Satgutier@umich.edu int ret = index - 1; 52410152Satgutier@umich.edu 52510152Satgutier@umich.edu if (ret < 0) 52610152Satgutier@umich.edu ret = cycle_size - 1; 52710152Satgutier@umich.edu 52810152Satgutier@umich.edu return ret; 52910152Satgutier@umich.edu} 53010152Satgutier@umich.edu 53110152Satgutier@umich.eduunsigned int 53210152Satgutier@umich.eduExecute::issue(ThreadID thread_id) 53310152Satgutier@umich.edu{ 53410152Satgutier@umich.edu const ForwardInstData *insts_in = getInput(thread_id); 53510152Satgutier@umich.edu ExecuteThreadInfo &thread = executeInfo[thread_id]; 53610152Satgutier@umich.edu 53710234Syasuko.eckert@amd.com /* Early termination if we have no instructions */ 53810234Syasuko.eckert@amd.com if (!insts_in) 53910152Satgutier@umich.edu return 0; 54010152Satgutier@umich.edu 54110152Satgutier@umich.edu /* Start from the first FU */ 54210152Satgutier@umich.edu unsigned int fu_index = 0; 54310152Satgutier@umich.edu 54410152Satgutier@umich.edu /* Remains true while instructions are still being issued. If any 54510152Satgutier@umich.edu * instruction fails to issue, this is set to false and we exit issue. 54610152Satgutier@umich.edu * This strictly enforces in-order issue. For other issue behaviours, 54710152Satgutier@umich.edu * a more complicated test in the outer while loop below is needed. */ 54810234Syasuko.eckert@amd.com bool issued = true; 54910234Syasuko.eckert@amd.com 55010152Satgutier@umich.edu /* Number of insts issues this cycle to check for issueLimit */ 55110152Satgutier@umich.edu unsigned num_insts_issued = 0; 55210152Satgutier@umich.edu 55310152Satgutier@umich.edu /* Number of memory ops issues this cycle to check for memoryIssueLimit */ 55410152Satgutier@umich.edu unsigned num_mem_insts_issued = 0; 55510152Satgutier@umich.edu 55610152Satgutier@umich.edu /* Number of instructions discarded this cycle in order to enforce a 55710152Satgutier@umich.edu * discardLimit. @todo, add that parameter? */ 55810234Syasuko.eckert@amd.com unsigned num_insts_discarded = 0; 55910152Satgutier@umich.edu 56010152Satgutier@umich.edu do { 56110152Satgutier@umich.edu MinorDynInstPtr inst = insts_in->insts[thread.inputIndex]; 56210152Satgutier@umich.edu Fault fault = inst->fault; 56310234Syasuko.eckert@amd.com bool discarded = false; 56410234Syasuko.eckert@amd.com bool issued_mem_ref = false; 56510234Syasuko.eckert@amd.com 56610234Syasuko.eckert@amd.com if (inst->isBubble()) { 56710234Syasuko.eckert@amd.com /* Skip */ 56810234Syasuko.eckert@amd.com issued = true; 56910234Syasuko.eckert@amd.com } else if (cpu.getContext(thread_id)->status() == 57010234Syasuko.eckert@amd.com ThreadContext::Suspended) 57110234Syasuko.eckert@amd.com { 57210234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Discarding inst: %s from suspended" 57310234Syasuko.eckert@amd.com " thread\n", *inst); 57410234Syasuko.eckert@amd.com 57510234Syasuko.eckert@amd.com issued = true; 57610234Syasuko.eckert@amd.com discarded = true; 57710234Syasuko.eckert@amd.com } else if (inst->id.streamSeqNum != thread.streamSeqNum) { 57810234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Discarding inst: %s as its stream" 57910234Syasuko.eckert@amd.com " state was unexpected, expected: %d\n", 58010234Syasuko.eckert@amd.com *inst, thread.streamSeqNum); 58110234Syasuko.eckert@amd.com issued = true; 58210234Syasuko.eckert@amd.com discarded = true; 58310234Syasuko.eckert@amd.com } else { 58410234Syasuko.eckert@amd.com /* Try and issue an instruction into an FU, assume we didn't and 58510234Syasuko.eckert@amd.com * fix that in the loop */ 58610234Syasuko.eckert@amd.com issued = false; 58710234Syasuko.eckert@amd.com 58810234Syasuko.eckert@amd.com /* Try FU from 0 each instruction */ 58910234Syasuko.eckert@amd.com fu_index = 0; 59010234Syasuko.eckert@amd.com 59110234Syasuko.eckert@amd.com /* Try and issue a single instruction stepping through the 59210234Syasuko.eckert@amd.com * available FUs */ 59310234Syasuko.eckert@amd.com do { 59410234Syasuko.eckert@amd.com FUPipeline *fu = funcUnits[fu_index]; 59510234Syasuko.eckert@amd.com 59610234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Trying to issue inst: %s to FU: %d\n", 59710234Syasuko.eckert@amd.com *inst, fu_index); 59810234Syasuko.eckert@amd.com 59910234Syasuko.eckert@amd.com /* Does the examined fu have the OpClass-related capability 60010234Syasuko.eckert@amd.com * needed to execute this instruction? Faults can always 60110234Syasuko.eckert@amd.com * issue to any FU but probably should just 'live' in the 60210234Syasuko.eckert@amd.com * inFlightInsts queue rather than having an FU. */ 60310234Syasuko.eckert@amd.com bool fu_is_capable = (!inst->isFault() ? 60410234Syasuko.eckert@amd.com fu->provides(inst->staticInst->opClass()) : true); 60510234Syasuko.eckert@amd.com 60610234Syasuko.eckert@amd.com if (inst->isNoCostInst()) { 60710234Syasuko.eckert@amd.com /* Issue free insts. to a fake numbered FU */ 60810234Syasuko.eckert@amd.com fu_index = noCostFUIndex; 60910234Syasuko.eckert@amd.com 61010234Syasuko.eckert@amd.com /* And start the countdown on activity to allow 61110234Syasuko.eckert@amd.com * this instruction to get to the end of its FU */ 61210234Syasuko.eckert@amd.com cpu.activityRecorder->activity(); 61310152Satgutier@umich.edu 61410234Syasuko.eckert@amd.com /* Mark the destinations for this instruction as 61510152Satgutier@umich.edu * busy */ 61610152Satgutier@umich.edu scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() + 61710234Syasuko.eckert@amd.com Cycles(0), cpu.getContext(thread_id), false); 61810234Syasuko.eckert@amd.com 61910234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Issuing %s to %d\n", inst->id, noCostFUIndex); 62010234Syasuko.eckert@amd.com inst->fuIndex = noCostFUIndex; 62110234Syasuko.eckert@amd.com inst->extraCommitDelay = Cycles(0); 62210234Syasuko.eckert@amd.com inst->extraCommitDelayExpr = NULL; 62310234Syasuko.eckert@amd.com 62410234Syasuko.eckert@amd.com /* Push the instruction onto the inFlight queue so 62510234Syasuko.eckert@amd.com * it can be committed in order */ 62610152Satgutier@umich.edu QueuedInst fu_inst(inst); 62710152Satgutier@umich.edu thread.inFlightInsts->push(fu_inst); 62810234Syasuko.eckert@amd.com 62910234Syasuko.eckert@amd.com issued = true; 63010234Syasuko.eckert@amd.com 63110234Syasuko.eckert@amd.com } else if (!fu_is_capable || fu->alreadyPushed()) { 63210152Satgutier@umich.edu /* Skip */ 63310234Syasuko.eckert@amd.com if (!fu_is_capable) { 63410234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Can't issue as FU: %d isn't" 63510234Syasuko.eckert@amd.com " capable\n", fu_index); 63610234Syasuko.eckert@amd.com } else { 63710234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Can't issue as FU: %d is" 63810234Syasuko.eckert@amd.com " already busy\n", fu_index); 63910234Syasuko.eckert@amd.com } 64010234Syasuko.eckert@amd.com } else if (fu->stalled) { 64110234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Can't issue inst: %s into FU: %d," 64210234Syasuko.eckert@amd.com " it's stalled\n", 64310234Syasuko.eckert@amd.com *inst, fu_index); 64410152Satgutier@umich.edu } else if (!fu->canInsert()) { 64510234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Can't issue inst: %s to busy FU" 64610234Syasuko.eckert@amd.com " for another: %d cycles\n", 64710234Syasuko.eckert@amd.com *inst, fu->cyclesBeforeInsert()); 64810152Satgutier@umich.edu } else { 64910234Syasuko.eckert@amd.com MinorFUTiming *timing = (!inst->isFault() ? 65010234Syasuko.eckert@amd.com fu->findTiming(inst->staticInst) : NULL); 65110234Syasuko.eckert@amd.com 65210234Syasuko.eckert@amd.com const std::vector<Cycles> *src_latencies = 65310234Syasuko.eckert@amd.com (timing ? &(timing->srcRegsRelativeLats) 65410234Syasuko.eckert@amd.com : NULL); 65510234Syasuko.eckert@amd.com 65610234Syasuko.eckert@amd.com const std::vector<bool> *cant_forward_from_fu_indices = 65710152Satgutier@umich.edu &(fu->cantForwardFromFUIndices); 65810234Syasuko.eckert@amd.com 65910234Syasuko.eckert@amd.com if (timing && timing->suppress) { 66010234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Can't issue inst: %s as extra" 66110152Satgutier@umich.edu " decoding is suppressing it\n", 66210234Syasuko.eckert@amd.com *inst); 66310234Syasuko.eckert@amd.com } else if (!scoreboard[thread_id].canInstIssue(inst, 66410234Syasuko.eckert@amd.com src_latencies, cant_forward_from_fu_indices, 66510234Syasuko.eckert@amd.com cpu.curCycle(), cpu.getContext(thread_id))) 66610234Syasuko.eckert@amd.com { 66710234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Can't issue inst: %s yet\n", 66810234Syasuko.eckert@amd.com *inst); 66910152Satgutier@umich.edu } else { 67010152Satgutier@umich.edu /* Can insert the instruction into this FU */ 67110152Satgutier@umich.edu DPRINTF(MinorExecute, "Issuing inst: %s" 67210152Satgutier@umich.edu " into FU %d\n", *inst, 67310152Satgutier@umich.edu fu_index); 67410152Satgutier@umich.edu 67510152Satgutier@umich.edu Cycles extra_dest_retire_lat = Cycles(0); 67610234Syasuko.eckert@amd.com TimingExpr *extra_dest_retire_lat_expr = NULL; 67710234Syasuko.eckert@amd.com Cycles extra_assumed_lat = Cycles(0); 67810152Satgutier@umich.edu 67910152Satgutier@umich.edu /* Add the extraCommitDelay and extraAssumeLat to 68010152Satgutier@umich.edu * the FU pipeline timings */ 68110152Satgutier@umich.edu if (timing) { 68210152Satgutier@umich.edu extra_dest_retire_lat = 68310152Satgutier@umich.edu timing->extraCommitLat; 68410152Satgutier@umich.edu extra_dest_retire_lat_expr = 68510152Satgutier@umich.edu timing->extraCommitLatExpr; 68610152Satgutier@umich.edu extra_assumed_lat = 68710152Satgutier@umich.edu timing->extraAssumedLat; 68810152Satgutier@umich.edu } 68910152Satgutier@umich.edu 69010152Satgutier@umich.edu issued_mem_ref = inst->isMemRef(); 69110152Satgutier@umich.edu 69210152Satgutier@umich.edu QueuedInst fu_inst(inst); 69310152Satgutier@umich.edu 69410152Satgutier@umich.edu /* Decorate the inst with FU details */ 69510152Satgutier@umich.edu inst->fuIndex = fu_index; 69610152Satgutier@umich.edu inst->extraCommitDelay = extra_dest_retire_lat; 69710152Satgutier@umich.edu inst->extraCommitDelayExpr = 69810152Satgutier@umich.edu extra_dest_retire_lat_expr; 69910152Satgutier@umich.edu 70010152Satgutier@umich.edu if (issued_mem_ref) { 70110152Satgutier@umich.edu /* Remember which instruction this memory op 70210152Satgutier@umich.edu * depends on so that initiateAcc can be called 70310152Satgutier@umich.edu * early */ 70410152Satgutier@umich.edu if (allowEarlyMemIssue) { 70510152Satgutier@umich.edu inst->instToWaitFor = 70610152Satgutier@umich.edu scoreboard[thread_id].execSeqNumToWaitFor(inst, 70710152Satgutier@umich.edu cpu.getContext(thread_id)); 70810152Satgutier@umich.edu 70910152Satgutier@umich.edu if (lsq.getLastMemBarrier(thread_id) > 71010152Satgutier@umich.edu inst->instToWaitFor) 71110234Syasuko.eckert@amd.com { 71210234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "A barrier will" 71310152Satgutier@umich.edu " cause a delay in mem ref issue of" 71410152Satgutier@umich.edu " inst: %s until after inst" 71510234Syasuko.eckert@amd.com " %d(exec)\n", *inst, 71610234Syasuko.eckert@amd.com lsq.getLastMemBarrier(thread_id)); 71710234Syasuko.eckert@amd.com 71810234Syasuko.eckert@amd.com inst->instToWaitFor = 71910234Syasuko.eckert@amd.com lsq.getLastMemBarrier(thread_id); 72010234Syasuko.eckert@amd.com } else { 72110234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Memory ref inst:" 72210234Syasuko.eckert@amd.com " %s must wait for inst %d(exec)" 72310234Syasuko.eckert@amd.com " before issuing\n", 72410234Syasuko.eckert@amd.com *inst, inst->instToWaitFor); 72510234Syasuko.eckert@amd.com } 72610234Syasuko.eckert@amd.com 72710234Syasuko.eckert@amd.com inst->canEarlyIssue = true; 72810234Syasuko.eckert@amd.com } 72910234Syasuko.eckert@amd.com /* Also queue this instruction in the memory ref 73010234Syasuko.eckert@amd.com * queue to ensure in-order issue to the LSQ */ 73110234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Pushing mem inst: %s\n", 73210152Satgutier@umich.edu *inst); 73310234Syasuko.eckert@amd.com thread.inFUMemInsts->push(fu_inst); 73410234Syasuko.eckert@amd.com } 73510152Satgutier@umich.edu 73610234Syasuko.eckert@amd.com /* Issue to FU */ 73710234Syasuko.eckert@amd.com fu->push(fu_inst); 73810234Syasuko.eckert@amd.com /* And start the countdown on activity to allow 73910234Syasuko.eckert@amd.com * this instruction to get to the end of its FU */ 74010234Syasuko.eckert@amd.com cpu.activityRecorder->activity(); 74110234Syasuko.eckert@amd.com 74210234Syasuko.eckert@amd.com /* Mark the destinations for this instruction as 74310234Syasuko.eckert@amd.com * busy */ 74410234Syasuko.eckert@amd.com scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() + 74510234Syasuko.eckert@amd.com fu->description.opLat + 74610234Syasuko.eckert@amd.com extra_dest_retire_lat + 74710234Syasuko.eckert@amd.com extra_assumed_lat, 74810152Satgutier@umich.edu cpu.getContext(thread_id), 74910234Syasuko.eckert@amd.com issued_mem_ref && extra_assumed_lat == Cycles(0)); 75010234Syasuko.eckert@amd.com 75110234Syasuko.eckert@amd.com /* Push the instruction onto the inFlight queue so 75210234Syasuko.eckert@amd.com * it can be committed in order */ 75310152Satgutier@umich.edu thread.inFlightInsts->push(fu_inst); 75410152Satgutier@umich.edu 75510152Satgutier@umich.edu issued = true; 75610234Syasuko.eckert@amd.com } 75710234Syasuko.eckert@amd.com } 75810234Syasuko.eckert@amd.com 75910234Syasuko.eckert@amd.com fu_index++; 76010152Satgutier@umich.edu } while (fu_index != numFuncUnits && !issued); 76110234Syasuko.eckert@amd.com 76210234Syasuko.eckert@amd.com if (!issued) 76310234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Didn't issue inst: %s\n", *inst); 76410234Syasuko.eckert@amd.com } 76510234Syasuko.eckert@amd.com 76610152Satgutier@umich.edu if (issued) { 76710234Syasuko.eckert@amd.com /* Generate MinorTrace's MinorInst lines. Do this at commit 76810234Syasuko.eckert@amd.com * to allow better instruction annotation? */ 76910234Syasuko.eckert@amd.com if (DTRACE(MinorTrace) && !inst->isBubble()) 77010234Syasuko.eckert@amd.com inst->minorTraceInst(*this); 77110152Satgutier@umich.edu 77210234Syasuko.eckert@amd.com /* Mark up barriers in the LSQ */ 77310234Syasuko.eckert@amd.com if (!discarded && inst->isInst() && 77410234Syasuko.eckert@amd.com inst->staticInst->isMemBarrier()) 77510234Syasuko.eckert@amd.com { 77610234Syasuko.eckert@amd.com DPRINTF(MinorMem, "Issuing memory barrier inst: %s\n", *inst); 77710234Syasuko.eckert@amd.com lsq.issuedMemBarrierInst(inst); 77810152Satgutier@umich.edu } 77910234Syasuko.eckert@amd.com 78010234Syasuko.eckert@amd.com if (inst->traceData && setTraceTimeOnIssue) { 78110234Syasuko.eckert@amd.com inst->traceData->setWhen(curTick()); 78210234Syasuko.eckert@amd.com } 78310234Syasuko.eckert@amd.com 78410234Syasuko.eckert@amd.com if (issued_mem_ref) 78510152Satgutier@umich.edu num_mem_insts_issued++; 78610152Satgutier@umich.edu 78710234Syasuko.eckert@amd.com if (discarded) { 78810234Syasuko.eckert@amd.com num_insts_discarded++; 78910234Syasuko.eckert@amd.com } else if (!inst->isBubble()) { 79010234Syasuko.eckert@amd.com num_insts_issued++; 79110234Syasuko.eckert@amd.com 79210234Syasuko.eckert@amd.com if (num_insts_issued == issueLimit) 79310234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Reached inst issue limit\n"); 79410234Syasuko.eckert@amd.com } 79510234Syasuko.eckert@amd.com 79610234Syasuko.eckert@amd.com thread.inputIndex++; 79710234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Stepping to next inst inputIndex: %d\n", 79810234Syasuko.eckert@amd.com thread.inputIndex); 79910234Syasuko.eckert@amd.com } 80010234Syasuko.eckert@amd.com 80110234Syasuko.eckert@amd.com /* Got to the end of a line */ 80210234Syasuko.eckert@amd.com if (thread.inputIndex == insts_in->width()) { 80310234Syasuko.eckert@amd.com popInput(thread_id); 80410234Syasuko.eckert@amd.com /* Set insts_in to null to force us to leave the surrounding 80510234Syasuko.eckert@amd.com * loop */ 80610234Syasuko.eckert@amd.com insts_in = NULL; 80710234Syasuko.eckert@amd.com 80810234Syasuko.eckert@amd.com if (processMoreThanOneInput) { 80910234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Wrapping\n"); 81010234Syasuko.eckert@amd.com insts_in = getInput(thread_id); 81110234Syasuko.eckert@amd.com } 81210234Syasuko.eckert@amd.com } 81310234Syasuko.eckert@amd.com } while (insts_in && thread.inputIndex < insts_in->width() && 81410234Syasuko.eckert@amd.com /* We still have instructions */ 81510234Syasuko.eckert@amd.com fu_index != numFuncUnits && /* Not visited all FUs */ 81610234Syasuko.eckert@amd.com issued && /* We've not yet failed to issue an instruction */ 81710234Syasuko.eckert@amd.com num_insts_issued != issueLimit && /* Still allowed to issue */ 81810234Syasuko.eckert@amd.com num_mem_insts_issued != memoryIssueLimit); 81910234Syasuko.eckert@amd.com 82010234Syasuko.eckert@amd.com return num_insts_issued; 82110234Syasuko.eckert@amd.com} 82210234Syasuko.eckert@amd.com 82310234Syasuko.eckert@amd.combool 82410234Syasuko.eckert@amd.comExecute::tryPCEvents(ThreadID thread_id) 82510234Syasuko.eckert@amd.com{ 82610234Syasuko.eckert@amd.com ThreadContext *thread = cpu.getContext(thread_id); 82710234Syasuko.eckert@amd.com unsigned int num_pc_event_checks = 0; 82810152Satgutier@umich.edu 82910234Syasuko.eckert@amd.com /* Handle PC events on instructions */ 83010234Syasuko.eckert@amd.com Addr oldPC; 83110234Syasuko.eckert@amd.com do { 83210234Syasuko.eckert@amd.com oldPC = thread->instAddr(); 83310152Satgutier@umich.edu cpu.system->pcEventQueue.service(thread); 83410234Syasuko.eckert@amd.com num_pc_event_checks++; 83510234Syasuko.eckert@amd.com } while (oldPC != thread->instAddr()); 83610234Syasuko.eckert@amd.com 83710234Syasuko.eckert@amd.com if (num_pc_event_checks > 1) { 83810234Syasuko.eckert@amd.com DPRINTF(PCEvent, "Acting on PC Event to PC: %s\n", 83910234Syasuko.eckert@amd.com thread->pcState()); 84010234Syasuko.eckert@amd.com } 84110234Syasuko.eckert@amd.com 84210152Satgutier@umich.edu return num_pc_event_checks > 1; 84310234Syasuko.eckert@amd.com} 84410234Syasuko.eckert@amd.com 84510234Syasuko.eckert@amd.comvoid 84610234Syasuko.eckert@amd.comExecute::doInstCommitAccounting(MinorDynInstPtr inst) 84710234Syasuko.eckert@amd.com{ 84810234Syasuko.eckert@amd.com assert(!inst->isFault()); 84910234Syasuko.eckert@amd.com 85010234Syasuko.eckert@amd.com MinorThread *thread = cpu.threads[inst->id.threadId]; 85110234Syasuko.eckert@amd.com 85210234Syasuko.eckert@amd.com /* Increment the many and various inst and op counts in the 85310234Syasuko.eckert@amd.com * thread and system */ 85410234Syasuko.eckert@amd.com if (!inst->staticInst->isMicroop() || inst->staticInst->isLastMicroop()) 85510234Syasuko.eckert@amd.com { 85610234Syasuko.eckert@amd.com thread->numInst++; 85710234Syasuko.eckert@amd.com thread->numInsts++; 85810234Syasuko.eckert@amd.com cpu.stats.numInsts++; 85910234Syasuko.eckert@amd.com cpu.system->totalNumInsts++; 86010234Syasuko.eckert@amd.com 86110234Syasuko.eckert@amd.com /* Act on events related to instruction counts */ 86210234Syasuko.eckert@amd.com cpu.comInstEventQueue[inst->id.threadId]->serviceEvents(thread->numInst); 86310234Syasuko.eckert@amd.com cpu.system->instEventQueue.serviceEvents(cpu.system->totalNumInsts); 86410234Syasuko.eckert@amd.com } 86510234Syasuko.eckert@amd.com thread->numOp++; 86610234Syasuko.eckert@amd.com thread->numOps++; 86710234Syasuko.eckert@amd.com cpu.stats.numOps++; 86810234Syasuko.eckert@amd.com cpu.stats.committedInstType[inst->id.threadId] 86910234Syasuko.eckert@amd.com [inst->staticInst->opClass()]++; 87010234Syasuko.eckert@amd.com 87110234Syasuko.eckert@amd.com /* Set the CP SeqNum to the numOps commit number */ 87210234Syasuko.eckert@amd.com if (inst->traceData) 87310234Syasuko.eckert@amd.com inst->traceData->setCPSeq(thread->numOp); 87410234Syasuko.eckert@amd.com 87510234Syasuko.eckert@amd.com cpu.probeInstCommit(inst->staticInst, inst->pc.instAddr()); 87610234Syasuko.eckert@amd.com} 87710234Syasuko.eckert@amd.com 87810234Syasuko.eckert@amd.combool 87910234Syasuko.eckert@amd.comExecute::commitInst(MinorDynInstPtr inst, bool early_memory_issue, 88010234Syasuko.eckert@amd.com BranchData &branch, Fault &fault, bool &committed, 88110234Syasuko.eckert@amd.com bool &completed_mem_issue) 88210234Syasuko.eckert@amd.com{ 88310234Syasuko.eckert@amd.com ThreadID thread_id = inst->id.threadId; 88410234Syasuko.eckert@amd.com ThreadContext *thread = cpu.getContext(thread_id); 88510234Syasuko.eckert@amd.com 88610234Syasuko.eckert@amd.com bool completed_inst = true; 88710234Syasuko.eckert@amd.com fault = NoFault; 88810234Syasuko.eckert@amd.com 88910234Syasuko.eckert@amd.com /* Is the thread for this instruction suspended? In that case, just 89010234Syasuko.eckert@amd.com * stall as long as there are no pending interrupts */ 89110234Syasuko.eckert@amd.com if (thread->status() == ThreadContext::Suspended && 89210234Syasuko.eckert@amd.com !isInterrupted(thread_id)) 89310234Syasuko.eckert@amd.com { 89410234Syasuko.eckert@amd.com panic("We should never hit the case where we try to commit from a " 89510234Syasuko.eckert@amd.com "suspended thread as the streamSeqNum should not match"); 89610234Syasuko.eckert@amd.com } else if (inst->isFault()) { 89710234Syasuko.eckert@amd.com ExecContext context(cpu, *cpu.threads[thread_id], *this, inst); 89810234Syasuko.eckert@amd.com 89910234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Fault inst reached Execute: %s\n", 90010234Syasuko.eckert@amd.com inst->fault->name()); 90110234Syasuko.eckert@amd.com 90210234Syasuko.eckert@amd.com fault = inst->fault; 90310234Syasuko.eckert@amd.com inst->fault->invoke(thread, NULL); 90410152Satgutier@umich.edu 90510152Satgutier@umich.edu tryToBranch(inst, fault, branch); 90610234Syasuko.eckert@amd.com } else if (inst->staticInst->isMemRef()) { 90710152Satgutier@umich.edu /* Memory accesses are executed in two parts: 90810234Syasuko.eckert@amd.com * executeMemRefInst -- calculates the EA and issues the access 90910234Syasuko.eckert@amd.com * to memory. This is done here. 91010234Syasuko.eckert@amd.com * handleMemResponse -- handles the response packet, done by 91110234Syasuko.eckert@amd.com * Execute::commit 91210152Satgutier@umich.edu * 91310234Syasuko.eckert@amd.com * While the memory access is in its FU, the EA is being 91410234Syasuko.eckert@amd.com * calculated. At the end of the FU, when it is ready to 91510234Syasuko.eckert@amd.com * 'commit' (in this function), the access is presented to the 91610234Syasuko.eckert@amd.com * memory queues. When a response comes back from memory, 91710234Syasuko.eckert@amd.com * Execute::commit will commit it. 91810234Syasuko.eckert@amd.com */ 91910234Syasuko.eckert@amd.com bool predicate_passed = false; 92010152Satgutier@umich.edu bool completed_mem_inst = executeMemRefInst(inst, branch, 92110152Satgutier@umich.edu predicate_passed, fault); 92210234Syasuko.eckert@amd.com 92310152Satgutier@umich.edu if (completed_mem_inst && fault != NoFault) { 92410234Syasuko.eckert@amd.com if (early_memory_issue) { 92510152Satgutier@umich.edu DPRINTF(MinorExecute, "Fault in early executing inst: %s\n", 92610152Satgutier@umich.edu fault->name()); 92710152Satgutier@umich.edu /* Don't execute the fault, just stall the instruction 92810152Satgutier@umich.edu * until it gets to the head of inFlightInsts */ 92910152Satgutier@umich.edu inst->canEarlyIssue = false; 93010152Satgutier@umich.edu /* Not completed as we'll come here again to pick up 93110152Satgutier@umich.edu * the fault when we get to the end of the FU */ 93210152Satgutier@umich.edu completed_inst = false; 93310152Satgutier@umich.edu } else { 93410152Satgutier@umich.edu DPRINTF(MinorExecute, "Fault in execute: %s\n", 93510152Satgutier@umich.edu fault->name()); 93610152Satgutier@umich.edu fault->invoke(thread, NULL); 93710152Satgutier@umich.edu 93810152Satgutier@umich.edu tryToBranch(inst, fault, branch); 93910152Satgutier@umich.edu completed_inst = true; 94010152Satgutier@umich.edu } 94110152Satgutier@umich.edu } else { 94210152Satgutier@umich.edu completed_inst = completed_mem_inst; 94310152Satgutier@umich.edu } 94410152Satgutier@umich.edu completed_mem_issue = completed_inst; 94510152Satgutier@umich.edu } else if (inst->isInst() && inst->staticInst->isMemBarrier() && 94610152Satgutier@umich.edu !lsq.canPushIntoStoreBuffer()) 94710152Satgutier@umich.edu { 94810234Syasuko.eckert@amd.com DPRINTF(MinorExecute, "Can't commit data barrier inst: %s yet as" 94910234Syasuko.eckert@amd.com " there isn't space in the store buffer\n", *inst); 95010152Satgutier@umich.edu 95110234Syasuko.eckert@amd.com completed_inst = false; 95210152Satgutier@umich.edu } else if (inst->isInst() && inst->staticInst->isQuiesce() 95310234Syasuko.eckert@amd.com && !branch.isBubble()){ 95410234Syasuko.eckert@amd.com /* This instruction can suspend, need to be able to communicate 95510234Syasuko.eckert@amd.com * backwards, so no other branches may evaluate this cycle*/ 95610234Syasuko.eckert@amd.com completed_inst = false; 95710234Syasuko.eckert@amd.com } else { 95810152Satgutier@umich.edu ExecContext context(cpu, *cpu.threads[thread_id], *this, inst); 959 960 DPRINTF(MinorExecute, "Committing inst: %s\n", *inst); 961 962 fault = inst->staticInst->execute(&context, 963 inst->traceData); 964 965 /* Set the predicate for tracing and dump */ 966 if (inst->traceData) 967 inst->traceData->setPredicate(context.readPredicate()); 968 969 committed = true; 970 971 if (fault != NoFault) { 972 DPRINTF(MinorExecute, "Fault in execute of inst: %s fault: %s\n", 973 *inst, fault->name()); 974 fault->invoke(thread, inst->staticInst); 975 } 976 977 doInstCommitAccounting(inst); 978 tryToBranch(inst, fault, branch); 979 } 980 981 if (completed_inst) { 982 /* Keep a copy of this instruction's predictionSeqNum just in case 983 * we need to issue a branch without an instruction (such as an 984 * interrupt) */ 985 executeInfo[thread_id].lastPredictionSeqNum = inst->id.predictionSeqNum; 986 987 /* Check to see if this instruction suspended the current thread. */ 988 if (!inst->isFault() && 989 thread->status() == ThreadContext::Suspended && 990 branch.isBubble() && /* It didn't branch too */ 991 !isInterrupted(thread_id)) /* Don't suspend if we have 992 interrupts */ 993 { 994 TheISA::PCState resume_pc = cpu.getContext(thread_id)->pcState(); 995 996 assert(resume_pc.microPC() == 0); 997 998 DPRINTF(MinorInterrupt, "Suspending thread: %d from Execute" 999 " inst: %s\n", thread_id, *inst); 1000 1001 cpu.stats.numFetchSuspends++; 1002 1003 updateBranchData(thread_id, BranchData::SuspendThread, inst, 1004 resume_pc, branch); 1005 } 1006 } 1007 1008 return completed_inst; 1009} 1010 1011void 1012Execute::commit(ThreadID thread_id, bool only_commit_microops, bool discard, 1013 BranchData &branch) 1014{ 1015 Fault fault = NoFault; 1016 Cycles now = cpu.curCycle(); 1017 ExecuteThreadInfo &ex_info = executeInfo[thread_id]; 1018 1019 /** 1020 * Try and execute as many instructions from the end of FU pipelines as 1021 * possible. This *doesn't* include actually advancing the pipelines. 1022 * 1023 * We do this by looping on the front of the inFlightInsts queue for as 1024 * long as we can find the desired instruction at the end of the 1025 * functional unit it was issued to without seeing a branch or a fault. 1026 * In this function, these terms are used: 1027 * complete -- The instruction has finished its passage through 1028 * its functional unit and its fate has been decided 1029 * (committed, discarded, issued to the memory system) 1030 * commit -- The instruction is complete(d), not discarded and has 1031 * its effects applied to the CPU state 1032 * discard(ed) -- The instruction is complete but not committed 1033 * as its streamSeqNum disagrees with the current 1034 * Execute::streamSeqNum 1035 * 1036 * Commits are also possible from two other places: 1037 * 1038 * 1) Responses returning from the LSQ 1039 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier 1040 * than their position in the inFlightInsts queue, but after all 1041 * their dependencies are resolved. 1042 */ 1043 1044 /* Has an instruction been completed? Once this becomes false, we stop 1045 * trying to complete instructions. */ 1046 bool completed_inst = true; 1047 1048 /* Number of insts committed this cycle to check against commitLimit */ 1049 unsigned int num_insts_committed = 0; 1050 1051 /* Number of memory access instructions committed to check against 1052 * memCommitLimit */ 1053 unsigned int num_mem_refs_committed = 0; 1054 1055 if (only_commit_microops && !ex_info.inFlightInsts->empty()) { 1056 DPRINTF(MinorInterrupt, "Only commit microops %s %d\n", 1057 *(ex_info.inFlightInsts->front().inst), 1058 ex_info.lastCommitWasEndOfMacroop); 1059 } 1060 1061 while (!ex_info.inFlightInsts->empty() && /* Some more instructions to process */ 1062 !branch.isStreamChange() && /* No real branch */ 1063 fault == NoFault && /* No faults */ 1064 completed_inst && /* Still finding instructions to execute */ 1065 num_insts_committed != commitLimit /* Not reached commit limit */ 1066 ) 1067 { 1068 if (only_commit_microops) { 1069 DPRINTF(MinorInterrupt, "Committing tail of insts before" 1070 " interrupt: %s\n", 1071 *(ex_info.inFlightInsts->front().inst)); 1072 } 1073 1074 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front()); 1075 1076 InstSeqNum head_exec_seq_num = 1077 head_inflight_inst->inst->id.execSeqNum; 1078 1079 /* The instruction we actually process if completed_inst 1080 * remains true to the end of the loop body. 1081 * Start by considering the the head of the in flight insts queue */ 1082 MinorDynInstPtr inst = head_inflight_inst->inst; 1083 1084 bool committed_inst = false; 1085 bool discard_inst = false; 1086 bool completed_mem_ref = false; 1087 bool issued_mem_ref = false; 1088 bool early_memory_issue = false; 1089 1090 /* Must set this again to go around the loop */ 1091 completed_inst = false; 1092 1093 /* If we're just completing a macroop before an interrupt or drain, 1094 * can we stil commit another microop (rather than a memory response) 1095 * without crosing into the next full instruction? */ 1096 bool can_commit_insts = !ex_info.inFlightInsts->empty() && 1097 !(only_commit_microops && ex_info.lastCommitWasEndOfMacroop); 1098 1099 /* Can we find a mem response for this inst */ 1100 LSQ::LSQRequestPtr mem_response = 1101 (inst->inLSQ ? lsq.findResponse(inst) : NULL); 1102 1103 DPRINTF(MinorExecute, "Trying to commit canCommitInsts: %d\n", 1104 can_commit_insts); 1105 1106 /* Test for PC events after every instruction */ 1107 if (isInbetweenInsts(thread_id) && tryPCEvents(thread_id)) { 1108 ThreadContext *thread = cpu.getContext(thread_id); 1109 1110 /* Branch as there was a change in PC */ 1111 updateBranchData(thread_id, BranchData::UnpredictedBranch, 1112 MinorDynInst::bubble(), thread->pcState(), branch); 1113 } else if (mem_response && 1114 num_mem_refs_committed < memoryCommitLimit) 1115 { 1116 /* Try to commit from the memory responses next */ 1117 discard_inst = inst->id.streamSeqNum != 1118 ex_info.streamSeqNum || discard; 1119 1120 DPRINTF(MinorExecute, "Trying to commit mem response: %s\n", 1121 *inst); 1122 1123 /* Complete or discard the response */ 1124 if (discard_inst) { 1125 DPRINTF(MinorExecute, "Discarding mem inst: %s as its" 1126 " stream state was unexpected, expected: %d\n", 1127 *inst, ex_info.streamSeqNum); 1128 1129 lsq.popResponse(mem_response); 1130 } else { 1131 handleMemResponse(inst, mem_response, branch, fault); 1132 committed_inst = true; 1133 } 1134 1135 completed_mem_ref = true; 1136 completed_inst = true; 1137 } else if (can_commit_insts) { 1138 /* If true, this instruction will, subject to timing tweaks, 1139 * be considered for completion. try_to_commit flattens 1140 * the `if' tree a bit and allows other tests for inst 1141 * commit to be inserted here. */ 1142 bool try_to_commit = false; 1143 1144 /* Try and issue memory ops early if they: 1145 * - Can push a request into the LSQ 1146 * - Have reached the end of their FUs 1147 * - Have had all their dependencies satisfied 1148 * - Are from the right stream 1149 * 1150 * For any other case, leave it to the normal instruction 1151 * issue below to handle them. 1152 */ 1153 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) { 1154 DPRINTF(MinorExecute, "Trying to commit from mem FUs\n"); 1155 1156 const MinorDynInstPtr head_mem_ref_inst = 1157 ex_info.inFUMemInsts->front().inst; 1158 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex]; 1159 const MinorDynInstPtr &fu_inst = fu->front().inst; 1160 1161 /* Use this, possibly out of order, inst as the one 1162 * to 'commit'/send to the LSQ */ 1163 if (!fu_inst->isBubble() && 1164 !fu_inst->inLSQ && 1165 fu_inst->canEarlyIssue && 1166 ex_info.streamSeqNum == fu_inst->id.streamSeqNum && 1167 head_exec_seq_num > fu_inst->instToWaitFor) 1168 { 1169 DPRINTF(MinorExecute, "Issuing mem ref early" 1170 " inst: %s instToWaitFor: %d\n", 1171 *(fu_inst), fu_inst->instToWaitFor); 1172 1173 inst = fu_inst; 1174 try_to_commit = true; 1175 early_memory_issue = true; 1176 completed_inst = true; 1177 } 1178 } 1179 1180 /* Try and commit FU-less insts */ 1181 if (!completed_inst && inst->isNoCostInst()) { 1182 DPRINTF(MinorExecute, "Committing no cost inst: %s", *inst); 1183 1184 try_to_commit = true; 1185 completed_inst = true; 1186 } 1187 1188 /* Try to issue from the ends of FUs and the inFlightInsts 1189 * queue */ 1190 if (!completed_inst && !inst->inLSQ) { 1191 DPRINTF(MinorExecute, "Trying to commit from FUs\n"); 1192 1193 /* Try to commit from a functional unit */ 1194 /* Is the head inst of the expected inst's FU actually the 1195 * expected inst? */ 1196 QueuedInst &fu_inst = 1197 funcUnits[inst->fuIndex]->front(); 1198 InstSeqNum fu_inst_seq_num = fu_inst.inst->id.execSeqNum; 1199 1200 if (fu_inst.inst->isBubble()) { 1201 /* No instruction ready */ 1202 completed_inst = false; 1203 } else if (fu_inst_seq_num != head_exec_seq_num) { 1204 /* Past instruction: we must have already executed it 1205 * in the same cycle and so the head inst isn't 1206 * actually at the end of its pipeline 1207 * Future instruction: handled above and only for 1208 * mem refs on their way to the LSQ */ 1209 } else if (fu_inst.inst->id == inst->id) { 1210 /* All instructions can be committed if they have the 1211 * right execSeqNum and there are no in-flight 1212 * mem insts before us */ 1213 try_to_commit = true; 1214 completed_inst = true; 1215 } 1216 } 1217 1218 if (try_to_commit) { 1219 discard_inst = inst->id.streamSeqNum != 1220 ex_info.streamSeqNum || discard; 1221 1222 /* Is this instruction discardable as its streamSeqNum 1223 * doesn't match? */ 1224 if (!discard_inst) { 1225 /* Try to commit or discard a non-memory instruction. 1226 * Memory ops are actually 'committed' from this FUs 1227 * and 'issued' into the memory system so we need to 1228 * account for them later (commit_was_mem_issue gets 1229 * set) */ 1230 if (inst->extraCommitDelayExpr) { 1231 DPRINTF(MinorExecute, "Evaluating expression for" 1232 " extra commit delay inst: %s\n", *inst); 1233 1234 ThreadContext *thread = cpu.getContext(thread_id); 1235 1236 TimingExprEvalContext context(inst->staticInst, 1237 thread, NULL); 1238 1239 uint64_t extra_delay = inst->extraCommitDelayExpr-> 1240 eval(context); 1241 1242 DPRINTF(MinorExecute, "Extra commit delay expr" 1243 " result: %d\n", extra_delay); 1244 1245 if (extra_delay < 128) { 1246 inst->extraCommitDelay += Cycles(extra_delay); 1247 } else { 1248 DPRINTF(MinorExecute, "Extra commit delay was" 1249 " very long: %d\n", extra_delay); 1250 } 1251 inst->extraCommitDelayExpr = NULL; 1252 } 1253 1254 /* Move the extraCommitDelay from the instruction 1255 * into the minimumCommitCycle */ 1256 if (inst->extraCommitDelay != Cycles(0)) { 1257 inst->minimumCommitCycle = cpu.curCycle() + 1258 inst->extraCommitDelay; 1259 inst->extraCommitDelay = Cycles(0); 1260 } 1261 1262 /* @todo Think about making lastMemBarrier be 1263 * MAX_UINT_64 to avoid using 0 as a marker value */ 1264 if (!inst->isFault() && inst->isMemRef() && 1265 lsq.getLastMemBarrier(thread_id) < 1266 inst->id.execSeqNum && 1267 lsq.getLastMemBarrier(thread_id) != 0) 1268 { 1269 DPRINTF(MinorExecute, "Not committing inst: %s yet" 1270 " as there are incomplete barriers in flight\n", 1271 *inst); 1272 completed_inst = false; 1273 } else if (inst->minimumCommitCycle > now) { 1274 DPRINTF(MinorExecute, "Not committing inst: %s yet" 1275 " as it wants to be stalled for %d more cycles\n", 1276 *inst, inst->minimumCommitCycle - now); 1277 completed_inst = false; 1278 } else { 1279 completed_inst = commitInst(inst, 1280 early_memory_issue, branch, fault, 1281 committed_inst, issued_mem_ref); 1282 } 1283 } else { 1284 /* Discard instruction */ 1285 completed_inst = true; 1286 } 1287 1288 if (completed_inst) { 1289 /* Allow the pipeline to advance. If the FU head 1290 * instruction wasn't the inFlightInsts head 1291 * but had already been committed, it would have 1292 * unstalled the pipeline before here */ 1293 if (inst->fuIndex != noCostFUIndex) { 1294 DPRINTF(MinorExecute, "Unstalling %d for inst %s\n", inst->fuIndex, inst->id); 1295 funcUnits[inst->fuIndex]->stalled = false; 1296 } 1297 } 1298 } 1299 } else { 1300 DPRINTF(MinorExecute, "No instructions to commit\n"); 1301 completed_inst = false; 1302 } 1303 1304 /* All discardable instructions must also be 'completed' by now */ 1305 assert(!(discard_inst && !completed_inst)); 1306 1307 /* Instruction committed but was discarded due to streamSeqNum 1308 * mismatch */ 1309 if (discard_inst) { 1310 DPRINTF(MinorExecute, "Discarding inst: %s as its stream" 1311 " state was unexpected, expected: %d\n", 1312 *inst, ex_info.streamSeqNum); 1313 1314 if (fault == NoFault) 1315 cpu.stats.numDiscardedOps++; 1316 } 1317 1318 /* Mark the mem inst as being in the LSQ */ 1319 if (issued_mem_ref) { 1320 inst->fuIndex = 0; 1321 inst->inLSQ = true; 1322 } 1323 1324 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts 1325 * as they've *definitely* exited the FUs */ 1326 if (completed_inst && inst->isMemRef()) { 1327 /* The MemRef could have been discarded from the FU or the memory 1328 * queue, so just check an FU instruction */ 1329 if (!ex_info.inFUMemInsts->empty() && 1330 ex_info.inFUMemInsts->front().inst == inst) 1331 { 1332 ex_info.inFUMemInsts->pop(); 1333 } 1334 } 1335 1336 if (completed_inst && !(issued_mem_ref && fault == NoFault)) { 1337 /* Note that this includes discarded insts */ 1338 DPRINTF(MinorExecute, "Completed inst: %s\n", *inst); 1339 1340 /* Got to the end of a full instruction? */ 1341 ex_info.lastCommitWasEndOfMacroop = inst->isFault() || 1342 inst->isLastOpInInst(); 1343 1344 /* lastPredictionSeqNum is kept as a convenience to prevent its 1345 * value from changing too much on the minorview display */ 1346 ex_info.lastPredictionSeqNum = inst->id.predictionSeqNum; 1347 1348 /* Finished with the inst, remove it from the inst queue and 1349 * clear its dependencies */ 1350 ex_info.inFlightInsts->pop(); 1351 1352 /* Complete barriers in the LSQ/move to store buffer */ 1353 if (inst->isInst() && inst->staticInst->isMemBarrier()) { 1354 DPRINTF(MinorMem, "Completing memory barrier" 1355 " inst: %s committed: %d\n", *inst, committed_inst); 1356 lsq.completeMemBarrierInst(inst, committed_inst); 1357 } 1358 1359 scoreboard[thread_id].clearInstDests(inst, inst->isMemRef()); 1360 } 1361 1362 /* Handle per-cycle instruction counting */ 1363 if (committed_inst) { 1364 bool is_no_cost_inst = inst->isNoCostInst(); 1365 1366 /* Don't show no cost instructions as having taken a commit 1367 * slot */ 1368 if (DTRACE(MinorTrace) && !is_no_cost_inst) 1369 ex_info.instsBeingCommitted.insts[num_insts_committed] = inst; 1370 1371 if (!is_no_cost_inst) 1372 num_insts_committed++; 1373 1374 if (num_insts_committed == commitLimit) 1375 DPRINTF(MinorExecute, "Reached inst commit limit\n"); 1376 1377 /* Re-set the time of the instruction if that's required for 1378 * tracing */ 1379 if (inst->traceData) { 1380 if (setTraceTimeOnCommit) 1381 inst->traceData->setWhen(curTick()); 1382 inst->traceData->dump(); 1383 } 1384 1385 if (completed_mem_ref) 1386 num_mem_refs_committed++; 1387 1388 if (num_mem_refs_committed == memoryCommitLimit) 1389 DPRINTF(MinorExecute, "Reached mem ref commit limit\n"); 1390 } 1391 } 1392} 1393 1394bool 1395Execute::isInbetweenInsts(ThreadID thread_id) const 1396{ 1397 return executeInfo[thread_id].lastCommitWasEndOfMacroop && 1398 !lsq.accessesInFlight(); 1399} 1400 1401void 1402Execute::evaluate() 1403{ 1404 if (!inp.outputWire->isBubble()) 1405 inputBuffer[inp.outputWire->threadId].setTail(*inp.outputWire); 1406 1407 BranchData &branch = *out.inputWire; 1408 1409 unsigned int num_issued = 0; 1410 1411 /* Do all the cycle-wise activities for dcachePort here to potentially 1412 * free up input spaces in the LSQ's requests queue */ 1413 lsq.step(); 1414 1415 /* Check interrupts first. Will halt commit if interrupt found */ 1416 bool interrupted = false; 1417 ThreadID interrupt_tid = checkInterrupts(branch, interrupted); 1418 1419 if (interrupt_tid != InvalidThreadID) { 1420 /* Signalling an interrupt this cycle, not issuing/committing from 1421 * any other threads */ 1422 } else if (!branch.isBubble()) { 1423 /* It's important that this is here to carry Fetch1 wakeups to Fetch1 1424 * without overwriting them */ 1425 DPRINTF(MinorInterrupt, "Execute skipping a cycle to allow old" 1426 " branch to complete\n"); 1427 } else { 1428 ThreadID commit_tid = getCommittingThread(); 1429 1430 if (commit_tid != InvalidThreadID) { 1431 ExecuteThreadInfo& commit_info = executeInfo[commit_tid]; 1432 1433 DPRINTF(MinorExecute, "Attempting to commit [tid:%d]\n", 1434 commit_tid); 1435 /* commit can set stalled flags observable to issue and so *must* be 1436 * called first */ 1437 if (commit_info.drainState != NotDraining) { 1438 if (commit_info.drainState == DrainCurrentInst) { 1439 /* Commit only micro-ops, don't kill anything else */ 1440 commit(commit_tid, true, false, branch); 1441 1442 if (isInbetweenInsts(commit_tid)) 1443 setDrainState(commit_tid, DrainHaltFetch); 1444 1445 /* Discard any generated branch */ 1446 branch = BranchData::bubble(); 1447 } else if (commit_info.drainState == DrainAllInsts) { 1448 /* Kill all instructions */ 1449 while (getInput(commit_tid)) 1450 popInput(commit_tid); 1451 commit(commit_tid, false, true, branch); 1452 } 1453 } else { 1454 /* Commit micro-ops only if interrupted. Otherwise, commit 1455 * anything you like */ 1456 DPRINTF(MinorExecute, "Committing micro-ops for interrupt[tid:%d]\n", 1457 commit_tid); 1458 bool only_commit_microops = interrupted && 1459 hasInterrupt(commit_tid); 1460 commit(commit_tid, only_commit_microops, false, branch); 1461 } 1462 1463 /* Halt fetch, but don't do it until we have the current instruction in 1464 * the bag */ 1465 if (commit_info.drainState == DrainHaltFetch) { 1466 updateBranchData(commit_tid, BranchData::HaltFetch, 1467 MinorDynInst::bubble(), TheISA::PCState(0), branch); 1468 1469 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1470 setDrainState(commit_tid, DrainAllInsts); 1471 } 1472 } 1473 ThreadID issue_tid = getIssuingThread(); 1474 /* This will issue merrily even when interrupted in the sure and 1475 * certain knowledge that the interrupt with change the stream */ 1476 if (issue_tid != InvalidThreadID) { 1477 DPRINTF(MinorExecute, "Attempting to issue [tid:%d]\n", 1478 issue_tid); 1479 num_issued = issue(issue_tid); 1480 } 1481 1482 } 1483 1484 /* Run logic to step functional units + decide if we are active on the next 1485 * clock cycle */ 1486 std::vector<MinorDynInstPtr> next_issuable_insts; 1487 bool can_issue_next = false; 1488 1489 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1490 /* Find the next issuable instruction for each thread and see if it can 1491 be issued */ 1492 if (getInput(tid)) { 1493 unsigned int input_index = executeInfo[tid].inputIndex; 1494 MinorDynInstPtr inst = getInput(tid)->insts[input_index]; 1495 if (inst->isFault()) { 1496 can_issue_next = true; 1497 } else if (!inst->isBubble()) { 1498 next_issuable_insts.push_back(inst); 1499 } 1500 } 1501 } 1502 1503 bool becoming_stalled = true; 1504 1505 /* Advance the pipelines and note whether they still need to be 1506 * advanced */ 1507 for (unsigned int i = 0; i < numFuncUnits; i++) { 1508 FUPipeline *fu = funcUnits[i]; 1509 fu->advance(); 1510 1511 /* If we need to tick again, the pipeline will have been left or set 1512 * to be unstalled */ 1513 if (fu->occupancy !=0 && !fu->stalled) 1514 becoming_stalled = false; 1515 1516 /* Could we possibly issue the next instruction from any thread? 1517 * This is quite an expensive test and is only used to determine 1518 * if the CPU should remain active, only run it if we aren't sure 1519 * we are active next cycle yet */ 1520 for (auto inst : next_issuable_insts) { 1521 if (!fu->stalled && fu->provides(inst->staticInst->opClass()) && 1522 scoreboard[inst->id.threadId].canInstIssue(inst, 1523 NULL, NULL, cpu.curCycle() + Cycles(1), 1524 cpu.getContext(inst->id.threadId))) { 1525 can_issue_next = true; 1526 break; 1527 } 1528 } 1529 } 1530 1531 bool head_inst_might_commit = false; 1532 1533 /* Could the head in flight insts be committed */ 1534 for (auto const &info : executeInfo) { 1535 if (!info.inFlightInsts->empty()) { 1536 const QueuedInst &head_inst = info.inFlightInsts->front(); 1537 1538 if (head_inst.inst->isNoCostInst()) { 1539 head_inst_might_commit = true; 1540 } else { 1541 FUPipeline *fu = funcUnits[head_inst.inst->fuIndex]; 1542 if ((fu->stalled && 1543 fu->front().inst->id == head_inst.inst->id) || 1544 lsq.findResponse(head_inst.inst)) 1545 { 1546 head_inst_might_commit = true; 1547 break; 1548 } 1549 } 1550 } 1551 } 1552 1553 DPRINTF(Activity, "Need to tick num issued insts: %s%s%s%s%s%s\n", 1554 (num_issued != 0 ? " (issued some insts)" : ""), 1555 (becoming_stalled ? "(becoming stalled)" : "(not becoming stalled)"), 1556 (can_issue_next ? " (can issued next inst)" : ""), 1557 (head_inst_might_commit ? "(head inst might commit)" : ""), 1558 (lsq.needsToTick() ? " (LSQ needs to tick)" : ""), 1559 (interrupted ? " (interrupted)" : "")); 1560 1561 bool need_to_tick = 1562 num_issued != 0 || /* Issued some insts this cycle */ 1563 !becoming_stalled || /* Some FU pipelines can still move */ 1564 can_issue_next || /* Can still issue a new inst */ 1565 head_inst_might_commit || /* Could possible commit the next inst */ 1566 lsq.needsToTick() || /* Must step the dcache port */ 1567 interrupted; /* There are pending interrupts */ 1568 1569 if (!need_to_tick) { 1570 DPRINTF(Activity, "The next cycle might be skippable as there are no" 1571 " advanceable FUs\n"); 1572 } 1573 1574 /* Wake up if we need to tick again */ 1575 if (need_to_tick) 1576 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1577 1578 /* Note activity of following buffer */ 1579 if (!branch.isBubble()) 1580 cpu.activityRecorder->activity(); 1581 1582 /* Make sure the input (if any left) is pushed */ 1583 if (!inp.outputWire->isBubble()) 1584 inputBuffer[inp.outputWire->threadId].pushTail(); 1585} 1586 1587ThreadID 1588Execute::checkInterrupts(BranchData& branch, bool& interrupted) 1589{ 1590 ThreadID tid = interruptPriority; 1591 /* Evaluate interrupts in round-robin based upon service */ 1592 do { 1593 /* Has an interrupt been signalled? This may not be acted on 1594 * straighaway so this is different from took_interrupt */ 1595 bool thread_interrupted = false; 1596 1597 if (FullSystem && cpu.getInterruptController(tid)) { 1598 /* This is here because it seems that after drainResume the 1599 * interrupt controller isn't always set */ 1600 thread_interrupted = executeInfo[tid].drainState == NotDraining && 1601 isInterrupted(tid); 1602 interrupted = interrupted || thread_interrupted; 1603 } else { 1604 DPRINTF(MinorInterrupt, "No interrupt controller\n"); 1605 } 1606 DPRINTF(MinorInterrupt, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n", 1607 tid, thread_interrupted, isInbetweenInsts(tid)); 1608 /* Act on interrupts */ 1609 if (thread_interrupted && isInbetweenInsts(tid)) { 1610 if (takeInterrupt(tid, branch)) { 1611 interruptPriority = tid; 1612 return tid; 1613 } 1614 } else { 1615 tid = (tid + 1) % cpu.numThreads; 1616 } 1617 } while (tid != interruptPriority); 1618 1619 return InvalidThreadID; 1620} 1621 1622bool 1623Execute::hasInterrupt(ThreadID thread_id) 1624{ 1625 if (FullSystem && cpu.getInterruptController(thread_id)) { 1626 return executeInfo[thread_id].drainState == NotDraining && 1627 isInterrupted(thread_id); 1628 } 1629 1630 return false; 1631} 1632 1633void 1634Execute::minorTrace() const 1635{ 1636 std::ostringstream insts; 1637 std::ostringstream stalled; 1638 1639 executeInfo[0].instsBeingCommitted.reportData(insts); 1640 lsq.minorTrace(); 1641 inputBuffer[0].minorTrace(); 1642 scoreboard[0].minorTrace(); 1643 1644 /* Report functional unit stalling in one string */ 1645 unsigned int i = 0; 1646 while (i < numFuncUnits) 1647 { 1648 stalled << (funcUnits[i]->stalled ? '1' : 'E'); 1649 i++; 1650 if (i != numFuncUnits) 1651 stalled << ','; 1652 } 1653 1654 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d" 1655 " stalled=%s drainState=%d isInbetweenInsts=%d\n", 1656 insts.str(), executeInfo[0].inputIndex, executeInfo[0].streamSeqNum, 1657 stalled.str(), executeInfo[0].drainState, isInbetweenInsts(0)); 1658 1659 std::for_each(funcUnits.begin(), funcUnits.end(), 1660 std::mem_fun(&FUPipeline::minorTrace)); 1661 1662 executeInfo[0].inFlightInsts->minorTrace(); 1663 executeInfo[0].inFUMemInsts->minorTrace(); 1664} 1665 1666inline ThreadID 1667Execute::getCommittingThread() 1668{ 1669 std::vector<ThreadID> priority_list; 1670 1671 switch (cpu.threadPolicy) { 1672 case Enums::SingleThreaded: 1673 return 0; 1674 case Enums::RoundRobin: 1675 priority_list = cpu.roundRobinPriority(commitPriority); 1676 break; 1677 case Enums::Random: 1678 priority_list = cpu.randomPriority(); 1679 break; 1680 default: 1681 panic("Invalid thread policy"); 1682 } 1683 1684 for (auto tid : priority_list) { 1685 ExecuteThreadInfo &ex_info = executeInfo[tid]; 1686 1687 bool is_thread_active = 1688 cpu.getContext(tid)->status() == ThreadContext::Active; 1689 bool can_commit_insts = !ex_info.inFlightInsts->empty() && 1690 is_thread_active; 1691 1692 if (can_commit_insts) { 1693 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front()); 1694 MinorDynInstPtr inst = head_inflight_inst->inst; 1695 1696 can_commit_insts = can_commit_insts && 1697 (!inst->inLSQ || (lsq.findResponse(inst) != NULL)); 1698 1699 if (!inst->inLSQ) { 1700 bool can_transfer_mem_inst = false; 1701 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) { 1702 const MinorDynInstPtr head_mem_ref_inst = 1703 ex_info.inFUMemInsts->front().inst; 1704 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex]; 1705 const MinorDynInstPtr &fu_inst = fu->front().inst; 1706 can_transfer_mem_inst = 1707 !fu_inst->isBubble() && 1708 fu_inst->id.threadId == tid && 1709 !fu_inst->inLSQ && 1710 fu_inst->canEarlyIssue && 1711 inst->id.execSeqNum > fu_inst->instToWaitFor; 1712 } 1713 1714 bool can_execute_fu_inst = inst->fuIndex == noCostFUIndex; 1715 if (can_commit_insts && !can_transfer_mem_inst && 1716 inst->fuIndex != noCostFUIndex) 1717 { 1718 QueuedInst& fu_inst = funcUnits[inst->fuIndex]->front(); 1719 can_execute_fu_inst = !fu_inst.inst->isBubble() && 1720 fu_inst.inst->id == inst->id; 1721 } 1722 1723 can_commit_insts = can_commit_insts && 1724 (can_transfer_mem_inst || can_execute_fu_inst); 1725 } 1726 } 1727 1728 1729 if (can_commit_insts) { 1730 commitPriority = tid; 1731 return tid; 1732 } 1733 } 1734 1735 return InvalidThreadID; 1736} 1737 1738inline ThreadID 1739Execute::getIssuingThread() 1740{ 1741 std::vector<ThreadID> priority_list; 1742 1743 switch (cpu.threadPolicy) { 1744 case Enums::SingleThreaded: 1745 return 0; 1746 case Enums::RoundRobin: 1747 priority_list = cpu.roundRobinPriority(issuePriority); 1748 break; 1749 case Enums::Random: 1750 priority_list = cpu.randomPriority(); 1751 break; 1752 default: 1753 panic("Invalid thread scheduling policy."); 1754 } 1755 1756 for (auto tid : priority_list) { 1757 if (cpu.getContext(tid)->status() == ThreadContext::Active && 1758 getInput(tid)) { 1759 issuePriority = tid; 1760 return tid; 1761 } 1762 } 1763 1764 return InvalidThreadID; 1765} 1766 1767void 1768Execute::drainResume() 1769{ 1770 DPRINTF(Drain, "MinorExecute drainResume\n"); 1771 1772 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1773 setDrainState(tid, NotDraining); 1774 } 1775 1776 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1777} 1778 1779std::ostream &operator <<(std::ostream &os, Execute::DrainState state) 1780{ 1781 switch (state) 1782 { 1783 case Execute::NotDraining: 1784 os << "NotDraining"; 1785 break; 1786 case Execute::DrainCurrentInst: 1787 os << "DrainCurrentInst"; 1788 break; 1789 case Execute::DrainHaltFetch: 1790 os << "DrainHaltFetch"; 1791 break; 1792 case Execute::DrainAllInsts: 1793 os << "DrainAllInsts"; 1794 break; 1795 default: 1796 os << "Drain-" << static_cast<int>(state); 1797 break; 1798 } 1799 1800 return os; 1801} 1802 1803void 1804Execute::setDrainState(ThreadID thread_id, DrainState state) 1805{ 1806 DPRINTF(Drain, "setDrainState[%d]: %s\n", thread_id, state); 1807 executeInfo[thread_id].drainState = state; 1808} 1809 1810unsigned int 1811Execute::drain() 1812{ 1813 DPRINTF(Drain, "MinorExecute drain\n"); 1814 1815 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1816 if (executeInfo[tid].drainState == NotDraining) { 1817 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); 1818 1819 /* Go to DrainCurrentInst if we're between microops 1820 * or waiting on an unbufferable memory operation. 1821 * Otherwise we can go straight to DrainHaltFetch 1822 */ 1823 if (isInbetweenInsts(tid)) 1824 setDrainState(tid, DrainHaltFetch); 1825 else 1826 setDrainState(tid, DrainCurrentInst); 1827 } 1828 } 1829 return (isDrained() ? 0 : 1); 1830} 1831 1832bool 1833Execute::isDrained() 1834{ 1835 if (!lsq.isDrained()) 1836 return false; 1837 1838 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 1839 if (!inputBuffer[tid].empty() || 1840 !executeInfo[tid].inFlightInsts->empty()) { 1841 1842 return false; 1843 } 1844 } 1845 1846 return true; 1847} 1848 1849Execute::~Execute() 1850{ 1851 for (unsigned int i = 0; i < numFuncUnits; i++) 1852 delete funcUnits[i]; 1853 1854 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) 1855 delete executeInfo[tid].inFlightInsts; 1856} 1857 1858bool 1859Execute::instIsRightStream(MinorDynInstPtr inst) 1860{ 1861 return inst->id.streamSeqNum == executeInfo[inst->id.threadId].streamSeqNum; 1862} 1863 1864bool 1865Execute::instIsHeadInst(MinorDynInstPtr inst) 1866{ 1867 bool ret = false; 1868 1869 if (!executeInfo[inst->id.threadId].inFlightInsts->empty()) 1870 ret = executeInfo[inst->id.threadId].inFlightInsts->front().inst->id == inst->id; 1871 1872 return ret; 1873} 1874 1875MinorCPU::MinorCPUPort & 1876Execute::getDcachePort() 1877{ 1878 return lsq.getDcachePort(); 1879} 1880 1881} 1882