exec_context.hh revision 13953:43ae8a30ec1f
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2011-2014, 2016-2018 ARM Limited 310259SAndrew.Bardsley@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 410259SAndrew.Bardsley@arm.com * All rights reserved 510259SAndrew.Bardsley@arm.com * 610259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 710259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 810259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 910259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 1010259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1110259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1210259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1310259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1410259SAndrew.Bardsley@arm.com * 1510259SAndrew.Bardsley@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1610259SAndrew.Bardsley@arm.com * All rights reserved. 1710259SAndrew.Bardsley@arm.com * 1810259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1910259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 2010259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 2110259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 2210259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 2310259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2410259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2510259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2610259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2710259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2810259SAndrew.Bardsley@arm.com * 2910259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4010259SAndrew.Bardsley@arm.com * 4110259SAndrew.Bardsley@arm.com * Authors: Steve Reinhardt 4210259SAndrew.Bardsley@arm.com * Dave Greene 4310259SAndrew.Bardsley@arm.com * Nathan Binkert 4410259SAndrew.Bardsley@arm.com * Andrew Bardsley 4510259SAndrew.Bardsley@arm.com */ 4610259SAndrew.Bardsley@arm.com 4710259SAndrew.Bardsley@arm.com/** 4810259SAndrew.Bardsley@arm.com * @file 4910785Sgope@wisc.edu * 5010259SAndrew.Bardsley@arm.com * ExecContext bears the exec_context interface for Minor. 5110259SAndrew.Bardsley@arm.com */ 5210259SAndrew.Bardsley@arm.com 5310259SAndrew.Bardsley@arm.com#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__ 5410259SAndrew.Bardsley@arm.com#define __CPU_MINOR_EXEC_CONTEXT_HH__ 5510259SAndrew.Bardsley@arm.com 5610259SAndrew.Bardsley@arm.com#include "cpu/exec_context.hh" 5710259SAndrew.Bardsley@arm.com#include "cpu/minor/execute.hh" 5810259SAndrew.Bardsley@arm.com#include "cpu/minor/pipeline.hh" 5910259SAndrew.Bardsley@arm.com#include "cpu/base.hh" 6010259SAndrew.Bardsley@arm.com#include "cpu/simple_thread.hh" 6110259SAndrew.Bardsley@arm.com#include "mem/request.hh" 6210259SAndrew.Bardsley@arm.com#include "debug/MinorExecute.hh" 6310259SAndrew.Bardsley@arm.com 6410259SAndrew.Bardsley@arm.comnamespace Minor 6510259SAndrew.Bardsley@arm.com{ 6610259SAndrew.Bardsley@arm.com 6710259SAndrew.Bardsley@arm.com/* Forward declaration of Execute */ 6810259SAndrew.Bardsley@arm.comclass Execute; 6910259SAndrew.Bardsley@arm.com 7010259SAndrew.Bardsley@arm.com/** ExecContext bears the exec_context interface for Minor. This nicely 7110259SAndrew.Bardsley@arm.com * separates that interface from other classes such as Pipeline, MinorCPU 7210259SAndrew.Bardsley@arm.com * and DynMinorInst and makes it easier to see what state is accessed by it. 7310259SAndrew.Bardsley@arm.com */ 7410259SAndrew.Bardsley@arm.comclass ExecContext : public ::ExecContext 7510259SAndrew.Bardsley@arm.com{ 7610259SAndrew.Bardsley@arm.com public: 7710259SAndrew.Bardsley@arm.com MinorCPU &cpu; 7810259SAndrew.Bardsley@arm.com 7910259SAndrew.Bardsley@arm.com /** ThreadState object, provides all the architectural state. */ 8010259SAndrew.Bardsley@arm.com SimpleThread &thread; 8110259SAndrew.Bardsley@arm.com 8210259SAndrew.Bardsley@arm.com /** The execute stage so we can peek at its contents. */ 8310259SAndrew.Bardsley@arm.com Execute &execute; 8410259SAndrew.Bardsley@arm.com 8510259SAndrew.Bardsley@arm.com /** Instruction for the benefit of memory operations and for PC */ 8610259SAndrew.Bardsley@arm.com MinorDynInstPtr inst; 8710259SAndrew.Bardsley@arm.com 8810259SAndrew.Bardsley@arm.com ExecContext ( 8910259SAndrew.Bardsley@arm.com MinorCPU &cpu_, 9010259SAndrew.Bardsley@arm.com SimpleThread &thread_, Execute &execute_, 9110259SAndrew.Bardsley@arm.com MinorDynInstPtr inst_) : 9210259SAndrew.Bardsley@arm.com cpu(cpu_), 9310259SAndrew.Bardsley@arm.com thread(thread_), 9410259SAndrew.Bardsley@arm.com execute(execute_), 9510259SAndrew.Bardsley@arm.com inst(inst_) 9610259SAndrew.Bardsley@arm.com { 9710259SAndrew.Bardsley@arm.com DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc); 9810259SAndrew.Bardsley@arm.com pcState(inst->pc); 9910259SAndrew.Bardsley@arm.com setPredicate(true); 10010259SAndrew.Bardsley@arm.com thread.setIntReg(TheISA::ZeroReg, 0); 10110259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA 10210259SAndrew.Bardsley@arm.com thread.setFloatReg(TheISA::ZeroReg, 0); 10310259SAndrew.Bardsley@arm.com#endif 10410259SAndrew.Bardsley@arm.com } 10510259SAndrew.Bardsley@arm.com 10610259SAndrew.Bardsley@arm.com Fault 10710259SAndrew.Bardsley@arm.com initiateMemRead(Addr addr, unsigned int size, 10810259SAndrew.Bardsley@arm.com Request::Flags flags) override 10910259SAndrew.Bardsley@arm.com { 11010259SAndrew.Bardsley@arm.com execute.getLSQ().pushRequest(inst, true /* load */, nullptr, 11110259SAndrew.Bardsley@arm.com size, addr, flags, NULL, nullptr); 11210259SAndrew.Bardsley@arm.com return NoFault; 11310259SAndrew.Bardsley@arm.com } 11410259SAndrew.Bardsley@arm.com 11510259SAndrew.Bardsley@arm.com Fault 11610259SAndrew.Bardsley@arm.com writeMem(uint8_t *data, unsigned int size, Addr addr, 11710259SAndrew.Bardsley@arm.com Request::Flags flags, uint64_t *res) override 11810259SAndrew.Bardsley@arm.com { 11910259SAndrew.Bardsley@arm.com execute.getLSQ().pushRequest(inst, false /* store */, data, 12010259SAndrew.Bardsley@arm.com size, addr, flags, res, nullptr); 12110259SAndrew.Bardsley@arm.com return NoFault; 12210259SAndrew.Bardsley@arm.com } 12310259SAndrew.Bardsley@arm.com 12410259SAndrew.Bardsley@arm.com Fault 12510259SAndrew.Bardsley@arm.com initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, 12610259SAndrew.Bardsley@arm.com AtomicOpFunctor *amo_op) override 12710259SAndrew.Bardsley@arm.com { 12810259SAndrew.Bardsley@arm.com // AMO requests are pushed through the store path 12910259SAndrew.Bardsley@arm.com execute.getLSQ().pushRequest(inst, false /* amo */, nullptr, 13010259SAndrew.Bardsley@arm.com size, addr, flags, nullptr, amo_op); 13110259SAndrew.Bardsley@arm.com return NoFault; 13210259SAndrew.Bardsley@arm.com } 13310259SAndrew.Bardsley@arm.com 13410259SAndrew.Bardsley@arm.com RegVal 13510259SAndrew.Bardsley@arm.com readIntRegOperand(const StaticInst *si, int idx) override 13610259SAndrew.Bardsley@arm.com { 13710259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 13810259SAndrew.Bardsley@arm.com assert(reg.isIntReg()); 13910259SAndrew.Bardsley@arm.com return thread.readIntReg(reg.index()); 14010259SAndrew.Bardsley@arm.com } 14110259SAndrew.Bardsley@arm.com 14210259SAndrew.Bardsley@arm.com RegVal 14310259SAndrew.Bardsley@arm.com readFloatRegOperandBits(const StaticInst *si, int idx) override 14410259SAndrew.Bardsley@arm.com { 14510259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 14610259SAndrew.Bardsley@arm.com assert(reg.isFloatReg()); 14710259SAndrew.Bardsley@arm.com return thread.readFloatReg(reg.index()); 14810259SAndrew.Bardsley@arm.com } 14910259SAndrew.Bardsley@arm.com 15010259SAndrew.Bardsley@arm.com const TheISA::VecRegContainer & 15110259SAndrew.Bardsley@arm.com readVecRegOperand(const StaticInst *si, int idx) const override 15210259SAndrew.Bardsley@arm.com { 15310259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 15410259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 15510259SAndrew.Bardsley@arm.com return thread.readVecReg(reg); 15610259SAndrew.Bardsley@arm.com } 15710259SAndrew.Bardsley@arm.com 15810259SAndrew.Bardsley@arm.com TheISA::VecRegContainer & 15910259SAndrew.Bardsley@arm.com getWritableVecRegOperand(const StaticInst *si, int idx) override 16010259SAndrew.Bardsley@arm.com { 16110259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 16210259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 16310259SAndrew.Bardsley@arm.com return thread.getWritableVecReg(reg); 16410259SAndrew.Bardsley@arm.com } 16510259SAndrew.Bardsley@arm.com 16610259SAndrew.Bardsley@arm.com TheISA::VecElem 16710259SAndrew.Bardsley@arm.com readVecElemOperand(const StaticInst *si, int idx) const override 16810259SAndrew.Bardsley@arm.com { 16910259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 17010259SAndrew.Bardsley@arm.com assert(reg.isVecElem()); 17110259SAndrew.Bardsley@arm.com return thread.readVecElem(reg); 17210259SAndrew.Bardsley@arm.com } 17310259SAndrew.Bardsley@arm.com 17410259SAndrew.Bardsley@arm.com const TheISA::VecPredRegContainer& 17510259SAndrew.Bardsley@arm.com readVecPredRegOperand(const StaticInst *si, int idx) const override 17610259SAndrew.Bardsley@arm.com { 17710259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 17810259SAndrew.Bardsley@arm.com assert(reg.isVecPredReg()); 17910259SAndrew.Bardsley@arm.com return thread.readVecPredReg(reg); 18010259SAndrew.Bardsley@arm.com } 18110259SAndrew.Bardsley@arm.com 18210259SAndrew.Bardsley@arm.com TheISA::VecPredRegContainer& 18310259SAndrew.Bardsley@arm.com getWritableVecPredRegOperand(const StaticInst *si, int idx) override 18410259SAndrew.Bardsley@arm.com { 18510259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 18610259SAndrew.Bardsley@arm.com assert(reg.isVecPredReg()); 18710259SAndrew.Bardsley@arm.com return thread.getWritableVecPredReg(reg); 18810259SAndrew.Bardsley@arm.com } 18910259SAndrew.Bardsley@arm.com 19010259SAndrew.Bardsley@arm.com void 19110259SAndrew.Bardsley@arm.com setIntRegOperand(const StaticInst *si, int idx, RegVal val) override 19210259SAndrew.Bardsley@arm.com { 19310259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 19410259SAndrew.Bardsley@arm.com assert(reg.isIntReg()); 19510259SAndrew.Bardsley@arm.com thread.setIntReg(reg.index(), val); 19610259SAndrew.Bardsley@arm.com } 19710259SAndrew.Bardsley@arm.com 19810259SAndrew.Bardsley@arm.com void 19910259SAndrew.Bardsley@arm.com setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override 20010259SAndrew.Bardsley@arm.com { 20110259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 20210259SAndrew.Bardsley@arm.com assert(reg.isFloatReg()); 20310259SAndrew.Bardsley@arm.com thread.setFloatReg(reg.index(), val); 20410259SAndrew.Bardsley@arm.com } 20510259SAndrew.Bardsley@arm.com 20610259SAndrew.Bardsley@arm.com void 20710259SAndrew.Bardsley@arm.com setVecRegOperand(const StaticInst *si, int idx, 20810259SAndrew.Bardsley@arm.com const TheISA::VecRegContainer& val) override 20910259SAndrew.Bardsley@arm.com { 21010259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 21110259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 21210259SAndrew.Bardsley@arm.com thread.setVecReg(reg, val); 21310259SAndrew.Bardsley@arm.com } 21410259SAndrew.Bardsley@arm.com 21510259SAndrew.Bardsley@arm.com void 21610259SAndrew.Bardsley@arm.com setVecPredRegOperand(const StaticInst *si, int idx, 21710259SAndrew.Bardsley@arm.com const TheISA::VecPredRegContainer& val) override 21810259SAndrew.Bardsley@arm.com { 21910259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 22010259SAndrew.Bardsley@arm.com assert(reg.isVecPredReg()); 22110259SAndrew.Bardsley@arm.com thread.setVecPredReg(reg, val); 22210259SAndrew.Bardsley@arm.com } 22310259SAndrew.Bardsley@arm.com 22410259SAndrew.Bardsley@arm.com /** Vector Register Lane Interfaces. */ 22510259SAndrew.Bardsley@arm.com /** @{ */ 22610259SAndrew.Bardsley@arm.com /** Reads source vector 8bit operand. */ 22710259SAndrew.Bardsley@arm.com ConstVecLane8 22810259SAndrew.Bardsley@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const 22910259SAndrew.Bardsley@arm.com override 23010259SAndrew.Bardsley@arm.com { 23110259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 23210259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 23310259SAndrew.Bardsley@arm.com return thread.readVec8BitLaneReg(reg); 23410259SAndrew.Bardsley@arm.com } 23510259SAndrew.Bardsley@arm.com 23610259SAndrew.Bardsley@arm.com /** Reads source vector 16bit operand. */ 23710259SAndrew.Bardsley@arm.com ConstVecLane16 23810259SAndrew.Bardsley@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const 23910259SAndrew.Bardsley@arm.com override 24010259SAndrew.Bardsley@arm.com { 24110259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 24210259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 24310259SAndrew.Bardsley@arm.com return thread.readVec16BitLaneReg(reg); 24410259SAndrew.Bardsley@arm.com } 24510259SAndrew.Bardsley@arm.com 24610259SAndrew.Bardsley@arm.com /** Reads source vector 32bit operand. */ 24710259SAndrew.Bardsley@arm.com ConstVecLane32 24810259SAndrew.Bardsley@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 24910259SAndrew.Bardsley@arm.com override 25010259SAndrew.Bardsley@arm.com { 25110259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 25210259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 25310259SAndrew.Bardsley@arm.com return thread.readVec32BitLaneReg(reg); 25410259SAndrew.Bardsley@arm.com } 25510259SAndrew.Bardsley@arm.com 25610259SAndrew.Bardsley@arm.com /** Reads source vector 64bit operand. */ 25710259SAndrew.Bardsley@arm.com ConstVecLane64 25810259SAndrew.Bardsley@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 25910259SAndrew.Bardsley@arm.com override 26010259SAndrew.Bardsley@arm.com { 26110259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 26210259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 26310259SAndrew.Bardsley@arm.com return thread.readVec64BitLaneReg(reg); 26410259SAndrew.Bardsley@arm.com } 26510259SAndrew.Bardsley@arm.com 26610259SAndrew.Bardsley@arm.com /** Write a lane of the destination vector operand. */ 26710259SAndrew.Bardsley@arm.com template <typename LD> 26810259SAndrew.Bardsley@arm.com void 26910785Sgope@wisc.edu setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 27010259SAndrew.Bardsley@arm.com { 27110259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 27210259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 27310259SAndrew.Bardsley@arm.com return thread.setVecLane(reg, val); 27410259SAndrew.Bardsley@arm.com } 275 virtual void 276 setVecLaneOperand(const StaticInst *si, int idx, 277 const LaneData<LaneSize::Byte>& val) override 278 { 279 setVecLaneOperandT(si, idx, val); 280 } 281 virtual void 282 setVecLaneOperand(const StaticInst *si, int idx, 283 const LaneData<LaneSize::TwoByte>& val) override 284 { 285 setVecLaneOperandT(si, idx, val); 286 } 287 virtual void 288 setVecLaneOperand(const StaticInst *si, int idx, 289 const LaneData<LaneSize::FourByte>& val) override 290 { 291 setVecLaneOperandT(si, idx, val); 292 } 293 virtual void 294 setVecLaneOperand(const StaticInst *si, int idx, 295 const LaneData<LaneSize::EightByte>& val) override 296 { 297 setVecLaneOperandT(si, idx, val); 298 } 299 /** @} */ 300 301 void 302 setVecElemOperand(const StaticInst *si, int idx, 303 const TheISA::VecElem val) override 304 { 305 const RegId& reg = si->destRegIdx(idx); 306 assert(reg.isVecElem()); 307 thread.setVecElem(reg, val); 308 } 309 310 bool 311 readPredicate() const override 312 { 313 return thread.readPredicate(); 314 } 315 316 void 317 setPredicate(bool val) override 318 { 319 thread.setPredicate(val); 320 } 321 322 bool 323 readMemAccPredicate() const override 324 { 325 return thread.readMemAccPredicate(); 326 } 327 328 void 329 setMemAccPredicate(bool val) override 330 { 331 thread.setMemAccPredicate(val); 332 } 333 334 TheISA::PCState 335 pcState() const override 336 { 337 return thread.pcState(); 338 } 339 340 void 341 pcState(const TheISA::PCState &val) override 342 { 343 thread.pcState(val); 344 } 345 346 RegVal 347 readMiscRegNoEffect(int misc_reg) const 348 { 349 return thread.readMiscRegNoEffect(misc_reg); 350 } 351 352 RegVal 353 readMiscReg(int misc_reg) override 354 { 355 return thread.readMiscReg(misc_reg); 356 } 357 358 void 359 setMiscReg(int misc_reg, RegVal val) override 360 { 361 thread.setMiscReg(misc_reg, val); 362 } 363 364 RegVal 365 readMiscRegOperand(const StaticInst *si, int idx) override 366 { 367 const RegId& reg = si->srcRegIdx(idx); 368 assert(reg.isMiscReg()); 369 return thread.readMiscReg(reg.index()); 370 } 371 372 void 373 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override 374 { 375 const RegId& reg = si->destRegIdx(idx); 376 assert(reg.isMiscReg()); 377 return thread.setMiscReg(reg.index(), val); 378 } 379 380 void 381 syscall(int64_t callnum, Fault *fault) override 382 { 383 if (FullSystem) 384 panic("Syscall emulation isn't available in FS mode.\n"); 385 386 thread.syscall(callnum, fault); 387 } 388 389 ThreadContext *tcBase() override { return thread.getTC(); } 390 391 /* @todo, should make stCondFailures persistent somewhere */ 392 unsigned int readStCondFailures() const override { return 0; } 393 void setStCondFailures(unsigned int st_cond_failures) override {} 394 395 ContextID contextId() { return thread.contextId(); } 396 /* ISA-specific (or at least currently ISA singleton) functions */ 397 398 /* X86: TLB twiddling */ 399 void 400 demapPage(Addr vaddr, uint64_t asn) override 401 { 402 thread.getITBPtr()->demapPage(vaddr, asn); 403 thread.getDTBPtr()->demapPage(vaddr, asn); 404 } 405 406 RegVal 407 readCCRegOperand(const StaticInst *si, int idx) override 408 { 409 const RegId& reg = si->srcRegIdx(idx); 410 assert(reg.isCCReg()); 411 return thread.readCCReg(reg.index()); 412 } 413 414 void 415 setCCRegOperand(const StaticInst *si, int idx, RegVal val) override 416 { 417 const RegId& reg = si->destRegIdx(idx); 418 assert(reg.isCCReg()); 419 thread.setCCReg(reg.index(), val); 420 } 421 422 void 423 demapInstPage(Addr vaddr, uint64_t asn) 424 { 425 thread.getITBPtr()->demapPage(vaddr, asn); 426 } 427 428 void 429 demapDataPage(Addr vaddr, uint64_t asn) 430 { 431 thread.getDTBPtr()->demapPage(vaddr, asn); 432 } 433 434 BaseCPU *getCpuPtr() { return &cpu; } 435 436 public: 437 // monitor/mwait funtions 438 void armMonitor(Addr address) override 439 { getCpuPtr()->armMonitor(inst->id.threadId, address); } 440 441 bool mwait(PacketPtr pkt) override 442 { return getCpuPtr()->mwait(inst->id.threadId, pkt); } 443 444 void mwaitAtomic(ThreadContext *tc) override 445 { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); } 446 447 AddressMonitor *getAddrMonitor() override 448 { return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId); } 449}; 450 451} 452 453#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */ 454