exec_context.hh revision 13628:332f730a1855
114049Snikos.nikoleris@arm.com/* 28839Sandreas.hansson@arm.com * Copyright (c) 2011-2014, 2016-2017 ARM Limited 38839Sandreas.hansson@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48839Sandreas.hansson@arm.com * All rights reserved 58839Sandreas.hansson@arm.com * 68839Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 78839Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 88839Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 98839Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 108839Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 118839Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 128839Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 133101Sstever@eecs.umich.edu * modified or unmodified, in source code or in binary form. 148579Ssteve.reinhardt@amd.com * 153101Sstever@eecs.umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 163101Sstever@eecs.umich.edu * All rights reserved. 173101Sstever@eecs.umich.edu * 183101Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 193101Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 203101Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 213101Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 223101Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 233101Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 243101Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 253101Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 263101Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 273101Sstever@eecs.umich.edu * this software without specific prior written permission. 283101Sstever@eecs.umich.edu * 293101Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303101Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313101Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323101Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333101Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343101Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353101Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363101Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373101Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383101Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393101Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403101Sstever@eecs.umich.edu * 413101Sstever@eecs.umich.edu * Authors: Steve Reinhardt 427778Sgblack@eecs.umich.edu * Dave Greene 438839Sandreas.hansson@arm.com * Nathan Binkert 443101Sstever@eecs.umich.edu * Andrew Bardsley 453101Sstever@eecs.umich.edu */ 463101Sstever@eecs.umich.edu 473101Sstever@eecs.umich.edu/** 483101Sstever@eecs.umich.edu * @file 493101Sstever@eecs.umich.edu * 503101Sstever@eecs.umich.edu * ExecContext bears the exec_context interface for Minor. 513101Sstever@eecs.umich.edu */ 523101Sstever@eecs.umich.edu 533101Sstever@eecs.umich.edu#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__ 543101Sstever@eecs.umich.edu#define __CPU_MINOR_EXEC_CONTEXT_HH__ 553101Sstever@eecs.umich.edu 563101Sstever@eecs.umich.edu#include "cpu/exec_context.hh" 573101Sstever@eecs.umich.edu#include "cpu/minor/execute.hh" 583101Sstever@eecs.umich.edu#include "cpu/minor/pipeline.hh" 593101Sstever@eecs.umich.edu#include "cpu/base.hh" 603101Sstever@eecs.umich.edu#include "cpu/simple_thread.hh" 613101Sstever@eecs.umich.edu#include "mem/request.hh" 6212563Sgabeblack@google.com#include "debug/MinorExecute.hh" 6313719Sandreas.sandberg@arm.com 6413719Sandreas.sandberg@arm.comnamespace Minor 6513719Sandreas.sandberg@arm.com{ 6612563Sgabeblack@google.com 673885Sbinkertn@umich.edu/* Forward declaration of Execute */ 683885Sbinkertn@umich.educlass Execute; 694762Snate@binkert.org 703885Sbinkertn@umich.edu/** ExecContext bears the exec_context interface for Minor. This nicely 713885Sbinkertn@umich.edu * separates that interface from other classes such as Pipeline, MinorCPU 727528Ssteve.reinhardt@amd.com * and DynMinorInst and makes it easier to see what state is accessed by it. 733885Sbinkertn@umich.edu */ 7413714Sandreas.sandberg@arm.comclass ExecContext : public ::ExecContext 7513714Sandreas.sandberg@arm.com{ 7613714Sandreas.sandberg@arm.com public: 773101Sstever@eecs.umich.edu MinorCPU &cpu; 784762Snate@binkert.org 7913716Sandreas.sandberg@arm.com /** ThreadState object, provides all the architectural state. */ 804762Snate@binkert.org SimpleThread &thread; 814762Snate@binkert.org 824762Snate@binkert.org /** The execute stage so we can peek at its contents. */ 8313716Sandreas.sandberg@arm.com Execute &execute; 844762Snate@binkert.org 854762Snate@binkert.org /** Instruction for the benefit of memory operations and for PC */ 864762Snate@binkert.org MinorDynInstPtr inst; 8713716Sandreas.sandberg@arm.com 884762Snate@binkert.org ExecContext ( 894762Snate@binkert.org MinorCPU &cpu_, 905033Smilesck@eecs.umich.edu SimpleThread &thread_, Execute &execute_, 915033Smilesck@eecs.umich.edu MinorDynInstPtr inst_) : 925033Smilesck@eecs.umich.edu cpu(cpu_), 935033Smilesck@eecs.umich.edu thread(thread_), 945033Smilesck@eecs.umich.edu execute(execute_), 955033Smilesck@eecs.umich.edu inst(inst_) 965033Smilesck@eecs.umich.edu { 975033Smilesck@eecs.umich.edu DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc); 985033Smilesck@eecs.umich.edu pcState(inst->pc); 995033Smilesck@eecs.umich.edu setPredicate(true); 1003101Sstever@eecs.umich.edu thread.setIntReg(TheISA::ZeroReg, 0); 1013101Sstever@eecs.umich.edu#if THE_ISA == ALPHA_ISA 1023101Sstever@eecs.umich.edu thread.setFloatReg(TheISA::ZeroReg, 0); 1035033Smilesck@eecs.umich.edu#endif 10410267SGeoffrey.Blake@arm.com } 1058596Ssteve.reinhardt@amd.com 1068596Ssteve.reinhardt@amd.com Fault 1078596Ssteve.reinhardt@amd.com initiateMemRead(Addr addr, unsigned int size, 1088596Ssteve.reinhardt@amd.com Request::Flags flags) override 1097673Snate@binkert.org { 1107673Snate@binkert.org execute.getLSQ().pushRequest(inst, true /* load */, nullptr, 1117673Snate@binkert.org size, addr, flags, NULL); 1127673Snate@binkert.org return NoFault; 11311988Sandreas.sandberg@arm.com } 11411988Sandreas.sandberg@arm.com 11511988Sandreas.sandberg@arm.com Fault 11611988Sandreas.sandberg@arm.com writeMem(uint8_t *data, unsigned int size, Addr addr, 1173101Sstever@eecs.umich.edu Request::Flags flags, uint64_t *res) override 1183101Sstever@eecs.umich.edu { 1193101Sstever@eecs.umich.edu execute.getLSQ().pushRequest(inst, false /* store */, data, 1203101Sstever@eecs.umich.edu size, addr, flags, res); 1213101Sstever@eecs.umich.edu return NoFault; 12210380SAndrew.Bardsley@arm.com } 12310380SAndrew.Bardsley@arm.com 12410380SAndrew.Bardsley@arm.com RegVal 12510380SAndrew.Bardsley@arm.com readIntRegOperand(const StaticInst *si, int idx) override 12610380SAndrew.Bardsley@arm.com { 12710380SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 12810458Sandreas.hansson@arm.com assert(reg.isIntReg()); 12910458Sandreas.hansson@arm.com return thread.readIntReg(reg.index()); 13010458Sandreas.hansson@arm.com } 13110458Sandreas.hansson@arm.com 13210458Sandreas.hansson@arm.com RegVal 13310458Sandreas.hansson@arm.com readFloatRegOperandBits(const StaticInst *si, int idx) override 13410458Sandreas.hansson@arm.com { 13510458Sandreas.hansson@arm.com const RegId& reg = si->srcRegIdx(idx); 13610458Sandreas.hansson@arm.com assert(reg.isFloatReg()); 13710458Sandreas.hansson@arm.com return thread.readFloatReg(reg.index()); 13810458Sandreas.hansson@arm.com } 13910458Sandreas.hansson@arm.com 1403101Sstever@eecs.umich.edu const TheISA::VecRegContainer & 1413101Sstever@eecs.umich.edu readVecRegOperand(const StaticInst *si, int idx) const override 1423101Sstever@eecs.umich.edu { 1433101Sstever@eecs.umich.edu const RegId& reg = si->srcRegIdx(idx); 1443101Sstever@eecs.umich.edu assert(reg.isVecReg()); 14510267SGeoffrey.Blake@arm.com return thread.readVecReg(reg); 14610267SGeoffrey.Blake@arm.com } 14710267SGeoffrey.Blake@arm.com 14810267SGeoffrey.Blake@arm.com TheISA::VecRegContainer & 1493101Sstever@eecs.umich.edu getWritableVecRegOperand(const StaticInst *si, int idx) override 1503101Sstever@eecs.umich.edu { 1513101Sstever@eecs.umich.edu const RegId& reg = si->destRegIdx(idx); 1523101Sstever@eecs.umich.edu assert(reg.isVecReg()); 1533101Sstever@eecs.umich.edu return thread.getWritableVecReg(reg); 1543101Sstever@eecs.umich.edu } 1553101Sstever@eecs.umich.edu 1563101Sstever@eecs.umich.edu TheISA::VecElem 1573101Sstever@eecs.umich.edu readVecElemOperand(const StaticInst *si, int idx) const override 1583101Sstever@eecs.umich.edu { 1593101Sstever@eecs.umich.edu const RegId& reg = si->srcRegIdx(idx); 1603101Sstever@eecs.umich.edu assert(reg.isVecElem()); 1613101Sstever@eecs.umich.edu return thread.readVecElem(reg); 1623101Sstever@eecs.umich.edu } 1633101Sstever@eecs.umich.edu 16413663Sandreas.sandberg@arm.com const TheISA::VecPredRegContainer& 1653101Sstever@eecs.umich.edu readVecPredRegOperand(const StaticInst *si, int idx) const override 16613675Sandreas.sandberg@arm.com { 1673101Sstever@eecs.umich.edu const RegId& reg = si->srcRegIdx(idx); 1683101Sstever@eecs.umich.edu assert(reg.isVecPredReg()); 1693101Sstever@eecs.umich.edu return thread.readVecPredReg(reg); 1703101Sstever@eecs.umich.edu } 17113675Sandreas.sandberg@arm.com 1723101Sstever@eecs.umich.edu TheISA::VecPredRegContainer& 1733101Sstever@eecs.umich.edu getWritableVecPredRegOperand(const StaticInst *si, int idx) override 1743101Sstever@eecs.umich.edu { 1753101Sstever@eecs.umich.edu const RegId& reg = si->destRegIdx(idx); 1763101Sstever@eecs.umich.edu assert(reg.isVecPredReg()); 17713663Sandreas.sandberg@arm.com return thread.getWritableVecPredReg(reg); 1783101Sstever@eecs.umich.edu } 1793101Sstever@eecs.umich.edu 18013663Sandreas.sandberg@arm.com void 1813101Sstever@eecs.umich.edu setIntRegOperand(const StaticInst *si, int idx, RegVal val) override 1823101Sstever@eecs.umich.edu { 1833101Sstever@eecs.umich.edu const RegId& reg = si->destRegIdx(idx); 18413716Sandreas.sandberg@arm.com assert(reg.isIntReg()); 1855033Smilesck@eecs.umich.edu thread.setIntReg(reg.index(), val); 1866656Snate@binkert.org } 1875033Smilesck@eecs.umich.edu 1885033Smilesck@eecs.umich.edu void 1895033Smilesck@eecs.umich.edu setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override 19013663Sandreas.sandberg@arm.com { 19113663Sandreas.sandberg@arm.com const RegId& reg = si->destRegIdx(idx); 1923101Sstever@eecs.umich.edu assert(reg.isFloatReg()); 19310267SGeoffrey.Blake@arm.com thread.setFloatReg(reg.index(), val); 19410267SGeoffrey.Blake@arm.com } 19510267SGeoffrey.Blake@arm.com 19610267SGeoffrey.Blake@arm.com void 19710267SGeoffrey.Blake@arm.com setVecRegOperand(const StaticInst *si, int idx, 19810267SGeoffrey.Blake@arm.com const TheISA::VecRegContainer& val) override 19910267SGeoffrey.Blake@arm.com { 20010267SGeoffrey.Blake@arm.com const RegId& reg = si->destRegIdx(idx); 20110267SGeoffrey.Blake@arm.com assert(reg.isVecReg()); 20210267SGeoffrey.Blake@arm.com thread.setVecReg(reg, val); 20310267SGeoffrey.Blake@arm.com } 20410267SGeoffrey.Blake@arm.com 20510267SGeoffrey.Blake@arm.com void 2063101Sstever@eecs.umich.edu setVecPredRegOperand(const StaticInst *si, int idx, 2073101Sstever@eecs.umich.edu const TheISA::VecPredRegContainer& val) override 2083101Sstever@eecs.umich.edu { 2093101Sstever@eecs.umich.edu const RegId& reg = si->destRegIdx(idx); 21013699Sandreas.sandberg@arm.com assert(reg.isVecPredReg()); 2113101Sstever@eecs.umich.edu thread.setVecPredReg(reg, val); 2123101Sstever@eecs.umich.edu } 2133101Sstever@eecs.umich.edu 2143101Sstever@eecs.umich.edu /** Vector Register Lane Interfaces. */ 2153101Sstever@eecs.umich.edu /** @{ */ 2163102Sstever@eecs.umich.edu /** Reads source vector 8bit operand. */ 2173101Sstever@eecs.umich.edu ConstVecLane8 2183101Sstever@eecs.umich.edu readVec8BitLaneOperand(const StaticInst *si, int idx) const 2193101Sstever@eecs.umich.edu override 22010267SGeoffrey.Blake@arm.com { 22110267SGeoffrey.Blake@arm.com const RegId& reg = si->srcRegIdx(idx); 22210267SGeoffrey.Blake@arm.com assert(reg.isVecReg()); 22310267SGeoffrey.Blake@arm.com return thread.readVec8BitLaneReg(reg); 22410267SGeoffrey.Blake@arm.com } 22510267SGeoffrey.Blake@arm.com 22610267SGeoffrey.Blake@arm.com /** Reads source vector 16bit operand. */ 2277673Snate@binkert.org ConstVecLane16 2288607Sgblack@eecs.umich.edu readVec16BitLaneOperand(const StaticInst *si, int idx) const 2297673Snate@binkert.org override 2303101Sstever@eecs.umich.edu { 23111988Sandreas.sandberg@arm.com const RegId& reg = si->srcRegIdx(idx); 23211988Sandreas.sandberg@arm.com assert(reg.isVecReg()); 23311988Sandreas.sandberg@arm.com return thread.readVec16BitLaneReg(reg); 2347673Snate@binkert.org } 2357673Snate@binkert.org 2363101Sstever@eecs.umich.edu /** Reads source vector 32bit operand. */ 2373101Sstever@eecs.umich.edu ConstVecLane32 2383101Sstever@eecs.umich.edu readVec32BitLaneOperand(const StaticInst *si, int idx) const 2393101Sstever@eecs.umich.edu override 2403101Sstever@eecs.umich.edu { 2413101Sstever@eecs.umich.edu const RegId& reg = si->srcRegIdx(idx); 2425033Smilesck@eecs.umich.edu assert(reg.isVecReg()); 2435475Snate@binkert.org return thread.readVec32BitLaneReg(reg); 24413663Sandreas.sandberg@arm.com } 24513663Sandreas.sandberg@arm.com 2465475Snate@binkert.org /** Reads source vector 64bit operand. */ 24710380SAndrew.Bardsley@arm.com ConstVecLane64 24810380SAndrew.Bardsley@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 24910380SAndrew.Bardsley@arm.com override 2503101Sstever@eecs.umich.edu { 2513101Sstever@eecs.umich.edu const RegId& reg = si->srcRegIdx(idx); 2523101Sstever@eecs.umich.edu assert(reg.isVecReg()); 2534762Snate@binkert.org return thread.readVec64BitLaneReg(reg); 2544762Snate@binkert.org } 2554762Snate@binkert.org 2563101Sstever@eecs.umich.edu /** Write a lane of the destination vector operand. */ 25712050Snikos.nikoleris@arm.com template <typename LD> 25812050Snikos.nikoleris@arm.com void 25912050Snikos.nikoleris@arm.com setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) 2608459SAli.Saidi@ARM.com { 2618459SAli.Saidi@ARM.com const RegId& reg = si->destRegIdx(idx); 26212050Snikos.nikoleris@arm.com assert(reg.isVecReg()); 2633101Sstever@eecs.umich.edu return thread.setVecLane(reg, val); 2647528Ssteve.reinhardt@amd.com } 2657528Ssteve.reinhardt@amd.com virtual void 2667528Ssteve.reinhardt@amd.com setVecLaneOperand(const StaticInst *si, int idx, 2677528Ssteve.reinhardt@amd.com const LaneData<LaneSize::Byte>& val) override 2687528Ssteve.reinhardt@amd.com { 2697528Ssteve.reinhardt@amd.com setVecLaneOperandT(si, idx, val); 2703101Sstever@eecs.umich.edu } 2717528Ssteve.reinhardt@amd.com virtual void 2727528Ssteve.reinhardt@amd.com setVecLaneOperand(const StaticInst *si, int idx, 2737528Ssteve.reinhardt@amd.com const LaneData<LaneSize::TwoByte>& val) override 2747528Ssteve.reinhardt@amd.com { 2757528Ssteve.reinhardt@amd.com setVecLaneOperandT(si, idx, val); 2767528Ssteve.reinhardt@amd.com } 2777528Ssteve.reinhardt@amd.com virtual void 2787528Ssteve.reinhardt@amd.com setVecLaneOperand(const StaticInst *si, int idx, 2797528Ssteve.reinhardt@amd.com const LaneData<LaneSize::FourByte>& val) override 2807528Ssteve.reinhardt@amd.com { 2818321Ssteve.reinhardt@amd.com setVecLaneOperandT(si, idx, val); 28212194Sgabeblack@google.com } 2837528Ssteve.reinhardt@amd.com virtual void 2847528Ssteve.reinhardt@amd.com setVecLaneOperand(const StaticInst *si, int idx, 2857528Ssteve.reinhardt@amd.com const LaneData<LaneSize::EightByte>& val) override 2867528Ssteve.reinhardt@amd.com { 2877528Ssteve.reinhardt@amd.com setVecLaneOperandT(si, idx, val); 2887528Ssteve.reinhardt@amd.com } 2897528Ssteve.reinhardt@amd.com /** @} */ 2907528Ssteve.reinhardt@amd.com 2917528Ssteve.reinhardt@amd.com void 2927528Ssteve.reinhardt@amd.com setVecElemOperand(const StaticInst *si, int idx, 2937528Ssteve.reinhardt@amd.com const TheISA::VecElem val) override 2947528Ssteve.reinhardt@amd.com { 2957528Ssteve.reinhardt@amd.com const RegId& reg = si->destRegIdx(idx); 2963101Sstever@eecs.umich.edu assert(reg.isVecElem()); 2978664SAli.Saidi@ARM.com thread.setVecElem(reg, val); 2988664SAli.Saidi@ARM.com } 2998664SAli.Saidi@ARM.com 3008664SAli.Saidi@ARM.com bool 3018664SAli.Saidi@ARM.com readPredicate() const override 3028664SAli.Saidi@ARM.com { 3039953Sgeoffrey.blake@arm.com return thread.readPredicate(); 3049953Sgeoffrey.blake@arm.com } 3059953Sgeoffrey.blake@arm.com 3069953Sgeoffrey.blake@arm.com void 3079953Sgeoffrey.blake@arm.com setPredicate(bool val) override 3089953Sgeoffrey.blake@arm.com { 3099953Sgeoffrey.blake@arm.com thread.setPredicate(val); 3109953Sgeoffrey.blake@arm.com } 3119953Sgeoffrey.blake@arm.com 3129953Sgeoffrey.blake@arm.com TheISA::PCState 3139953Sgeoffrey.blake@arm.com pcState() const override 3149953Sgeoffrey.blake@arm.com { 3159953Sgeoffrey.blake@arm.com return thread.pcState(); 31610267SGeoffrey.Blake@arm.com } 31710267SGeoffrey.Blake@arm.com 31810267SGeoffrey.Blake@arm.com void 31910267SGeoffrey.Blake@arm.com pcState(const TheISA::PCState &val) override 32010267SGeoffrey.Blake@arm.com { 32110267SGeoffrey.Blake@arm.com thread.pcState(val); 32210267SGeoffrey.Blake@arm.com } 32312563Sgabeblack@google.com 32410267SGeoffrey.Blake@arm.com RegVal 32510267SGeoffrey.Blake@arm.com readMiscRegNoEffect(int misc_reg) const 32610267SGeoffrey.Blake@arm.com { 32710267SGeoffrey.Blake@arm.com return thread.readMiscRegNoEffect(misc_reg); 32810267SGeoffrey.Blake@arm.com } 32910267SGeoffrey.Blake@arm.com 33010267SGeoffrey.Blake@arm.com RegVal 33110267SGeoffrey.Blake@arm.com readMiscReg(int misc_reg) override 33210267SGeoffrey.Blake@arm.com { 33310267SGeoffrey.Blake@arm.com return thread.readMiscReg(misc_reg); 33410267SGeoffrey.Blake@arm.com } 33510267SGeoffrey.Blake@arm.com 3363101Sstever@eecs.umich.edu void 3373101Sstever@eecs.umich.edu setMiscReg(int misc_reg, RegVal val) override 3383101Sstever@eecs.umich.edu { 3393101Sstever@eecs.umich.edu thread.setMiscReg(misc_reg, val); 3403101Sstever@eecs.umich.edu } 3413101Sstever@eecs.umich.edu 3423101Sstever@eecs.umich.edu RegVal 34310364SGeoffrey.Blake@arm.com readMiscRegOperand(const StaticInst *si, int idx) override 34410364SGeoffrey.Blake@arm.com { 34510364SGeoffrey.Blake@arm.com const RegId& reg = si->srcRegIdx(idx); 34610364SGeoffrey.Blake@arm.com assert(reg.isMiscReg()); 3473101Sstever@eecs.umich.edu return thread.readMiscReg(reg.index()); 3484762Snate@binkert.org } 3494762Snate@binkert.org 3504762Snate@binkert.org void 3514762Snate@binkert.org setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override 3527528Ssteve.reinhardt@amd.com { 3534762Snate@binkert.org const RegId& reg = si->destRegIdx(idx); 3544762Snate@binkert.org assert(reg.isMiscReg()); 3554762Snate@binkert.org return thread.setMiscReg(reg.index(), val); 35610267SGeoffrey.Blake@arm.com } 35710267SGeoffrey.Blake@arm.com 35810267SGeoffrey.Blake@arm.com Fault 35910267SGeoffrey.Blake@arm.com hwrei() override 36010267SGeoffrey.Blake@arm.com { 36110267SGeoffrey.Blake@arm.com#if THE_ISA == ALPHA_ISA 36210267SGeoffrey.Blake@arm.com return thread.hwrei(); 36310267SGeoffrey.Blake@arm.com#else 36410267SGeoffrey.Blake@arm.com return NoFault; 36510267SGeoffrey.Blake@arm.com#endif 36610267SGeoffrey.Blake@arm.com } 36710267SGeoffrey.Blake@arm.com 36810267SGeoffrey.Blake@arm.com bool 36910267SGeoffrey.Blake@arm.com simPalCheck(int palFunc) override 37010267SGeoffrey.Blake@arm.com { 37110267SGeoffrey.Blake@arm.com#if THE_ISA == ALPHA_ISA 37210267SGeoffrey.Blake@arm.com return thread.simPalCheck(palFunc); 37310267SGeoffrey.Blake@arm.com#else 37410267SGeoffrey.Blake@arm.com return false; 37510267SGeoffrey.Blake@arm.com#endif 37610267SGeoffrey.Blake@arm.com } 37710267SGeoffrey.Blake@arm.com 37810267SGeoffrey.Blake@arm.com void 37910267SGeoffrey.Blake@arm.com syscall(int64_t callnum, Fault *fault) override 38010267SGeoffrey.Blake@arm.com { 38110267SGeoffrey.Blake@arm.com if (FullSystem) 38210364SGeoffrey.Blake@arm.com panic("Syscall emulation isn't available in FS mode.\n"); 38310364SGeoffrey.Blake@arm.com 38410267SGeoffrey.Blake@arm.com thread.syscall(callnum, fault); 38510267SGeoffrey.Blake@arm.com } 38610267SGeoffrey.Blake@arm.com 38710267SGeoffrey.Blake@arm.com ThreadContext *tcBase() override { return thread.getTC(); } 38810267SGeoffrey.Blake@arm.com 38910267SGeoffrey.Blake@arm.com /* @todo, should make stCondFailures persistent somewhere */ 3907673Snate@binkert.org unsigned int readStCondFailures() const override { return 0; } 3917673Snate@binkert.org void setStCondFailures(unsigned int st_cond_failures) override {} 3927673Snate@binkert.org 3933101Sstever@eecs.umich.edu ContextID contextId() { return thread.contextId(); } 39411988Sandreas.sandberg@arm.com /* ISA-specific (or at least currently ISA singleton) functions */ 39511988Sandreas.sandberg@arm.com 39611988Sandreas.sandberg@arm.com /* X86: TLB twiddling */ 39711988Sandreas.sandberg@arm.com void 3987673Snate@binkert.org demapPage(Addr vaddr, uint64_t asn) override 3997673Snate@binkert.org { 4003101Sstever@eecs.umich.edu thread.getITBPtr()->demapPage(vaddr, asn); 4013101Sstever@eecs.umich.edu thread.getDTBPtr()->demapPage(vaddr, asn); 4023101Sstever@eecs.umich.edu } 4033101Sstever@eecs.umich.edu 4043101Sstever@eecs.umich.edu RegVal 4053101Sstever@eecs.umich.edu readCCRegOperand(const StaticInst *si, int idx) override 4063101Sstever@eecs.umich.edu { 4073101Sstever@eecs.umich.edu const RegId& reg = si->srcRegIdx(idx); 4083101Sstever@eecs.umich.edu assert(reg.isCCReg()); 4093101Sstever@eecs.umich.edu return thread.readCCReg(reg.index()); 4103101Sstever@eecs.umich.edu } 4113101Sstever@eecs.umich.edu 4123101Sstever@eecs.umich.edu void 4133101Sstever@eecs.umich.edu setCCRegOperand(const StaticInst *si, int idx, RegVal val) override 4143101Sstever@eecs.umich.edu { 4155033Smilesck@eecs.umich.edu const RegId& reg = si->destRegIdx(idx); 4165033Smilesck@eecs.umich.edu assert(reg.isCCReg()); 4173101Sstever@eecs.umich.edu thread.setCCReg(reg.index(), val); 4183101Sstever@eecs.umich.edu } 4193101Sstever@eecs.umich.edu 4203101Sstever@eecs.umich.edu void 4213101Sstever@eecs.umich.edu demapInstPage(Addr vaddr, uint64_t asn) 4223101Sstever@eecs.umich.edu { 4233101Sstever@eecs.umich.edu thread.getITBPtr()->demapPage(vaddr, asn); 4243101Sstever@eecs.umich.edu } 4253101Sstever@eecs.umich.edu 4263101Sstever@eecs.umich.edu void 4273101Sstever@eecs.umich.edu demapDataPage(Addr vaddr, uint64_t asn) 4283101Sstever@eecs.umich.edu { 4293101Sstever@eecs.umich.edu thread.getDTBPtr()->demapPage(vaddr, asn); 4303101Sstever@eecs.umich.edu } 4313101Sstever@eecs.umich.edu 4323101Sstever@eecs.umich.edu BaseCPU *getCpuPtr() { return &cpu; } 4333101Sstever@eecs.umich.edu 4343101Sstever@eecs.umich.edu /* MIPS: other thread register reading/writing */ 4353101Sstever@eecs.umich.edu RegVal 4363101Sstever@eecs.umich.edu readRegOtherThread(const RegId ®, ThreadID tid=InvalidThreadID) 4373101Sstever@eecs.umich.edu { 4383101Sstever@eecs.umich.edu SimpleThread *other_thread = (tid == InvalidThreadID 4393101Sstever@eecs.umich.edu ? &thread : cpu.threads[tid]); 4403101Sstever@eecs.umich.edu 4413101Sstever@eecs.umich.edu switch (reg.classValue()) { 44210267SGeoffrey.Blake@arm.com case IntRegClass: 4437673Snate@binkert.org return other_thread->readIntReg(reg.index()); 4447673Snate@binkert.org break; 4457673Snate@binkert.org case FloatRegClass: 4467673Snate@binkert.org return other_thread->readFloatReg(reg.index()); 4477673Snate@binkert.org break; 44810267SGeoffrey.Blake@arm.com case MiscRegClass: 44910267SGeoffrey.Blake@arm.com return other_thread->readMiscReg(reg.index()); 45010267SGeoffrey.Blake@arm.com default: 45110267SGeoffrey.Blake@arm.com panic("Unexpected reg class! (%s)", 45210458Sandreas.hansson@arm.com reg.className()); 45310458Sandreas.hansson@arm.com return 0; 45410458Sandreas.hansson@arm.com } 45510458Sandreas.hansson@arm.com } 45610458Sandreas.hansson@arm.com 4574762Snate@binkert.org void 4584762Snate@binkert.org setRegOtherThread(const RegId ®, RegVal val, 4593101Sstever@eecs.umich.edu ThreadID tid=InvalidThreadID) 4603101Sstever@eecs.umich.edu { 4613101Sstever@eecs.umich.edu SimpleThread *other_thread = (tid == InvalidThreadID 4623101Sstever@eecs.umich.edu ? &thread : cpu.threads[tid]); 4633101Sstever@eecs.umich.edu 46413708Sandreas.sandberg@arm.com switch (reg.classValue()) { 46513708Sandreas.sandberg@arm.com case IntRegClass: 46613708Sandreas.sandberg@arm.com return other_thread->setIntReg(reg.index(), val); 46713708Sandreas.sandberg@arm.com break; 4683101Sstever@eecs.umich.edu case FloatRegClass: 4693101Sstever@eecs.umich.edu return other_thread->setFloatReg(reg.index(), val); 4703101Sstever@eecs.umich.edu break; 4713101Sstever@eecs.umich.edu case MiscRegClass: 4723101Sstever@eecs.umich.edu return other_thread->setMiscReg(reg.index(), val); 4733101Sstever@eecs.umich.edu default: 4743714Sstever@eecs.umich.edu panic("Unexpected reg class! (%s)", 4753714Sstever@eecs.umich.edu reg.className()); 4763714Sstever@eecs.umich.edu } 4773714Sstever@eecs.umich.edu } 4783714Sstever@eecs.umich.edu 4793714Sstever@eecs.umich.edu public: 4803101Sstever@eecs.umich.edu // monitor/mwait funtions 4813101Sstever@eecs.umich.edu void armMonitor(Addr address) override 4823101Sstever@eecs.umich.edu { getCpuPtr()->armMonitor(inst->id.threadId, address); } 4833101Sstever@eecs.umich.edu 4843101Sstever@eecs.umich.edu bool mwait(PacketPtr pkt) override 4853101Sstever@eecs.umich.edu { return getCpuPtr()->mwait(inst->id.threadId, pkt); } 48613708Sandreas.sandberg@arm.com 4873101Sstever@eecs.umich.edu void mwaitAtomic(ThreadContext *tc) override 4883101Sstever@eecs.umich.edu { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); } 4893101Sstever@eecs.umich.edu 4903101Sstever@eecs.umich.edu AddressMonitor *getAddrMonitor() override 4913101Sstever@eecs.umich.edu { return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId); } 49213708Sandreas.sandberg@arm.com}; 4933101Sstever@eecs.umich.edu 49413708Sandreas.sandberg@arm.com} 49513708Sandreas.sandberg@arm.com 49613708Sandreas.sandberg@arm.com#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */ 49713708Sandreas.sandberg@arm.com