exec_context.hh revision 13429:a1e199fd8122
113172Sgiacomo.travaglini@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2011-2014, 2016 ARM Limited 310259SAndrew.Bardsley@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 410259SAndrew.Bardsley@arm.com * All rights reserved 510259SAndrew.Bardsley@arm.com * 610259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 710259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 810259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 910259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 1010259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1110259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1210259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1310259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1410259SAndrew.Bardsley@arm.com * 1510259SAndrew.Bardsley@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1610259SAndrew.Bardsley@arm.com * All rights reserved. 1710259SAndrew.Bardsley@arm.com * 1810259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1910259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 2010259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 2110259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 2210259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 2310259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2410259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2510259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2610259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2710259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2810259SAndrew.Bardsley@arm.com * 2910259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4010259SAndrew.Bardsley@arm.com * 4110259SAndrew.Bardsley@arm.com * Authors: Steve Reinhardt 4210259SAndrew.Bardsley@arm.com * Dave Greene 4312563Sgabeblack@google.com * Nathan Binkert 4412563Sgabeblack@google.com * Andrew Bardsley 4510259SAndrew.Bardsley@arm.com */ 4610259SAndrew.Bardsley@arm.com 4710259SAndrew.Bardsley@arm.com/** 4810259SAndrew.Bardsley@arm.com * @file 4913665Sandreas.sandberg@arm.com * 5013665Sandreas.sandberg@arm.com * ExecContext bears the exec_context interface for Minor. 5113665Sandreas.sandberg@arm.com */ 5213665Sandreas.sandberg@arm.com 5310259SAndrew.Bardsley@arm.com#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__ 5413665Sandreas.sandberg@arm.com#define __CPU_MINOR_EXEC_CONTEXT_HH__ 5510259SAndrew.Bardsley@arm.com 5610259SAndrew.Bardsley@arm.com#include "cpu/exec_context.hh" 5710259SAndrew.Bardsley@arm.com#include "cpu/minor/execute.hh" 5810259SAndrew.Bardsley@arm.com#include "cpu/minor/pipeline.hh" 5910259SAndrew.Bardsley@arm.com#include "cpu/base.hh" 6010259SAndrew.Bardsley@arm.com#include "cpu/simple_thread.hh" 6110259SAndrew.Bardsley@arm.com#include "mem/request.hh" 6210259SAndrew.Bardsley@arm.com#include "debug/MinorExecute.hh" 6310259SAndrew.Bardsley@arm.com 6410259SAndrew.Bardsley@arm.comnamespace Minor 6510259SAndrew.Bardsley@arm.com{ 6610259SAndrew.Bardsley@arm.com 6710259SAndrew.Bardsley@arm.com/* Forward declaration of Execute */ 6810259SAndrew.Bardsley@arm.comclass Execute; 6910259SAndrew.Bardsley@arm.com 7010259SAndrew.Bardsley@arm.com/** ExecContext bears the exec_context interface for Minor. This nicely 7110259SAndrew.Bardsley@arm.com * separates that interface from other classes such as Pipeline, MinorCPU 7210259SAndrew.Bardsley@arm.com * and DynMinorInst and makes it easier to see what state is accessed by it. 7310259SAndrew.Bardsley@arm.com */ 7410259SAndrew.Bardsley@arm.comclass ExecContext : public ::ExecContext 7510259SAndrew.Bardsley@arm.com{ 7610259SAndrew.Bardsley@arm.com public: 7710259SAndrew.Bardsley@arm.com MinorCPU &cpu; 7810259SAndrew.Bardsley@arm.com 7910259SAndrew.Bardsley@arm.com /** ThreadState object, provides all the architectural state. */ 8010259SAndrew.Bardsley@arm.com SimpleThread &thread; 8110259SAndrew.Bardsley@arm.com 8210259SAndrew.Bardsley@arm.com /** The execute stage so we can peek at its contents. */ 8310259SAndrew.Bardsley@arm.com Execute &execute; 8410259SAndrew.Bardsley@arm.com 8510259SAndrew.Bardsley@arm.com /** Instruction for the benefit of memory operations and for PC */ 8610259SAndrew.Bardsley@arm.com MinorDynInstPtr inst; 8710259SAndrew.Bardsley@arm.com 8810259SAndrew.Bardsley@arm.com ExecContext ( 8910259SAndrew.Bardsley@arm.com MinorCPU &cpu_, 9010259SAndrew.Bardsley@arm.com SimpleThread &thread_, Execute &execute_, 9110259SAndrew.Bardsley@arm.com MinorDynInstPtr inst_) : 9210259SAndrew.Bardsley@arm.com cpu(cpu_), 9310259SAndrew.Bardsley@arm.com thread(thread_), 9410259SAndrew.Bardsley@arm.com execute(execute_), 9510259SAndrew.Bardsley@arm.com inst(inst_) 9610259SAndrew.Bardsley@arm.com { 9710259SAndrew.Bardsley@arm.com DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc); 9810259SAndrew.Bardsley@arm.com pcState(inst->pc); 9910259SAndrew.Bardsley@arm.com setPredicate(true); 10010259SAndrew.Bardsley@arm.com thread.setIntReg(TheISA::ZeroReg, 0); 10110259SAndrew.Bardsley@arm.com#if THE_ISA == ALPHA_ISA 10210259SAndrew.Bardsley@arm.com thread.setFloatReg(TheISA::ZeroReg, 0.0); 10310259SAndrew.Bardsley@arm.com#endif 10410259SAndrew.Bardsley@arm.com } 10510259SAndrew.Bardsley@arm.com 10610259SAndrew.Bardsley@arm.com Fault 10710259SAndrew.Bardsley@arm.com initiateMemRead(Addr addr, unsigned int size, 10810259SAndrew.Bardsley@arm.com Request::Flags flags) override 10910259SAndrew.Bardsley@arm.com { 11010259SAndrew.Bardsley@arm.com execute.getLSQ().pushRequest(inst, true /* load */, nullptr, 11110259SAndrew.Bardsley@arm.com size, addr, flags, NULL); 11210259SAndrew.Bardsley@arm.com return NoFault; 11310259SAndrew.Bardsley@arm.com } 11410259SAndrew.Bardsley@arm.com 11510259SAndrew.Bardsley@arm.com Fault 11610259SAndrew.Bardsley@arm.com writeMem(uint8_t *data, unsigned int size, Addr addr, 11710259SAndrew.Bardsley@arm.com Request::Flags flags, uint64_t *res) override 11810259SAndrew.Bardsley@arm.com { 11910259SAndrew.Bardsley@arm.com execute.getLSQ().pushRequest(inst, false /* store */, data, 12010259SAndrew.Bardsley@arm.com size, addr, flags, res); 12110259SAndrew.Bardsley@arm.com return NoFault; 12210259SAndrew.Bardsley@arm.com } 12310259SAndrew.Bardsley@arm.com 12410259SAndrew.Bardsley@arm.com IntReg 12510259SAndrew.Bardsley@arm.com readIntRegOperand(const StaticInst *si, int idx) override 12610259SAndrew.Bardsley@arm.com { 12710259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 12810259SAndrew.Bardsley@arm.com assert(reg.isIntReg()); 12910259SAndrew.Bardsley@arm.com return thread.readIntReg(reg.index()); 13010259SAndrew.Bardsley@arm.com } 13110259SAndrew.Bardsley@arm.com 13210259SAndrew.Bardsley@arm.com TheISA::FloatReg 13310259SAndrew.Bardsley@arm.com readFloatRegOperand(const StaticInst *si, int idx) override 13410259SAndrew.Bardsley@arm.com { 13510259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 13610259SAndrew.Bardsley@arm.com assert(reg.isFloatReg()); 13710259SAndrew.Bardsley@arm.com return thread.readFloatReg(reg.index()); 13810259SAndrew.Bardsley@arm.com } 13910259SAndrew.Bardsley@arm.com 14010259SAndrew.Bardsley@arm.com TheISA::FloatRegBits 14110259SAndrew.Bardsley@arm.com readFloatRegOperandBits(const StaticInst *si, int idx) override 14210259SAndrew.Bardsley@arm.com { 14310259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 14410259SAndrew.Bardsley@arm.com assert(reg.isFloatReg()); 14510259SAndrew.Bardsley@arm.com return thread.readFloatRegBits(reg.index()); 14610259SAndrew.Bardsley@arm.com } 14711683Sfernando.endo2@gmail.com 14811683Sfernando.endo2@gmail.com const TheISA::VecRegContainer& 14910259SAndrew.Bardsley@arm.com readVecRegOperand(const StaticInst *si, int idx) const override 15010259SAndrew.Bardsley@arm.com { 15110259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 15210259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 15313172Sgiacomo.travaglini@arm.com return thread.readVecReg(reg); 15413172Sgiacomo.travaglini@arm.com } 15513172Sgiacomo.travaglini@arm.com 15610259SAndrew.Bardsley@arm.com TheISA::VecRegContainer& 15710259SAndrew.Bardsley@arm.com getWritableVecRegOperand(const StaticInst *si, int idx) override 15810259SAndrew.Bardsley@arm.com { 15910259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 16010259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 16111683Sfernando.endo2@gmail.com return thread.getWritableVecReg(reg); 16211683Sfernando.endo2@gmail.com } 16310259SAndrew.Bardsley@arm.com 16410259SAndrew.Bardsley@arm.com TheISA::VecElem 16510259SAndrew.Bardsley@arm.com readVecElemOperand(const StaticInst *si, int idx) const override 16610259SAndrew.Bardsley@arm.com { 16710259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 16810259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 16910259SAndrew.Bardsley@arm.com return thread.readVecElem(reg); 17010259SAndrew.Bardsley@arm.com } 17110259SAndrew.Bardsley@arm.com 17210259SAndrew.Bardsley@arm.com void 17310259SAndrew.Bardsley@arm.com setIntRegOperand(const StaticInst *si, int idx, IntReg val) override 17410259SAndrew.Bardsley@arm.com { 17510259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 17610259SAndrew.Bardsley@arm.com assert(reg.isIntReg()); 17711567Smitch.hayenga@arm.com thread.setIntReg(reg.index(), val); 17811567Smitch.hayenga@arm.com } 17910259SAndrew.Bardsley@arm.com 18010259SAndrew.Bardsley@arm.com void 18110259SAndrew.Bardsley@arm.com setFloatRegOperand(const StaticInst *si, int idx, 18210259SAndrew.Bardsley@arm.com TheISA::FloatReg val) override 18310259SAndrew.Bardsley@arm.com { 18410259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 18510259SAndrew.Bardsley@arm.com assert(reg.isFloatReg()); 18610259SAndrew.Bardsley@arm.com thread.setFloatReg(reg.index(), val); 18710259SAndrew.Bardsley@arm.com } 18810259SAndrew.Bardsley@arm.com 18910259SAndrew.Bardsley@arm.com void 19010259SAndrew.Bardsley@arm.com setFloatRegOperandBits(const StaticInst *si, int idx, 19110259SAndrew.Bardsley@arm.com TheISA::FloatRegBits val) override 19210259SAndrew.Bardsley@arm.com { 19310259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 19410259SAndrew.Bardsley@arm.com assert(reg.isFloatReg()); 19511567Smitch.hayenga@arm.com thread.setFloatRegBits(reg.index(), val); 19611567Smitch.hayenga@arm.com } 19710259SAndrew.Bardsley@arm.com 19810259SAndrew.Bardsley@arm.com void 19910259SAndrew.Bardsley@arm.com setVecRegOperand(const StaticInst *si, int idx, 20010259SAndrew.Bardsley@arm.com const TheISA::VecRegContainer& val) override 20110259SAndrew.Bardsley@arm.com { 20210259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 20310259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 20410259SAndrew.Bardsley@arm.com thread.setVecReg(reg, val); 20510259SAndrew.Bardsley@arm.com } 20610259SAndrew.Bardsley@arm.com 20710259SAndrew.Bardsley@arm.com /** Vector Register Lane Interfaces. */ 20810259SAndrew.Bardsley@arm.com /** @{ */ 20910259SAndrew.Bardsley@arm.com /** Reads source vector 8bit operand. */ 21010259SAndrew.Bardsley@arm.com ConstVecLane8 21110259SAndrew.Bardsley@arm.com readVec8BitLaneOperand(const StaticInst *si, int idx) const 21210259SAndrew.Bardsley@arm.com override 21310259SAndrew.Bardsley@arm.com { 21410259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 21510259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 21610259SAndrew.Bardsley@arm.com return thread.readVec8BitLaneReg(reg); 21710259SAndrew.Bardsley@arm.com } 21810259SAndrew.Bardsley@arm.com 21910259SAndrew.Bardsley@arm.com /** Reads source vector 16bit operand. */ 22010259SAndrew.Bardsley@arm.com ConstVecLane16 22110259SAndrew.Bardsley@arm.com readVec16BitLaneOperand(const StaticInst *si, int idx) const 22210259SAndrew.Bardsley@arm.com override 22310259SAndrew.Bardsley@arm.com { 22410259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 22510259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 22610259SAndrew.Bardsley@arm.com return thread.readVec16BitLaneReg(reg); 22710259SAndrew.Bardsley@arm.com } 22810259SAndrew.Bardsley@arm.com 22910259SAndrew.Bardsley@arm.com /** Reads source vector 32bit operand. */ 23010259SAndrew.Bardsley@arm.com ConstVecLane32 23110259SAndrew.Bardsley@arm.com readVec32BitLaneOperand(const StaticInst *si, int idx) const 23210259SAndrew.Bardsley@arm.com override 23310259SAndrew.Bardsley@arm.com { 23410259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 23510259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 23610259SAndrew.Bardsley@arm.com return thread.readVec32BitLaneReg(reg); 23710259SAndrew.Bardsley@arm.com } 23810259SAndrew.Bardsley@arm.com 23910259SAndrew.Bardsley@arm.com /** Reads source vector 64bit operand. */ 24010259SAndrew.Bardsley@arm.com ConstVecLane64 24110259SAndrew.Bardsley@arm.com readVec64BitLaneOperand(const StaticInst *si, int idx) const 24210259SAndrew.Bardsley@arm.com override 24310259SAndrew.Bardsley@arm.com { 24410259SAndrew.Bardsley@arm.com const RegId& reg = si->srcRegIdx(idx); 24510259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 24610259SAndrew.Bardsley@arm.com return thread.readVec64BitLaneReg(reg); 24710259SAndrew.Bardsley@arm.com } 24810259SAndrew.Bardsley@arm.com 24910259SAndrew.Bardsley@arm.com /** Write a lane of the destination vector operand. */ 25010259SAndrew.Bardsley@arm.com template <typename LD> 25110259SAndrew.Bardsley@arm.com void 25210259SAndrew.Bardsley@arm.com setVecLaneOperandT(const StaticInst *si, int idx, 25310259SAndrew.Bardsley@arm.com const LD& val) 25410259SAndrew.Bardsley@arm.com { 25510259SAndrew.Bardsley@arm.com const RegId& reg = si->destRegIdx(idx); 25610259SAndrew.Bardsley@arm.com assert(reg.isVecReg()); 25710259SAndrew.Bardsley@arm.com return thread.setVecLane(reg, val); 25810259SAndrew.Bardsley@arm.com } 25910259SAndrew.Bardsley@arm.com virtual void 26010259SAndrew.Bardsley@arm.com setVecLaneOperand(const StaticInst *si, int idx, 26110259SAndrew.Bardsley@arm.com const LaneData<LaneSize::Byte>& val) override 26210259SAndrew.Bardsley@arm.com { 26310259SAndrew.Bardsley@arm.com setVecLaneOperandT(si, idx, val); 26410259SAndrew.Bardsley@arm.com } 26510259SAndrew.Bardsley@arm.com virtual void 26610259SAndrew.Bardsley@arm.com setVecLaneOperand(const StaticInst *si, int idx, 26710259SAndrew.Bardsley@arm.com const LaneData<LaneSize::TwoByte>& val) override 26810259SAndrew.Bardsley@arm.com { 26910259SAndrew.Bardsley@arm.com setVecLaneOperandT(si, idx, val); 27010259SAndrew.Bardsley@arm.com } 27110259SAndrew.Bardsley@arm.com virtual void 27210259SAndrew.Bardsley@arm.com setVecLaneOperand(const StaticInst *si, int idx, 27310259SAndrew.Bardsley@arm.com const LaneData<LaneSize::FourByte>& val) override 27410259SAndrew.Bardsley@arm.com { 27510259SAndrew.Bardsley@arm.com setVecLaneOperandT(si, idx, val); 27610259SAndrew.Bardsley@arm.com } 27710259SAndrew.Bardsley@arm.com virtual void 27810785Sgope@wisc.edu setVecLaneOperand(const StaticInst *si, int idx, 27910259SAndrew.Bardsley@arm.com const LaneData<LaneSize::EightByte>& val) override 28010259SAndrew.Bardsley@arm.com { 28110259SAndrew.Bardsley@arm.com setVecLaneOperandT(si, idx, val); 28212563Sgabeblack@google.com } 28310259SAndrew.Bardsley@arm.com /** @} */ 284 285 void 286 setVecElemOperand(const StaticInst *si, int idx, 287 const TheISA::VecElem val) override 288 { 289 const RegId& reg = si->destRegIdx(idx); 290 assert(reg.isVecReg()); 291 thread.setVecElem(reg, val); 292 } 293 294 bool 295 readPredicate() const override 296 { 297 return thread.readPredicate(); 298 } 299 300 void 301 setPredicate(bool val) override 302 { 303 thread.setPredicate(val); 304 } 305 306 TheISA::PCState 307 pcState() const override 308 { 309 return thread.pcState(); 310 } 311 312 void 313 pcState(const TheISA::PCState &val) override 314 { 315 thread.pcState(val); 316 } 317 318 TheISA::MiscReg 319 readMiscRegNoEffect(int misc_reg) const 320 { 321 return thread.readMiscRegNoEffect(misc_reg); 322 } 323 324 TheISA::MiscReg 325 readMiscReg(int misc_reg) override 326 { 327 return thread.readMiscReg(misc_reg); 328 } 329 330 void 331 setMiscReg(int misc_reg, const TheISA::MiscReg &val) override 332 { 333 thread.setMiscReg(misc_reg, val); 334 } 335 336 TheISA::MiscReg 337 readMiscRegOperand(const StaticInst *si, int idx) override 338 { 339 const RegId& reg = si->srcRegIdx(idx); 340 assert(reg.isMiscReg()); 341 return thread.readMiscReg(reg.index()); 342 } 343 344 void 345 setMiscRegOperand(const StaticInst *si, int idx, 346 const TheISA::MiscReg &val) override 347 { 348 const RegId& reg = si->destRegIdx(idx); 349 assert(reg.isMiscReg()); 350 return thread.setMiscReg(reg.index(), val); 351 } 352 353 Fault 354 hwrei() override 355 { 356#if THE_ISA == ALPHA_ISA 357 return thread.hwrei(); 358#else 359 return NoFault; 360#endif 361 } 362 363 bool 364 simPalCheck(int palFunc) override 365 { 366#if THE_ISA == ALPHA_ISA 367 return thread.simPalCheck(palFunc); 368#else 369 return false; 370#endif 371 } 372 373 void 374 syscall(int64_t callnum, Fault *fault) override 375 { 376 if (FullSystem) 377 panic("Syscall emulation isn't available in FS mode.\n"); 378 379 thread.syscall(callnum, fault); 380 } 381 382 ThreadContext *tcBase() override { return thread.getTC(); } 383 384 /* @todo, should make stCondFailures persistent somewhere */ 385 unsigned int readStCondFailures() const override { return 0; } 386 void setStCondFailures(unsigned int st_cond_failures) override {} 387 388 ContextID contextId() { return thread.contextId(); } 389 /* ISA-specific (or at least currently ISA singleton) functions */ 390 391 /* X86: TLB twiddling */ 392 void 393 demapPage(Addr vaddr, uint64_t asn) override 394 { 395 thread.getITBPtr()->demapPage(vaddr, asn); 396 thread.getDTBPtr()->demapPage(vaddr, asn); 397 } 398 399 TheISA::CCReg 400 readCCRegOperand(const StaticInst *si, int idx) override 401 { 402 const RegId& reg = si->srcRegIdx(idx); 403 assert(reg.isCCReg()); 404 return thread.readCCReg(reg.index()); 405 } 406 407 void 408 setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override 409 { 410 const RegId& reg = si->destRegIdx(idx); 411 assert(reg.isCCReg()); 412 thread.setCCReg(reg.index(), val); 413 } 414 415 void 416 demapInstPage(Addr vaddr, uint64_t asn) 417 { 418 thread.getITBPtr()->demapPage(vaddr, asn); 419 } 420 421 void 422 demapDataPage(Addr vaddr, uint64_t asn) 423 { 424 thread.getDTBPtr()->demapPage(vaddr, asn); 425 } 426 427 BaseCPU *getCpuPtr() { return &cpu; } 428 429 /* MIPS: other thread register reading/writing */ 430 uint64_t 431 readRegOtherThread(const RegId& reg, ThreadID tid = InvalidThreadID) 432 { 433 SimpleThread *other_thread = (tid == InvalidThreadID 434 ? &thread : cpu.threads[tid]); 435 436 switch (reg.classValue()) { 437 case IntRegClass: 438 return other_thread->readIntReg(reg.index()); 439 break; 440 case FloatRegClass: 441 return other_thread->readFloatRegBits(reg.index()); 442 break; 443 case MiscRegClass: 444 return other_thread->readMiscReg(reg.index()); 445 default: 446 panic("Unexpected reg class! (%s)", 447 reg.className()); 448 return 0; 449 } 450 } 451 452 void 453 setRegOtherThread(const RegId& reg, const TheISA::MiscReg &val, 454 ThreadID tid = InvalidThreadID) 455 { 456 SimpleThread *other_thread = (tid == InvalidThreadID 457 ? &thread : cpu.threads[tid]); 458 459 switch (reg.classValue()) { 460 case IntRegClass: 461 return other_thread->setIntReg(reg.index(), val); 462 break; 463 case FloatRegClass: 464 return other_thread->setFloatRegBits(reg.index(), val); 465 break; 466 case MiscRegClass: 467 return other_thread->setMiscReg(reg.index(), val); 468 default: 469 panic("Unexpected reg class! (%s)", 470 reg.className()); 471 } 472 } 473 474 public: 475 // monitor/mwait funtions 476 void armMonitor(Addr address) override 477 { getCpuPtr()->armMonitor(inst->id.threadId, address); } 478 479 bool mwait(PacketPtr pkt) override 480 { return getCpuPtr()->mwait(inst->id.threadId, pkt); } 481 482 void mwaitAtomic(ThreadContext *tc) override 483 { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); } 484 485 AddressMonitor *getAddrMonitor() override 486 { return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId); } 487}; 488 489} 490 491#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */ 492