dyn_inst.hh revision 10259
13101Sstever@eecs.umich.edu/* 23101Sstever@eecs.umich.edu * Copyright (c) 2013-2014 ARM Limited 33101Sstever@eecs.umich.edu * All rights reserved 43101Sstever@eecs.umich.edu * 53101Sstever@eecs.umich.edu * The license below extends only to copyright in the software and shall 63101Sstever@eecs.umich.edu * not be construed as granting a license to any other intellectual 73101Sstever@eecs.umich.edu * property including but not limited to intellectual property relating 83101Sstever@eecs.umich.edu * to a hardware implementation of the functionality of the software 93101Sstever@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 103101Sstever@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 113101Sstever@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 123101Sstever@eecs.umich.edu * modified or unmodified, in source code or in binary form. 133101Sstever@eecs.umich.edu * 143101Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 153101Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 163101Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 173101Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 183101Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 193101Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 203101Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 213101Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 223101Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 233101Sstever@eecs.umich.edu * this software without specific prior written permission. 243101Sstever@eecs.umich.edu * 253101Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 263101Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 273101Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 283101Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 293101Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 303101Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 313101Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 323101Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 333101Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 343101Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 353101Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 363101Sstever@eecs.umich.edu * 373101Sstever@eecs.umich.edu * Authors: Andrew Bardsley 383101Sstever@eecs.umich.edu */ 393101Sstever@eecs.umich.edu 403101Sstever@eecs.umich.edu/** 413101Sstever@eecs.umich.edu * @file 423101Sstever@eecs.umich.edu * 433101Sstever@eecs.umich.edu * The dynamic instruction and instruction/line id (sequence numbers) 443101Sstever@eecs.umich.edu * definition for Minor. A spirited attempt is made here to not carry too 453101Sstever@eecs.umich.edu * much on this structure. 463101Sstever@eecs.umich.edu */ 473885Sbinkertn@umich.edu 483885Sbinkertn@umich.edu#ifndef __CPU_MINOR_DYN_INST_HH__ 493885Sbinkertn@umich.edu#define __CPU_MINOR_DYN_INST_HH__ 504762Snate@binkert.org 513885Sbinkertn@umich.edu#include <iostream> 523885Sbinkertn@umich.edu 533885Sbinkertn@umich.edu#include "base/refcnt.hh" 543101Sstever@eecs.umich.edu#include "cpu/minor/buffers.hh" 554380Sbinkertn@umich.edu#include "cpu/inst_seq.hh" 564167Sbinkertn@umich.edu#include "cpu/static_inst.hh" 573102Sstever@eecs.umich.edu#include "cpu/timing_expr.hh" 583101Sstever@eecs.umich.edu#include "sim/faults.hh" 594762Snate@binkert.org 604762Snate@binkert.orgnamespace Minor 614762Snate@binkert.org{ 624762Snate@binkert.org 634762Snate@binkert.orgclass MinorDynInst; 644762Snate@binkert.org 654762Snate@binkert.org/** MinorDynInsts are currently reference counted. */ 664762Snate@binkert.orgtypedef RefCountingPtr<MinorDynInst> MinorDynInstPtr; 674762Snate@binkert.org 684762Snate@binkert.org/** Id for lines and instructions. This includes all the relevant sequence 694762Snate@binkert.org * numbers and thread ids for all stages of execution. */ 703101Sstever@eecs.umich.educlass InstId 713101Sstever@eecs.umich.edu{ 723101Sstever@eecs.umich.edu public: 733101Sstever@eecs.umich.edu /** First sequence numbers to use in initialisation of the pipeline and 743101Sstever@eecs.umich.edu * to be expected on the first line/instruction issued */ 753101Sstever@eecs.umich.edu static const InstSeqNum firstStreamSeqNum = 1; 763101Sstever@eecs.umich.edu static const InstSeqNum firstPredictionSeqNum = 1; 773101Sstever@eecs.umich.edu static const InstSeqNum firstLineSeqNum = 1; 783101Sstever@eecs.umich.edu static const InstSeqNum firstFetchSeqNum = 1; 793101Sstever@eecs.umich.edu static const InstSeqNum firstExecSeqNum = 1; 803101Sstever@eecs.umich.edu 813101Sstever@eecs.umich.edu public: 823101Sstever@eecs.umich.edu /** The thread to which this line/instruction belongs */ 833101Sstever@eecs.umich.edu ThreadID threadId; 843101Sstever@eecs.umich.edu 853101Sstever@eecs.umich.edu /** The 'stream' this instruction belongs to. Streams are interrupted 863101Sstever@eecs.umich.edu * (and sequence numbers increased) when Execute finds it wants to 873101Sstever@eecs.umich.edu * change the stream of instructions due to a branch. */ 883101Sstever@eecs.umich.edu InstSeqNum streamSeqNum; 893101Sstever@eecs.umich.edu 903101Sstever@eecs.umich.edu /** The predicted qualifier to stream, attached by Fetch2 as a 913101Sstever@eecs.umich.edu * consequence of branch prediction */ 923101Sstever@eecs.umich.edu InstSeqNum predictionSeqNum; 933101Sstever@eecs.umich.edu 943101Sstever@eecs.umich.edu /** Line sequence number. This is the sequence number of the fetched 953101Sstever@eecs.umich.edu * line from which this instruction was fetched */ 963101Sstever@eecs.umich.edu InstSeqNum lineSeqNum; 973101Sstever@eecs.umich.edu 983101Sstever@eecs.umich.edu /** Fetch sequence number. This is 0 for bubbles and an ascending 993101Sstever@eecs.umich.edu * sequence for the stream of all fetched instructions */ 1003101Sstever@eecs.umich.edu InstSeqNum fetchSeqNum; 1013101Sstever@eecs.umich.edu 1023101Sstever@eecs.umich.edu /** 'Execute' sequence number. These are assigned after micro-op 1033101Sstever@eecs.umich.edu * decomposition and form an ascending sequence (starting with 1) for 1043101Sstever@eecs.umich.edu * post-micro-op decomposed instructions. */ 1053101Sstever@eecs.umich.edu InstSeqNum execSeqNum; 1063101Sstever@eecs.umich.edu 1073101Sstever@eecs.umich.edu public: 1083101Sstever@eecs.umich.edu /** Very boring default constructor */ 1093101Sstever@eecs.umich.edu InstId( 1103101Sstever@eecs.umich.edu ThreadID thread_id = 0, InstSeqNum stream_seq_num = 0, 1113101Sstever@eecs.umich.edu InstSeqNum prediction_seq_num = 0, InstSeqNum line_seq_num = 0, 1123101Sstever@eecs.umich.edu InstSeqNum fetch_seq_num = 0, InstSeqNum exec_seq_num = 0) : 1133101Sstever@eecs.umich.edu threadId(thread_id), streamSeqNum(stream_seq_num), 1143101Sstever@eecs.umich.edu predictionSeqNum(prediction_seq_num), lineSeqNum(line_seq_num), 1153101Sstever@eecs.umich.edu fetchSeqNum(fetch_seq_num), execSeqNum(exec_seq_num) 1163101Sstever@eecs.umich.edu { } 1173101Sstever@eecs.umich.edu 1183101Sstever@eecs.umich.edu public: 1193101Sstever@eecs.umich.edu /* Equal if the thread and last set sequence number matches */ 1203101Sstever@eecs.umich.edu bool 1213101Sstever@eecs.umich.edu operator== (const InstId &rhs) 1223101Sstever@eecs.umich.edu { 1234762Snate@binkert.org /* If any of fetch and exec sequence number are not set 1243101Sstever@eecs.umich.edu * they need to be 0, so a straight comparison is still 1253102Sstever@eecs.umich.edu * fine */ 1263101Sstever@eecs.umich.edu bool ret = (threadId == rhs.threadId && 1273101Sstever@eecs.umich.edu lineSeqNum == rhs.lineSeqNum && 1283101Sstever@eecs.umich.edu fetchSeqNum == rhs.fetchSeqNum && 1294762Snate@binkert.org execSeqNum == rhs.execSeqNum); 1304762Snate@binkert.org 1314762Snate@binkert.org /* Stream and prediction *must* match if these are the same id */ 1323101Sstever@eecs.umich.edu if (ret) { 1333101Sstever@eecs.umich.edu assert(streamSeqNum == rhs.streamSeqNum && 1343101Sstever@eecs.umich.edu predictionSeqNum == rhs.predictionSeqNum); 1353101Sstever@eecs.umich.edu } 1363101Sstever@eecs.umich.edu 1373101Sstever@eecs.umich.edu return ret; 1383101Sstever@eecs.umich.edu } 1393101Sstever@eecs.umich.edu}; 1403101Sstever@eecs.umich.edu 1413101Sstever@eecs.umich.edu/** Print this id in the usual slash-separated format expected by 1423101Sstever@eecs.umich.edu * MinorTrace */ 1433101Sstever@eecs.umich.edustd::ostream &operator <<(std::ostream &os, const InstId &id); 1443101Sstever@eecs.umich.edu 1453102Sstever@eecs.umich.educlass MinorDynInst; 1463101Sstever@eecs.umich.edu 1473101Sstever@eecs.umich.edu/** Print a short reference to this instruction. '-' for a bubble and a 1483101Sstever@eecs.umich.edu * series of '/' separated sequence numbers for other instructions. The 1493101Sstever@eecs.umich.edu * sequence numbers will be in the order: stream, prediction, line, fetch, 1503101Sstever@eecs.umich.edu * exec with exec absent if it is 0. This is used by MinorTrace. */ 1513101Sstever@eecs.umich.edustd::ostream &operator <<(std::ostream &os, const MinorDynInst &inst); 1523101Sstever@eecs.umich.edu 1533101Sstever@eecs.umich.edu/** Dynamic instruction for Minor. 1543101Sstever@eecs.umich.edu * MinorDynInst implements the BubbleIF interface 1553101Sstever@eecs.umich.edu * Has two separate notions of sequence number for pre/post-micro-op 1563101Sstever@eecs.umich.edu * decomposition: fetchSeqNum and execSeqNum */ 1573101Sstever@eecs.umich.educlass MinorDynInst : public RefCounted 1583101Sstever@eecs.umich.edu{ 1593101Sstever@eecs.umich.edu private: 1603101Sstever@eecs.umich.edu /** A prototypical bubble instruction. You must call MinorDynInst::init 1613101Sstever@eecs.umich.edu * to initialise this */ 1623101Sstever@eecs.umich.edu static MinorDynInstPtr bubbleInst; 1633101Sstever@eecs.umich.edu 1643101Sstever@eecs.umich.edu public: 1653101Sstever@eecs.umich.edu StaticInstPtr staticInst; 1664762Snate@binkert.org 1674762Snate@binkert.org InstId id; 1684762Snate@binkert.org 1693101Sstever@eecs.umich.edu /** Trace information for this instruction's execution */ 1703101Sstever@eecs.umich.edu Trace::InstRecord *traceData; 1713101Sstever@eecs.umich.edu 1723101Sstever@eecs.umich.edu /** The fetch address of this instruction */ 1733101Sstever@eecs.umich.edu TheISA::PCState pc; 1743101Sstever@eecs.umich.edu 1753101Sstever@eecs.umich.edu /** This is actually a fault masquerading as an instruction */ 1763101Sstever@eecs.umich.edu Fault fault; 1773101Sstever@eecs.umich.edu 1783101Sstever@eecs.umich.edu /** Tried to predict the destination of this inst (if a control 1793101Sstever@eecs.umich.edu * instruction or a sys call) */ 1803101Sstever@eecs.umich.edu bool triedToPredict; 1813101Sstever@eecs.umich.edu 1823101Sstever@eecs.umich.edu /** This instruction was predicted to change control flow and 1833101Sstever@eecs.umich.edu * the following instructions will have a newer predictionSeqNum */ 1843101Sstever@eecs.umich.edu bool predictedTaken; 1854762Snate@binkert.org 1864762Snate@binkert.org /** Predicted branch target */ 1874762Snate@binkert.org TheISA::PCState predictedTarget; 1884762Snate@binkert.org 1894762Snate@binkert.org /** Fields only set during execution */ 1904762Snate@binkert.org 1914762Snate@binkert.org /** FU this instruction is issued to */ 1924762Snate@binkert.org unsigned int fuIndex; 1934762Snate@binkert.org 1944762Snate@binkert.org /** This instruction is in the LSQ, not a functional unit */ 1954762Snate@binkert.org bool inLSQ; 1964762Snate@binkert.org 1974762Snate@binkert.org /** The instruction has been sent to the store buffer */ 1984762Snate@binkert.org bool inStoreBuffer; 1994762Snate@binkert.org 2004762Snate@binkert.org /** Can this instruction be executed out of order. In this model, 2013101Sstever@eecs.umich.edu * this only happens with mem refs that need to be issued early 2023101Sstever@eecs.umich.edu * to allow other instructions to fill the fetch delay */ 2033101Sstever@eecs.umich.edu bool canEarlyIssue; 2043101Sstever@eecs.umich.edu 2053101Sstever@eecs.umich.edu /** execSeqNum of the latest inst on which this inst depends. 2063101Sstever@eecs.umich.edu * This can be used as a sanity check for dependency ordering 2073101Sstever@eecs.umich.edu * where slightly out of order execution is required (notably 2083101Sstever@eecs.umich.edu * initiateAcc for memory ops) */ 2093101Sstever@eecs.umich.edu InstSeqNum instToWaitFor; 2103101Sstever@eecs.umich.edu 2113101Sstever@eecs.umich.edu /** Extra delay at the end of the pipeline */ 2123101Sstever@eecs.umich.edu Cycles extraCommitDelay; 2133101Sstever@eecs.umich.edu TimingExpr *extraCommitDelayExpr; 2143101Sstever@eecs.umich.edu 2153101Sstever@eecs.umich.edu /** Once issued, extraCommitDelay becomes minimumCommitCycle 2163101Sstever@eecs.umich.edu * to account for delay in absolute time */ 2173101Sstever@eecs.umich.edu Cycles minimumCommitCycle; 2183101Sstever@eecs.umich.edu 2193101Sstever@eecs.umich.edu /** Flat register indices so that, when clearing the scoreboard, we 2203101Sstever@eecs.umich.edu * have the same register indices as when the instruction was marked 2213101Sstever@eecs.umich.edu * up */ 2223101Sstever@eecs.umich.edu TheISA::RegIndex flatDestRegIdx[TheISA::MaxInstDestRegs]; 2233101Sstever@eecs.umich.edu 2243101Sstever@eecs.umich.edu /** Effective address as set by ExecContext::setEA */ 2253101Sstever@eecs.umich.edu Addr ea; 2263101Sstever@eecs.umich.edu 2273101Sstever@eecs.umich.edu public: 2283101Sstever@eecs.umich.edu MinorDynInst(InstId id_ = InstId(), Fault fault_ = NoFault) : 2293101Sstever@eecs.umich.edu staticInst(NULL), id(id_), traceData(NULL), 2303101Sstever@eecs.umich.edu pc(TheISA::PCState(0)), fault(fault_), 2313101Sstever@eecs.umich.edu triedToPredict(false), predictedTaken(false), 2323101Sstever@eecs.umich.edu fuIndex(0), inLSQ(false), inStoreBuffer(false), 2333101Sstever@eecs.umich.edu canEarlyIssue(false), 2343101Sstever@eecs.umich.edu instToWaitFor(0), extraCommitDelay(Cycles(0)), 2353101Sstever@eecs.umich.edu extraCommitDelayExpr(NULL), minimumCommitCycle(Cycles(0)), 2363101Sstever@eecs.umich.edu ea(0) 2373101Sstever@eecs.umich.edu { } 2383101Sstever@eecs.umich.edu 2393101Sstever@eecs.umich.edu public: 2403101Sstever@eecs.umich.edu /** The BubbleIF interface. */ 2413101Sstever@eecs.umich.edu bool isBubble() const { return id.fetchSeqNum == 0; } 2423101Sstever@eecs.umich.edu 2433101Sstever@eecs.umich.edu /** There is a single bubble inst */ 2443101Sstever@eecs.umich.edu static MinorDynInstPtr bubble() { return bubbleInst; } 2453101Sstever@eecs.umich.edu 2463101Sstever@eecs.umich.edu /** Is this a fault rather than instruction */ 2473101Sstever@eecs.umich.edu bool isFault() const { return fault != NoFault; } 2483101Sstever@eecs.umich.edu 2493101Sstever@eecs.umich.edu /** Is this a real instruction */ 2503101Sstever@eecs.umich.edu bool isInst() const { return !isBubble() && !isFault(); } 2513101Sstever@eecs.umich.edu 2523101Sstever@eecs.umich.edu /** Is this a real mem ref instruction */ 2533101Sstever@eecs.umich.edu bool isMemRef() const { return isInst() && staticInst->isMemRef(); } 2543101Sstever@eecs.umich.edu 2553101Sstever@eecs.umich.edu /** Is this an instruction that can be executed `for free' and 2563101Sstever@eecs.umich.edu * needn't spend time in an FU */ 2574762Snate@binkert.org bool isNoCostInst() const; 2584762Snate@binkert.org 2594762Snate@binkert.org /** Assuming this is not a fault, is this instruction either 2604762Snate@binkert.org * a whole instruction or the last microop from a macroop */ 2613101Sstever@eecs.umich.edu bool isLastOpInInst() const; 2623101Sstever@eecs.umich.edu 2633101Sstever@eecs.umich.edu /** Initialise the class */ 2643101Sstever@eecs.umich.edu static void init(); 2653101Sstever@eecs.umich.edu 2663101Sstever@eecs.umich.edu /** Print (possibly verbose) instruction information for 2673101Sstever@eecs.umich.edu * MinorTrace using the given Named object's name */ 2683101Sstever@eecs.umich.edu void minorTraceInst(const Named &named_object) const; 2693101Sstever@eecs.umich.edu 2703101Sstever@eecs.umich.edu /** ReportIF interface */ 2713101Sstever@eecs.umich.edu void reportData(std::ostream &os) const; 2723714Sstever@eecs.umich.edu 2733714Sstever@eecs.umich.edu ~MinorDynInst(); 2743714Sstever@eecs.umich.edu}; 2753714Sstever@eecs.umich.edu 2763714Sstever@eecs.umich.edu/** Print a summary of the instruction */ 2773714Sstever@eecs.umich.edustd::ostream &operator <<(std::ostream &os, const MinorDynInst &inst); 2783101Sstever@eecs.umich.edu 2793101Sstever@eecs.umich.edu} 2803101Sstever@eecs.umich.edu 2813101Sstever@eecs.umich.edu#endif /* __CPU_MINOR_DYN_INST_HH__ */ 2823101Sstever@eecs.umich.edu