dyn_inst.hh revision 12104
113558Snikos.nikoleris@arm.com/* 28839Sandreas.hansson@arm.com * Copyright (c) 2013-2014 ARM Limited 38839Sandreas.hansson@arm.com * All rights reserved 48839Sandreas.hansson@arm.com * 58839Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68839Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78839Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88839Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98839Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108839Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118839Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128839Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 133101Sstever@eecs.umich.edu * 148579Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 153101Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 163101Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 173101Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 183101Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 193101Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 203101Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 213101Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 223101Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 233101Sstever@eecs.umich.edu * this software without specific prior written permission. 243101Sstever@eecs.umich.edu * 253101Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 263101Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 273101Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 283101Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 293101Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 303101Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 313101Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 323101Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 333101Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 343101Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 353101Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 363101Sstever@eecs.umich.edu * 373101Sstever@eecs.umich.edu * Authors: Andrew Bardsley 383101Sstever@eecs.umich.edu */ 393101Sstever@eecs.umich.edu 403101Sstever@eecs.umich.edu/** 413101Sstever@eecs.umich.edu * @file 427778Sgblack@eecs.umich.edu * 438839Sandreas.hansson@arm.com * The dynamic instruction and instruction/line id (sequence numbers) 443101Sstever@eecs.umich.edu * definition for Minor. A spirited attempt is made here to not carry too 453101Sstever@eecs.umich.edu * much on this structure. 463101Sstever@eecs.umich.edu */ 473101Sstever@eecs.umich.edu 483101Sstever@eecs.umich.edu#ifndef __CPU_MINOR_DYN_INST_HH__ 493101Sstever@eecs.umich.edu#define __CPU_MINOR_DYN_INST_HH__ 503101Sstever@eecs.umich.edu 513101Sstever@eecs.umich.edu#include <iostream> 523101Sstever@eecs.umich.edu 533101Sstever@eecs.umich.edu#include "base/refcnt.hh" 543101Sstever@eecs.umich.edu#include "cpu/minor/buffers.hh" 553101Sstever@eecs.umich.edu#include "cpu/inst_seq.hh" 563101Sstever@eecs.umich.edu#include "cpu/static_inst.hh" 573101Sstever@eecs.umich.edu#include "cpu/timing_expr.hh" 583101Sstever@eecs.umich.edu#include "sim/faults.hh" 593101Sstever@eecs.umich.edu 603101Sstever@eecs.umich.edunamespace Minor 613101Sstever@eecs.umich.edu{ 6212563Sgabeblack@google.com 6313719Sandreas.sandberg@arm.comclass MinorDynInst; 6413719Sandreas.sandberg@arm.com 6513719Sandreas.sandberg@arm.com/** MinorDynInsts are currently reference counted. */ 6612563Sgabeblack@google.comtypedef RefCountingPtr<MinorDynInst> MinorDynInstPtr; 673885Sbinkertn@umich.edu 683885Sbinkertn@umich.edu/** Id for lines and instructions. This includes all the relevant sequence 694762Snate@binkert.org * numbers and thread ids for all stages of execution. */ 703885Sbinkertn@umich.educlass InstId 713885Sbinkertn@umich.edu{ 727528Ssteve.reinhardt@amd.com public: 733885Sbinkertn@umich.edu /** First sequence numbers to use in initialisation of the pipeline and 7413714Sandreas.sandberg@arm.com * to be expected on the first line/instruction issued */ 7513714Sandreas.sandberg@arm.com static const InstSeqNum firstStreamSeqNum = 1; 7613714Sandreas.sandberg@arm.com static const InstSeqNum firstPredictionSeqNum = 1; 773101Sstever@eecs.umich.edu static const InstSeqNum firstLineSeqNum = 1; 784762Snate@binkert.org static const InstSeqNum firstFetchSeqNum = 1; 7913716Sandreas.sandberg@arm.com static const InstSeqNum firstExecSeqNum = 1; 804762Snate@binkert.org 814762Snate@binkert.org public: 824762Snate@binkert.org /** The thread to which this line/instruction belongs */ 8313716Sandreas.sandberg@arm.com ThreadID threadId; 844762Snate@binkert.org 854762Snate@binkert.org /** The 'stream' this instruction belongs to. Streams are interrupted 864762Snate@binkert.org * (and sequence numbers increased) when Execute finds it wants to 8713716Sandreas.sandberg@arm.com * change the stream of instructions due to a branch. */ 884762Snate@binkert.org InstSeqNum streamSeqNum; 894762Snate@binkert.org 905033Smilesck@eecs.umich.edu /** The predicted qualifier to stream, attached by Fetch2 as a 915033Smilesck@eecs.umich.edu * consequence of branch prediction */ 925033Smilesck@eecs.umich.edu InstSeqNum predictionSeqNum; 935033Smilesck@eecs.umich.edu 945033Smilesck@eecs.umich.edu /** Line sequence number. This is the sequence number of the fetched 955033Smilesck@eecs.umich.edu * line from which this instruction was fetched */ 965033Smilesck@eecs.umich.edu InstSeqNum lineSeqNum; 975033Smilesck@eecs.umich.edu 985033Smilesck@eecs.umich.edu /** Fetch sequence number. This is 0 for bubbles and an ascending 995033Smilesck@eecs.umich.edu * sequence for the stream of all fetched instructions */ 1003101Sstever@eecs.umich.edu InstSeqNum fetchSeqNum; 1013101Sstever@eecs.umich.edu 1023101Sstever@eecs.umich.edu /** 'Execute' sequence number. These are assigned after micro-op 1035033Smilesck@eecs.umich.edu * decomposition and form an ascending sequence (starting with 1) for 10410267SGeoffrey.Blake@arm.com * post-micro-op decomposed instructions. */ 1058596Ssteve.reinhardt@amd.com InstSeqNum execSeqNum; 1068596Ssteve.reinhardt@amd.com 1078596Ssteve.reinhardt@amd.com public: 1088596Ssteve.reinhardt@amd.com /** Very boring default constructor */ 1097673Snate@binkert.org InstId( 1107673Snate@binkert.org ThreadID thread_id = 0, InstSeqNum stream_seq_num = 0, 1117673Snate@binkert.org InstSeqNum prediction_seq_num = 0, InstSeqNum line_seq_num = 0, 1127673Snate@binkert.org InstSeqNum fetch_seq_num = 0, InstSeqNum exec_seq_num = 0) : 11311988Sandreas.sandberg@arm.com threadId(thread_id), streamSeqNum(stream_seq_num), 11411988Sandreas.sandberg@arm.com predictionSeqNum(prediction_seq_num), lineSeqNum(line_seq_num), 11511988Sandreas.sandberg@arm.com fetchSeqNum(fetch_seq_num), execSeqNum(exec_seq_num) 11611988Sandreas.sandberg@arm.com { } 1173101Sstever@eecs.umich.edu 1183101Sstever@eecs.umich.edu public: 1193101Sstever@eecs.umich.edu /* Equal if the thread and last set sequence number matches */ 1203101Sstever@eecs.umich.edu bool 1213101Sstever@eecs.umich.edu operator== (const InstId &rhs) 12210380SAndrew.Bardsley@arm.com { 12310380SAndrew.Bardsley@arm.com /* If any of fetch and exec sequence number are not set 12410380SAndrew.Bardsley@arm.com * they need to be 0, so a straight comparison is still 12510380SAndrew.Bardsley@arm.com * fine */ 12610380SAndrew.Bardsley@arm.com bool ret = (threadId == rhs.threadId && 12710380SAndrew.Bardsley@arm.com lineSeqNum == rhs.lineSeqNum && 12810458Sandreas.hansson@arm.com fetchSeqNum == rhs.fetchSeqNum && 12910458Sandreas.hansson@arm.com execSeqNum == rhs.execSeqNum); 13010458Sandreas.hansson@arm.com 13110458Sandreas.hansson@arm.com /* Stream and prediction *must* match if these are the same id */ 13210458Sandreas.hansson@arm.com if (ret) { 13310458Sandreas.hansson@arm.com assert(streamSeqNum == rhs.streamSeqNum && 13410458Sandreas.hansson@arm.com predictionSeqNum == rhs.predictionSeqNum); 13510458Sandreas.hansson@arm.com } 13610458Sandreas.hansson@arm.com 13710458Sandreas.hansson@arm.com return ret; 13810458Sandreas.hansson@arm.com } 13910458Sandreas.hansson@arm.com}; 1403101Sstever@eecs.umich.edu 1413101Sstever@eecs.umich.edu/** Print this id in the usual slash-separated format expected by 1423101Sstever@eecs.umich.edu * MinorTrace */ 1433101Sstever@eecs.umich.edustd::ostream &operator <<(std::ostream &os, const InstId &id); 1443101Sstever@eecs.umich.edu 14510267SGeoffrey.Blake@arm.comclass MinorDynInst; 14610267SGeoffrey.Blake@arm.com 14710267SGeoffrey.Blake@arm.com/** Print a short reference to this instruction. '-' for a bubble and a 14810267SGeoffrey.Blake@arm.com * series of '/' separated sequence numbers for other instructions. The 1493101Sstever@eecs.umich.edu * sequence numbers will be in the order: stream, prediction, line, fetch, 1503101Sstever@eecs.umich.edu * exec with exec absent if it is 0. This is used by MinorTrace. */ 1513101Sstever@eecs.umich.edustd::ostream &operator <<(std::ostream &os, const MinorDynInst &inst); 1523101Sstever@eecs.umich.edu 1533101Sstever@eecs.umich.edu/** Dynamic instruction for Minor. 1543101Sstever@eecs.umich.edu * MinorDynInst implements the BubbleIF interface 1553101Sstever@eecs.umich.edu * Has two separate notions of sequence number for pre/post-micro-op 1563101Sstever@eecs.umich.edu * decomposition: fetchSeqNum and execSeqNum */ 1573101Sstever@eecs.umich.educlass MinorDynInst : public RefCounted 1583101Sstever@eecs.umich.edu{ 1593101Sstever@eecs.umich.edu private: 1603101Sstever@eecs.umich.edu /** A prototypical bubble instruction. You must call MinorDynInst::init 1613101Sstever@eecs.umich.edu * to initialise this */ 1623101Sstever@eecs.umich.edu static MinorDynInstPtr bubbleInst; 1633101Sstever@eecs.umich.edu 16413663Sandreas.sandberg@arm.com public: 1653101Sstever@eecs.umich.edu StaticInstPtr staticInst; 16613675Sandreas.sandberg@arm.com 1673101Sstever@eecs.umich.edu InstId id; 1683101Sstever@eecs.umich.edu 1693101Sstever@eecs.umich.edu /** Trace information for this instruction's execution */ 1703101Sstever@eecs.umich.edu Trace::InstRecord *traceData; 17113675Sandreas.sandberg@arm.com 1723101Sstever@eecs.umich.edu /** The fetch address of this instruction */ 1733101Sstever@eecs.umich.edu TheISA::PCState pc; 1743101Sstever@eecs.umich.edu 1753101Sstever@eecs.umich.edu /** This is actually a fault masquerading as an instruction */ 1763101Sstever@eecs.umich.edu Fault fault; 17713663Sandreas.sandberg@arm.com 1783101Sstever@eecs.umich.edu /** Tried to predict the destination of this inst (if a control 1793101Sstever@eecs.umich.edu * instruction or a sys call) */ 18013663Sandreas.sandberg@arm.com bool triedToPredict; 1813101Sstever@eecs.umich.edu 1823101Sstever@eecs.umich.edu /** This instruction was predicted to change control flow and 1833101Sstever@eecs.umich.edu * the following instructions will have a newer predictionSeqNum */ 18413716Sandreas.sandberg@arm.com bool predictedTaken; 1855033Smilesck@eecs.umich.edu 1866656Snate@binkert.org /** Predicted branch target */ 1875033Smilesck@eecs.umich.edu TheISA::PCState predictedTarget; 1885033Smilesck@eecs.umich.edu 1895033Smilesck@eecs.umich.edu /** Fields only set during execution */ 19013663Sandreas.sandberg@arm.com 19113663Sandreas.sandberg@arm.com /** FU this instruction is issued to */ 1923101Sstever@eecs.umich.edu unsigned int fuIndex; 19310267SGeoffrey.Blake@arm.com 19410267SGeoffrey.Blake@arm.com /** This instruction is in the LSQ, not a functional unit */ 19510267SGeoffrey.Blake@arm.com bool inLSQ; 19610267SGeoffrey.Blake@arm.com 19710267SGeoffrey.Blake@arm.com /** The instruction has been sent to the store buffer */ 19810267SGeoffrey.Blake@arm.com bool inStoreBuffer; 19910267SGeoffrey.Blake@arm.com 20010267SGeoffrey.Blake@arm.com /** Can this instruction be executed out of order. In this model, 20110267SGeoffrey.Blake@arm.com * this only happens with mem refs that need to be issued early 20210267SGeoffrey.Blake@arm.com * to allow other instructions to fill the fetch delay */ 20310267SGeoffrey.Blake@arm.com bool canEarlyIssue; 20410267SGeoffrey.Blake@arm.com 20510267SGeoffrey.Blake@arm.com /** execSeqNum of the latest inst on which this inst depends. 2063101Sstever@eecs.umich.edu * This can be used as a sanity check for dependency ordering 2073101Sstever@eecs.umich.edu * where slightly out of order execution is required (notably 2083101Sstever@eecs.umich.edu * initiateAcc for memory ops) */ 2093101Sstever@eecs.umich.edu InstSeqNum instToWaitFor; 21013699Sandreas.sandberg@arm.com 2113101Sstever@eecs.umich.edu /** Extra delay at the end of the pipeline */ 2123101Sstever@eecs.umich.edu Cycles extraCommitDelay; 2133101Sstever@eecs.umich.edu TimingExpr *extraCommitDelayExpr; 2143101Sstever@eecs.umich.edu 2153101Sstever@eecs.umich.edu /** Once issued, extraCommitDelay becomes minimumCommitCycle 2163102Sstever@eecs.umich.edu * to account for delay in absolute time */ 2173101Sstever@eecs.umich.edu Cycles minimumCommitCycle; 2183101Sstever@eecs.umich.edu 2193101Sstever@eecs.umich.edu /** Flat register indices so that, when clearing the scoreboard, we 22010267SGeoffrey.Blake@arm.com * have the same register indices as when the instruction was marked 22110267SGeoffrey.Blake@arm.com * up */ 22210267SGeoffrey.Blake@arm.com RegId flatDestRegIdx[TheISA::MaxInstDestRegs]; 22310267SGeoffrey.Blake@arm.com 22410267SGeoffrey.Blake@arm.com /** Effective address as set by ExecContext::setEA */ 22510267SGeoffrey.Blake@arm.com Addr ea; 22610267SGeoffrey.Blake@arm.com 2277673Snate@binkert.org public: 2288607Sgblack@eecs.umich.edu MinorDynInst(InstId id_ = InstId(), Fault fault_ = NoFault) : 2297673Snate@binkert.org staticInst(NULL), id(id_), traceData(NULL), 2303101Sstever@eecs.umich.edu pc(TheISA::PCState(0)), fault(fault_), 23111988Sandreas.sandberg@arm.com triedToPredict(false), predictedTaken(false), 23211988Sandreas.sandberg@arm.com fuIndex(0), inLSQ(false), inStoreBuffer(false), 23311988Sandreas.sandberg@arm.com canEarlyIssue(false), 2347673Snate@binkert.org instToWaitFor(0), extraCommitDelay(Cycles(0)), 2357673Snate@binkert.org extraCommitDelayExpr(NULL), minimumCommitCycle(Cycles(0)), 2363101Sstever@eecs.umich.edu ea(0) 2373101Sstever@eecs.umich.edu { } 2383101Sstever@eecs.umich.edu 2393101Sstever@eecs.umich.edu public: 2403101Sstever@eecs.umich.edu /** The BubbleIF interface. */ 2413101Sstever@eecs.umich.edu bool isBubble() const { return id.fetchSeqNum == 0; } 2425033Smilesck@eecs.umich.edu 2435475Snate@binkert.org /** There is a single bubble inst */ 24413663Sandreas.sandberg@arm.com static MinorDynInstPtr bubble() { return bubbleInst; } 24513663Sandreas.sandberg@arm.com 2465475Snate@binkert.org /** Is this a fault rather than instruction */ 24710380SAndrew.Bardsley@arm.com bool isFault() const { return fault != NoFault; } 24810380SAndrew.Bardsley@arm.com 24910380SAndrew.Bardsley@arm.com /** Is this a real instruction */ 2503101Sstever@eecs.umich.edu bool isInst() const { return !isBubble() && !isFault(); } 2513101Sstever@eecs.umich.edu 2523101Sstever@eecs.umich.edu /** Is this a real mem ref instruction */ 2534762Snate@binkert.org bool isMemRef() const { return isInst() && staticInst->isMemRef(); } 2544762Snate@binkert.org 2554762Snate@binkert.org /** Is this an instruction that can be executed `for free' and 2563101Sstever@eecs.umich.edu * needn't spend time in an FU */ 25712050Snikos.nikoleris@arm.com bool isNoCostInst() const; 25812050Snikos.nikoleris@arm.com 25912050Snikos.nikoleris@arm.com /** Assuming this is not a fault, is this instruction either 2608459SAli.Saidi@ARM.com * a whole instruction or the last microop from a macroop */ 2618459SAli.Saidi@ARM.com bool isLastOpInInst() const; 26212050Snikos.nikoleris@arm.com 2633101Sstever@eecs.umich.edu /** Initialise the class */ 2647528Ssteve.reinhardt@amd.com static void init(); 2657528Ssteve.reinhardt@amd.com 2667528Ssteve.reinhardt@amd.com /** Print (possibly verbose) instruction information for 2677528Ssteve.reinhardt@amd.com * MinorTrace using the given Named object's name */ 2687528Ssteve.reinhardt@amd.com void minorTraceInst(const Named &named_object) const; 2697528Ssteve.reinhardt@amd.com 2703101Sstever@eecs.umich.edu /** ReportIF interface */ 2717528Ssteve.reinhardt@amd.com void reportData(std::ostream &os) const; 2727528Ssteve.reinhardt@amd.com 2737528Ssteve.reinhardt@amd.com ~MinorDynInst(); 2747528Ssteve.reinhardt@amd.com}; 2757528Ssteve.reinhardt@amd.com 2767528Ssteve.reinhardt@amd.com/** Print a summary of the instruction */ 2777528Ssteve.reinhardt@amd.comstd::ostream &operator <<(std::ostream &os, const MinorDynInst &inst); 2787528Ssteve.reinhardt@amd.com 2797528Ssteve.reinhardt@amd.com} 2807528Ssteve.reinhardt@amd.com 2818321Ssteve.reinhardt@amd.com#endif /* __CPU_MINOR_DYN_INST_HH__ */ 28212194Sgabeblack@google.com