dyn_inst.cc revision 12104
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2013-2014 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1510259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1610259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 1710259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 1810259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1910259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2010259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2110259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2210259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2310259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2410259SAndrew.Bardsley@arm.com * 2510259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610259SAndrew.Bardsley@arm.com * 3710259SAndrew.Bardsley@arm.com * Authors: Andrew Bardsley 3810259SAndrew.Bardsley@arm.com */ 3910259SAndrew.Bardsley@arm.com 4011793Sbrandon.potter@amd.com#include "cpu/minor/dyn_inst.hh" 4111793Sbrandon.potter@amd.com 4210259SAndrew.Bardsley@arm.com#include <iomanip> 4310259SAndrew.Bardsley@arm.com#include <sstream> 4410259SAndrew.Bardsley@arm.com 4510259SAndrew.Bardsley@arm.com#include "arch/isa.hh" 4610259SAndrew.Bardsley@arm.com#include "arch/registers.hh" 4711793Sbrandon.potter@amd.com#include "cpu/base.hh" 4810259SAndrew.Bardsley@arm.com#include "cpu/minor/trace.hh" 4910259SAndrew.Bardsley@arm.com#include "cpu/reg_class.hh" 5010259SAndrew.Bardsley@arm.com#include "debug/MinorExecute.hh" 5110259SAndrew.Bardsley@arm.com#include "enums/OpClass.hh" 5210259SAndrew.Bardsley@arm.com 5310259SAndrew.Bardsley@arm.comnamespace Minor 5410259SAndrew.Bardsley@arm.com{ 5510259SAndrew.Bardsley@arm.com 5611567Smitch.hayenga@arm.comconst InstSeqNum InstId::firstStreamSeqNum; 5711567Smitch.hayenga@arm.comconst InstSeqNum InstId::firstPredictionSeqNum; 5811567Smitch.hayenga@arm.comconst InstSeqNum InstId::firstLineSeqNum; 5911567Smitch.hayenga@arm.comconst InstSeqNum InstId::firstFetchSeqNum; 6011567Smitch.hayenga@arm.comconst InstSeqNum InstId::firstExecSeqNum; 6111567Smitch.hayenga@arm.com 6210259SAndrew.Bardsley@arm.comstd::ostream & 6310259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, const InstId &id) 6410259SAndrew.Bardsley@arm.com{ 6510259SAndrew.Bardsley@arm.com os << id.threadId << '/' << id.streamSeqNum << '.' 6610259SAndrew.Bardsley@arm.com << id.predictionSeqNum << '/' << id.lineSeqNum; 6710259SAndrew.Bardsley@arm.com 6810259SAndrew.Bardsley@arm.com /* Not all structures have fetch and exec sequence numbers */ 6910259SAndrew.Bardsley@arm.com if (id.fetchSeqNum != 0) { 7010259SAndrew.Bardsley@arm.com os << '/' << id.fetchSeqNum; 7110259SAndrew.Bardsley@arm.com if (id.execSeqNum != 0) 7210259SAndrew.Bardsley@arm.com os << '.' << id.execSeqNum; 7310259SAndrew.Bardsley@arm.com } 7410259SAndrew.Bardsley@arm.com 7510259SAndrew.Bardsley@arm.com return os; 7610259SAndrew.Bardsley@arm.com} 7710259SAndrew.Bardsley@arm.com 7810259SAndrew.Bardsley@arm.comMinorDynInstPtr MinorDynInst::bubbleInst = NULL; 7910259SAndrew.Bardsley@arm.com 8010259SAndrew.Bardsley@arm.comvoid 8110259SAndrew.Bardsley@arm.comMinorDynInst::init() 8210259SAndrew.Bardsley@arm.com{ 8310259SAndrew.Bardsley@arm.com if (!bubbleInst) { 8410259SAndrew.Bardsley@arm.com bubbleInst = new MinorDynInst(); 8510259SAndrew.Bardsley@arm.com assert(bubbleInst->isBubble()); 8610259SAndrew.Bardsley@arm.com /* Make bubbleInst immortal */ 8710259SAndrew.Bardsley@arm.com bubbleInst->incref(); 8810259SAndrew.Bardsley@arm.com } 8910259SAndrew.Bardsley@arm.com} 9010259SAndrew.Bardsley@arm.com 9110259SAndrew.Bardsley@arm.combool 9210259SAndrew.Bardsley@arm.comMinorDynInst::isLastOpInInst() const 9310259SAndrew.Bardsley@arm.com{ 9410259SAndrew.Bardsley@arm.com assert(staticInst); 9510259SAndrew.Bardsley@arm.com return !(staticInst->isMicroop() && !staticInst->isLastMicroop()); 9610259SAndrew.Bardsley@arm.com} 9710259SAndrew.Bardsley@arm.com 9810259SAndrew.Bardsley@arm.combool 9910259SAndrew.Bardsley@arm.comMinorDynInst::isNoCostInst() const 10010259SAndrew.Bardsley@arm.com{ 10110259SAndrew.Bardsley@arm.com return isInst() && staticInst->opClass() == No_OpClass; 10210259SAndrew.Bardsley@arm.com} 10310259SAndrew.Bardsley@arm.com 10410259SAndrew.Bardsley@arm.comvoid 10510259SAndrew.Bardsley@arm.comMinorDynInst::reportData(std::ostream &os) const 10610259SAndrew.Bardsley@arm.com{ 10710259SAndrew.Bardsley@arm.com if (isBubble()) 10810259SAndrew.Bardsley@arm.com os << "-"; 10910259SAndrew.Bardsley@arm.com else if (isFault()) 11010259SAndrew.Bardsley@arm.com os << "F;" << id; 11110259SAndrew.Bardsley@arm.com else 11210259SAndrew.Bardsley@arm.com os << id; 11310259SAndrew.Bardsley@arm.com} 11410259SAndrew.Bardsley@arm.com 11510259SAndrew.Bardsley@arm.comstd::ostream & 11610259SAndrew.Bardsley@arm.comoperator <<(std::ostream &os, const MinorDynInst &inst) 11710259SAndrew.Bardsley@arm.com{ 11810259SAndrew.Bardsley@arm.com os << inst.id << " pc: 0x" 11910259SAndrew.Bardsley@arm.com << std::hex << inst.pc.instAddr() << std::dec << " ("; 12010259SAndrew.Bardsley@arm.com 12110259SAndrew.Bardsley@arm.com if (inst.isFault()) 12210259SAndrew.Bardsley@arm.com os << "fault: \"" << inst.fault->name() << '"'; 12310259SAndrew.Bardsley@arm.com else if (inst.staticInst) 12410259SAndrew.Bardsley@arm.com os << inst.staticInst->getName(); 12510259SAndrew.Bardsley@arm.com else 12610259SAndrew.Bardsley@arm.com os << "bubble"; 12710259SAndrew.Bardsley@arm.com 12810259SAndrew.Bardsley@arm.com os << ')'; 12910259SAndrew.Bardsley@arm.com 13010259SAndrew.Bardsley@arm.com return os; 13110259SAndrew.Bardsley@arm.com} 13210259SAndrew.Bardsley@arm.com 13310259SAndrew.Bardsley@arm.com/** Print a register in the form r<n>, f<n>, m<n>(<name>), z for integer, 13410259SAndrew.Bardsley@arm.com * float, misc and zero registers given an 'architectural register number' */ 13510259SAndrew.Bardsley@arm.comstatic void 13612104Snathanael.premillieu@arm.comprintRegName(std::ostream &os, RegId reg) 13710259SAndrew.Bardsley@arm.com{ 13812104Snathanael.premillieu@arm.com RegClass reg_class = reg.regClass; 13910259SAndrew.Bardsley@arm.com 14010259SAndrew.Bardsley@arm.com switch (reg_class) 14110259SAndrew.Bardsley@arm.com { 14210259SAndrew.Bardsley@arm.com case MiscRegClass: 14310259SAndrew.Bardsley@arm.com { 14412104Snathanael.premillieu@arm.com RegIndex misc_reg = reg.regIdx; 14510259SAndrew.Bardsley@arm.com 14610259SAndrew.Bardsley@arm.com /* This is an ugly test because not all archs. have miscRegName */ 14710259SAndrew.Bardsley@arm.com#if THE_ISA == ARM_ISA 14810259SAndrew.Bardsley@arm.com os << 'm' << misc_reg << '(' << TheISA::miscRegName[misc_reg] << 14910259SAndrew.Bardsley@arm.com ')'; 15010259SAndrew.Bardsley@arm.com#else 15110259SAndrew.Bardsley@arm.com os << 'n' << misc_reg; 15210259SAndrew.Bardsley@arm.com#endif 15310259SAndrew.Bardsley@arm.com } 15410259SAndrew.Bardsley@arm.com break; 15510259SAndrew.Bardsley@arm.com case FloatRegClass: 15612104Snathanael.premillieu@arm.com os << 'f' << static_cast<unsigned int>(reg.regIdx); 15710259SAndrew.Bardsley@arm.com break; 15810259SAndrew.Bardsley@arm.com case IntRegClass: 15912104Snathanael.premillieu@arm.com if (reg.isZeroReg()) { 16010259SAndrew.Bardsley@arm.com os << 'z'; 16110259SAndrew.Bardsley@arm.com } else { 16212104Snathanael.premillieu@arm.com os << 'r' << static_cast<unsigned int>(reg.regIdx); 16310259SAndrew.Bardsley@arm.com } 16410259SAndrew.Bardsley@arm.com break; 16510259SAndrew.Bardsley@arm.com case CCRegClass: 16612104Snathanael.premillieu@arm.com os << 'c' << static_cast<unsigned int>(reg.regIdx); 16710259SAndrew.Bardsley@arm.com } 16810259SAndrew.Bardsley@arm.com} 16910259SAndrew.Bardsley@arm.com 17010259SAndrew.Bardsley@arm.comvoid 17110259SAndrew.Bardsley@arm.comMinorDynInst::minorTraceInst(const Named &named_object) const 17210259SAndrew.Bardsley@arm.com{ 17310259SAndrew.Bardsley@arm.com if (isFault()) { 17410259SAndrew.Bardsley@arm.com MINORINST(&named_object, "id=F;%s addr=0x%x fault=\"%s\"\n", 17510259SAndrew.Bardsley@arm.com id, pc.instAddr(), fault->name()); 17610259SAndrew.Bardsley@arm.com } else { 17710259SAndrew.Bardsley@arm.com unsigned int num_src_regs = staticInst->numSrcRegs(); 17810259SAndrew.Bardsley@arm.com unsigned int num_dest_regs = staticInst->numDestRegs(); 17910259SAndrew.Bardsley@arm.com 18010259SAndrew.Bardsley@arm.com std::ostringstream regs_str; 18110259SAndrew.Bardsley@arm.com 18210259SAndrew.Bardsley@arm.com /* Format lists of src and dest registers for microops and 18310259SAndrew.Bardsley@arm.com * 'full' instructions */ 18410259SAndrew.Bardsley@arm.com if (!staticInst->isMacroop()) { 18510259SAndrew.Bardsley@arm.com regs_str << " srcRegs="; 18610259SAndrew.Bardsley@arm.com 18710259SAndrew.Bardsley@arm.com unsigned int src_reg = 0; 18810259SAndrew.Bardsley@arm.com while (src_reg < num_src_regs) { 18910259SAndrew.Bardsley@arm.com printRegName(regs_str, staticInst->srcRegIdx(src_reg)); 19010259SAndrew.Bardsley@arm.com 19110259SAndrew.Bardsley@arm.com src_reg++; 19210259SAndrew.Bardsley@arm.com if (src_reg != num_src_regs) 19310259SAndrew.Bardsley@arm.com regs_str << ','; 19410259SAndrew.Bardsley@arm.com } 19510259SAndrew.Bardsley@arm.com 19610259SAndrew.Bardsley@arm.com regs_str << " destRegs="; 19710259SAndrew.Bardsley@arm.com 19810259SAndrew.Bardsley@arm.com unsigned int dest_reg = 0; 19910259SAndrew.Bardsley@arm.com while (dest_reg < num_dest_regs) { 20010259SAndrew.Bardsley@arm.com printRegName(regs_str, staticInst->destRegIdx(dest_reg)); 20110259SAndrew.Bardsley@arm.com 20210259SAndrew.Bardsley@arm.com dest_reg++; 20310259SAndrew.Bardsley@arm.com if (dest_reg != num_dest_regs) 20410259SAndrew.Bardsley@arm.com regs_str << ','; 20510259SAndrew.Bardsley@arm.com } 20610259SAndrew.Bardsley@arm.com 20710259SAndrew.Bardsley@arm.com#if THE_ISA == ARM_ISA 20810259SAndrew.Bardsley@arm.com regs_str << " extMachInst=" << std::hex << std::setw(16) 20910259SAndrew.Bardsley@arm.com << std::setfill('0') << staticInst->machInst << std::dec; 21010259SAndrew.Bardsley@arm.com#endif 21110259SAndrew.Bardsley@arm.com } 21210259SAndrew.Bardsley@arm.com 21310259SAndrew.Bardsley@arm.com std::ostringstream flags; 21410259SAndrew.Bardsley@arm.com staticInst->printFlags(flags, " "); 21510259SAndrew.Bardsley@arm.com 21610259SAndrew.Bardsley@arm.com MINORINST(&named_object, "id=%s addr=0x%x inst=\"%s\" class=%s" 21710259SAndrew.Bardsley@arm.com " flags=\"%s\"%s%s\n", 21810259SAndrew.Bardsley@arm.com id, pc.instAddr(), 21910259SAndrew.Bardsley@arm.com (staticInst->opClass() == No_OpClass ? 22010259SAndrew.Bardsley@arm.com "(invalid)" : staticInst->disassemble(0,NULL)), 22110259SAndrew.Bardsley@arm.com Enums::OpClassStrings[staticInst->opClass()], 22210259SAndrew.Bardsley@arm.com flags.str(), 22310259SAndrew.Bardsley@arm.com regs_str.str(), 22410259SAndrew.Bardsley@arm.com (predictedTaken ? " predictedTaken" : "")); 22510259SAndrew.Bardsley@arm.com } 22610259SAndrew.Bardsley@arm.com} 22710259SAndrew.Bardsley@arm.com 22810259SAndrew.Bardsley@arm.comMinorDynInst::~MinorDynInst() 22910259SAndrew.Bardsley@arm.com{ 23010259SAndrew.Bardsley@arm.com if (traceData) 23110259SAndrew.Bardsley@arm.com delete traceData; 23210259SAndrew.Bardsley@arm.com} 23310259SAndrew.Bardsley@arm.com 23410259SAndrew.Bardsley@arm.com} 235