decode.hh revision 10259:ebb376f73dd2
1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Andrew Bardsley 38 */ 39 40/** 41 * @file 42 * 43 * Decode collects macro-ops from Fetch2 and splits them into micro-ops 44 * passed to Execute. 45 */ 46 47#ifndef __CPU_MINOR_DECODE_HH__ 48#define __CPU_MINOR_DECODE_HH__ 49 50#include "cpu/minor/buffers.hh" 51#include "cpu/minor/cpu.hh" 52#include "cpu/minor/dyn_inst.hh" 53#include "cpu/minor/pipe_data.hh" 54 55namespace Minor 56{ 57 58/* Decode takes instructions from Fetch2 and decomposes them into micro-ops 59 * to feed to Execute. It generates a new sequence number for each 60 * instruction: execSeqNum. 61 */ 62class Decode : public Named 63{ 64 protected: 65 /** Pointer back to the containing CPU */ 66 MinorCPU &cpu; 67 68 /** Input port carrying macro instructions from Fetch2 */ 69 Latch<ForwardInstData>::Output inp; 70 /** Output port carrying micro-op decomposed instructions to Execute */ 71 Latch<ForwardInstData>::Input out; 72 73 /** Interface to reserve space in the next stage */ 74 Reservable &nextStageReserve; 75 76 /** Width of output of this stage/input of next in instructions */ 77 unsigned int outputWidth; 78 79 /** If true, more than one input word can be processed each cycle if 80 * there is room in the output to contain its processed data */ 81 bool processMoreThanOneInput; 82 83 public: 84 /* Public for Pipeline to be able to pass it to Fetch2 */ 85 InputBuffer<ForwardInstData> inputBuffer; 86 87 protected: 88 /** Data members after this line are cycle-to-cycle state */ 89 90 /** Index into the inputBuffer's head marking the start of unhandled 91 * instructions */ 92 unsigned int inputIndex; 93 94 /** True when we're in the process of decomposing a micro-op and 95 * microopPC will be valid. This is only the case when there isn't 96 * sufficient space in Executes input buffer to take the whole of a 97 * decomposed instruction and some of that instructions micro-ops must 98 * be generated in a later cycle */ 99 bool inMacroop; 100 TheISA::PCState microopPC; 101 102 /** Source of execSeqNums to number instructions. */ 103 InstSeqNum execSeqNum; 104 105 /** Blocked indication for report */ 106 bool blocked; 107 108 protected: 109 /** Get a piece of data to work on, or 0 if there is no data. */ 110 const ForwardInstData *getInput(); 111 112 /** Pop an element off the input buffer, if there are any */ 113 void popInput(); 114 115 public: 116 Decode(const std::string &name, 117 MinorCPU &cpu_, 118 MinorCPUParams ¶ms, 119 Latch<ForwardInstData>::Output inp_, 120 Latch<ForwardInstData>::Input out_, 121 Reservable &next_stage_input_buffer); 122 123 public: 124 /** Pass on input/buffer data to the output if you can */ 125 void evaluate(); 126 127 void minorTrace() const; 128 129 /** Is this stage drained? For Decoed, draining is initiated by 130 * Execute halting Fetch1 causing Fetch2 to naturally drain 131 * into Decode and on to Execute which is responsible for 132 * actually killing instructions */ 133 bool isDrained(); 134}; 135 136} 137 138#endif /* __CPU_MINOR_DECODE_HH__ */ 139