decode.cc revision 10259:ebb376f73dd2 
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40#include "cpu/minor/decode.hh"
41#include "cpu/minor/pipeline.hh"
42#include "debug/Decode.hh"
43
44namespace Minor
45{
46
47Decode::Decode(const std::string &name,
48    MinorCPU &cpu_,
49    MinorCPUParams &params,
50    Latch<ForwardInstData>::Output inp_,
51    Latch<ForwardInstData>::Input out_,
52    Reservable &next_stage_input_buffer) :
53    Named(name),
54    cpu(cpu_),
55    inp(inp_),
56    out(out_),
57    nextStageReserve(next_stage_input_buffer),
58    outputWidth(params.executeInputWidth),
59    processMoreThanOneInput(params.decodeCycleInput),
60    inputBuffer(name + ".inputBuffer", "insts", params.decodeInputBufferSize),
61    inputIndex(0),
62    inMacroop(false),
63    execSeqNum(InstId::firstExecSeqNum)
64{
65    if (outputWidth < 1)
66        fatal("%s: executeInputWidth must be >= 1 (%d)\n", name, outputWidth);
67
68    if (params.decodeInputBufferSize < 1) {
69        fatal("%s: decodeInputBufferSize must be >= 1 (%d)\n", name,
70        params.decodeInputBufferSize);
71    }
72}
73
74const ForwardInstData *
75Decode::getInput()
76{
77    /* Get insts from the inputBuffer to work with */
78    if (!inputBuffer.empty()) {
79        const ForwardInstData &head = inputBuffer.front();
80
81        return (head.isBubble() ? NULL : &(inputBuffer.front()));
82    } else {
83        return NULL;
84    }
85}
86
87void
88Decode::popInput()
89{
90    if (!inputBuffer.empty())
91        inputBuffer.pop();
92
93    inputIndex = 0;
94    inMacroop = false;
95}
96
97#if TRACING_ON
98/** Add the tracing data to an instruction.  This originates in
99 *  decode because this is the first place that execSeqNums are known
100 *  (these are used as the 'FetchSeq' in tracing data) */
101static void
102dynInstAddTracing(MinorDynInstPtr inst, StaticInstPtr static_inst,
103    MinorCPU &cpu)
104{
105    inst->traceData = cpu.getTracer()->getInstRecord(curTick(),
106        cpu.getContext(inst->id.threadId),
107        inst->staticInst, inst->pc, static_inst);
108
109    /* Use the execSeqNum as the fetch sequence number as this most closely
110     *  matches the other processor models' idea of fetch sequence */
111    if (inst->traceData)
112        inst->traceData->setFetchSeq(inst->id.execSeqNum);
113}
114#endif
115
116void
117Decode::evaluate()
118{
119    inputBuffer.setTail(*inp.outputWire);
120    ForwardInstData &insts_out = *out.inputWire;
121
122    assert(insts_out.isBubble());
123
124    blocked = false;
125
126    if (!nextStageReserve.canReserve()) {
127        blocked = true;
128    } else {
129        const ForwardInstData *insts_in = getInput();
130
131        unsigned int output_index = 0;
132
133        /* Pack instructions into the output while we can.  This may involve
134         * using more than one input line */
135        while (insts_in &&
136           inputIndex < insts_in->width() && /* Still more input */
137           output_index < outputWidth /* Still more output to fill */)
138        {
139            MinorDynInstPtr inst = insts_in->insts[inputIndex];
140
141            if (inst->isBubble()) {
142                /* Skip */
143                inputIndex++;
144                inMacroop = false;
145            } else {
146                StaticInstPtr static_inst = inst->staticInst;
147                /* Static inst of a macro-op above the output_inst */
148                StaticInstPtr parent_static_inst = NULL;
149                MinorDynInstPtr output_inst = inst;
150
151                if (inst->isFault()) {
152                    DPRINTF(Decode, "Fault being passed: %d\n",
153                        inst->fault->name());
154
155                    inputIndex++;
156                    inMacroop = false;
157                } else if (static_inst->isMacroop()) {
158                    /* Generate a new micro-op */
159                    StaticInstPtr static_micro_inst;
160
161                    /* Set up PC for the next micro-op emitted */
162                    if (!inMacroop) {
163                        microopPC = inst->pc;
164                        inMacroop = true;
165                    }
166
167                    /* Get the micro-op static instruction from the
168                     * static_inst. */
169                    static_micro_inst =
170                        static_inst->fetchMicroop(microopPC.microPC());
171
172                    output_inst = new MinorDynInst(inst->id);
173                    output_inst->pc = microopPC;
174                    output_inst->staticInst = static_micro_inst;
175                    output_inst->fault = NoFault;
176
177                    /* Allow a predicted next address only on the last
178                     *  microop */
179                    if (static_micro_inst->isLastMicroop()) {
180                        output_inst->predictedTaken = inst->predictedTaken;
181                        output_inst->predictedTarget = inst->predictedTarget;
182                    }
183
184                    DPRINTF(Decode, "Microop decomposition inputIndex:"
185                        " %d output_index: %d lastMicroop: %s microopPC:"
186                        " %d.%d inst: %d\n",
187                        inputIndex, output_index,
188                        (static_micro_inst->isLastMicroop() ?
189                            "true" : "false"),
190                        microopPC.instAddr(), microopPC.microPC(),
191                        *output_inst);
192
193                    /* Acknowledge that the static_inst isn't mine, it's my
194                     * parent macro-op's */
195                    parent_static_inst = static_inst;
196
197                    static_micro_inst->advancePC(microopPC);
198
199                    /* Step input if this is the last micro-op */
200                    if (static_micro_inst->isLastMicroop()) {
201                        inputIndex++;
202                        inMacroop = false;
203                    }
204                } else {
205                    /* Doesn't need decomposing, pass on instruction */
206                    DPRINTF(Decode, "Passing on inst: %s inputIndex:"
207                        " %d output_index: %d\n",
208                        *output_inst, inputIndex, output_index);
209
210                    parent_static_inst = static_inst;
211
212                    /* Step input */
213                    inputIndex++;
214                    inMacroop = false;
215                }
216
217                /* Set execSeqNum of output_inst */
218                output_inst->id.execSeqNum = execSeqNum;
219                /* Add tracing */
220#if TRACING_ON
221                dynInstAddTracing(output_inst, parent_static_inst, cpu);
222#endif
223
224                /* Step to next sequence number */
225                execSeqNum++;
226
227                /* Correctly size the output before writing */
228                if(output_index == 0) insts_out.resize(outputWidth);
229                /* Push into output */
230                insts_out.insts[output_index] = output_inst;
231                output_index++;
232            }
233
234            /* Have we finished with the input? */
235            if (inputIndex == insts_in->width()) {
236                /* If we have just been producing micro-ops, we *must* have
237                 * got to the end of that for inputIndex to be pushed past
238                 * insts_in->width() */
239                assert(!inMacroop);
240                popInput();
241                insts_in = NULL;
242
243                if (processMoreThanOneInput) {
244                    DPRINTF(Decode, "Wrapping\n");
245                    insts_in = getInput();
246                }
247            }
248        }
249
250        /* The rest of the output (if any) should already have been packed
251         *  with bubble instructions by insts_out's initialisation
252         *
253         *  for (; output_index < outputWidth; output_index++)
254         *      assert(insts_out.insts[output_index]->isBubble());
255         */
256    }
257
258    /* If we generated output, reserve space for the result in the next stage
259     *  and mark the stage as being active this cycle */
260    if (!insts_out.isBubble()) {
261        /* Note activity of following buffer */
262        cpu.activityRecorder->activity();
263        nextStageReserve.reserve();
264    }
265
266    /* If we still have input to process and somewhere to put it,
267     *  mark stage as active */
268    if (getInput() && nextStageReserve.canReserve())
269        cpu.activityRecorder->activateStage(Pipeline::DecodeStageId);
270
271    /* Make sure the input (if any left) is pushed */
272    inputBuffer.pushTail();
273}
274
275bool
276Decode::isDrained()
277{
278    return inputBuffer.empty() && (*inp.outputWire).isBubble();
279}
280
281void
282Decode::minorTrace() const
283{
284    std::ostringstream data;
285
286    if (blocked)
287        data << 'B';
288    else
289        (*out.inputWire).reportData(data);
290
291    MINORTRACE("insts=%s\n", data.str());
292    inputBuffer.minorTrace();
293}
294
295}
296