cpu.hh revision 10913:38dbdeea7f1f 
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40/**
41 * @file
42 *
43 *  Top level definition of the Minor in-order CPU model
44 */
45
46#ifndef __CPU_MINOR_CPU_HH__
47#define __CPU_MINOR_CPU_HH__
48
49#include "cpu/minor/activity.hh"
50#include "cpu/minor/stats.hh"
51#include "cpu/base.hh"
52#include "cpu/simple_thread.hh"
53#include "params/MinorCPU.hh"
54
55namespace Minor
56{
57/** Forward declared to break the cyclic inclusion dependencies between
58 *  pipeline and cpu */
59class Pipeline;
60
61/** Minor will use the SimpleThread state for now */
62typedef SimpleThread MinorThread;
63};
64
65/**
66 *  MinorCPU is an in-order CPU model with four fixed pipeline stages:
67 *
68 *  Fetch1 - fetches lines from memory
69 *  Fetch2 - decomposes lines into macro-op instructions
70 *  Decode - decomposes macro-ops into micro-ops
71 *  Execute - executes those micro-ops
72 *
73 *  This pipeline is carried in the MinorCPU::pipeline object.
74 *  The exec_context interface is not carried by MinorCPU but by
75 *      Minor::ExecContext objects
76 *  created by Minor::Execute.
77 */
78class MinorCPU : public BaseCPU
79{
80  protected:
81    /** pipeline is a container for the clockable pipeline stage objects.
82     *  Elements of pipeline call TheISA to implement the model. */
83    Minor::Pipeline *pipeline;
84
85  public:
86    /** Activity recording for pipeline.  This belongs to Pipeline but
87     *  stages will access it through the CPU as the MinorCPU object
88     *  actually mediates idling behaviour */
89    Minor::MinorActivityRecorder *activityRecorder;
90
91    /** These are thread state-representing objects for this CPU.  If
92     *  you need a ThreadContext for *any* reason, use
93     *  threads[threadId]->getTC() */
94    std::vector<Minor::MinorThread *> threads;
95
96  public:
97    /** Provide a non-protected base class for Minor's Ports as derived
98     *  classes are created by Fetch1 and Execute */
99    class MinorCPUPort : public MasterPort
100    {
101      public:
102        /** The enclosing cpu */
103        MinorCPU &cpu;
104
105      public:
106        MinorCPUPort(const std::string& name_, MinorCPU &cpu_)
107            : MasterPort(name_, &cpu_), cpu(cpu_)
108        { }
109
110      protected:
111        /** Snooping a coherence request, do nothing.  */
112        virtual void recvTimingSnoopReq(PacketPtr pkt) { }
113    };
114
115  protected:
116     /** Return a reference to the data port. */
117    MasterPort &getDataPort();
118
119    /** Return a reference to the instruction port. */
120    MasterPort &getInstPort();
121
122  public:
123    MinorCPU(MinorCPUParams *params);
124
125    ~MinorCPU();
126
127  public:
128    /** Starting, waking and initialisation */
129    void init();
130    void startup();
131    void wakeup();
132
133    Addr dbg_vtophys(Addr addr);
134
135    /** Processor-specific statistics */
136    Minor::MinorStats stats;
137
138    /** Stats interface from SimObject (by way of BaseCPU) */
139    void regStats();
140
141    /** Simple inst count interface from BaseCPU */
142    Counter totalInsts() const;
143    Counter totalOps() const;
144
145    void serializeThread(CheckpointOut &cp,
146                         ThreadID tid) const M5_ATTR_OVERRIDE;
147    void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
148
149    /** Serialize pipeline data */
150    void serialize(CheckpointOut &cp) const;
151    void unserialize(CheckpointIn &cp);
152
153    /** Drain interface */
154    DrainState drain() M5_ATTR_OVERRIDE;
155    void drainResume() M5_ATTR_OVERRIDE;
156    /** Signal from Pipeline that MinorCPU should signal that a drain
157     *  is complete and set its drainState */
158    void signalDrainDone();
159    void memWriteback();
160
161    /** Switching interface from BaseCPU */
162    void switchOut();
163    void takeOverFrom(BaseCPU *old_cpu);
164
165    /** Thread activation interface from BaseCPU. */
166    void activateContext(ThreadID thread_id);
167    void suspendContext(ThreadID thread_id);
168
169    /** Interface for stages to signal that they have become active after
170     *  a callback or eventq event where the pipeline itself may have
171     *  already been idled.  The stage argument should be from the
172     *  enumeration Pipeline::StageId */
173    void wakeupOnEvent(unsigned int stage_id);
174};
175
176#endif /* __CPU_MINOR_CPU_HH__ */
177