MinorCPU.py revision 12563:8d59ed22ae79 
1# Copyright (c) 2012-2014 ARM Limited
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13# Copyright (c) 2007 The Regents of The University of Michigan
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38#
39# Authors: Gabe Black
40#          Nathan Binkert
41#          Andrew Bardsley
42
43from __future__ import print_function
44
45from m5.defines import buildEnv
46from m5.params import *
47from m5.proxy import *
48from m5.SimObject import SimObject
49from BaseCPU import BaseCPU
50from DummyChecker import DummyChecker
51from BranchPredictor import *
52from TimingExpr import TimingExpr
53
54from FuncUnit import OpClass
55
56class MinorOpClass(SimObject):
57    """Boxing of OpClass to get around build problems and provide a hook for
58    future additions to OpClass checks"""
59
60    type = 'MinorOpClass'
61    cxx_header = "cpu/minor/func_unit.hh"
62
63    opClass = Param.OpClass("op class to match")
64
65class MinorOpClassSet(SimObject):
66    """A set of matchable op classes"""
67
68    type = 'MinorOpClassSet'
69    cxx_header = "cpu/minor/func_unit.hh"
70
71    opClasses = VectorParam.MinorOpClass([], "op classes to be matched."
72        "  An empty list means any class")
73
74class MinorFUTiming(SimObject):
75    type = 'MinorFUTiming'
76    cxx_header = "cpu/minor/func_unit.hh"
77
78    mask = Param.UInt64(0, "mask for testing ExtMachInst")
79    match = Param.UInt64(0, "match value for testing ExtMachInst:"
80        " (ext_mach_inst & mask) == match")
81    suppress = Param.Bool(False, "if true, this inst. is not executed by"
82        " this FU")
83    extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for"
84        " this inst.")
85    extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a"
86        " run-time evaluated expression")
87    extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard"
88        " retire time for this insts dest registers once it leaves the"
89        " functional unit.  For mem refs, if this is 0, the result's time"
90        " is marked as unpredictable and no forwarding can take place.")
91    srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles"
92        " after inst. issue that each src reg can be available for this"
93        " inst. to issue")
94    opClasses = Param.MinorOpClassSet(MinorOpClassSet(),
95        "op classes to be considered for this decode.  An empty set means any"
96        " class")
97    description = Param.String('', "description string of the decoding/inst."
98        " class")
99
100def minorMakeOpClassSet(op_classes):
101    """Make a MinorOpClassSet from a list of OpClass enum value strings"""
102    def boxOpClass(op_class):
103        return MinorOpClass(opClass=op_class)
104
105    return MinorOpClassSet(opClasses=map(boxOpClass, op_classes))
106
107class MinorFU(SimObject):
108    type = 'MinorFU'
109    cxx_header = "cpu/minor/func_unit.hh"
110
111    opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations"
112        " allowed on this functional unit")
113    opLat = Param.Cycles(1, "latency in cycles")
114    issueLat = Param.Cycles(1, "cycles until another instruction can be"
115        " issued")
116    timings = VectorParam.MinorFUTiming([], "extra decoding rules")
117
118    cantForwardFromFUIndices = VectorParam.Unsigned([],
119        "list of FU indices from which this FU can't receive and early"
120        " (forwarded) result")
121
122class MinorFUPool(SimObject):
123    type = 'MinorFUPool'
124    cxx_header = "cpu/minor/func_unit.hh"
125
126    funcUnits = VectorParam.MinorFU("functional units")
127
128class MinorDefaultIntFU(MinorFU):
129    opClasses = minorMakeOpClassSet(['IntAlu'])
130    timings = [MinorFUTiming(description="Int",
131        srcRegsRelativeLats=[2])]
132    opLat = 3
133
134class MinorDefaultIntMulFU(MinorFU):
135    opClasses = minorMakeOpClassSet(['IntMult'])
136    timings = [MinorFUTiming(description='Mul',
137        srcRegsRelativeLats=[0])]
138    opLat = 3
139
140class MinorDefaultIntDivFU(MinorFU):
141    opClasses = minorMakeOpClassSet(['IntDiv'])
142    issueLat = 9
143    opLat = 9
144
145class MinorDefaultFloatSimdFU(MinorFU):
146    opClasses = minorMakeOpClassSet([
147        'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult',
148        'FloatMultAcc', 'FloatDiv', 'FloatSqrt',
149        'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
150        'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
151        'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
152        'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
153        'SimdFloatMultAcc', 'SimdFloatSqrt'])
154    timings = [MinorFUTiming(description='FloatSimd',
155        srcRegsRelativeLats=[2])]
156    opLat = 6
157
158class MinorDefaultMemFU(MinorFU):
159    opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead',
160                                     'FloatMemWrite'])
161    timings = [MinorFUTiming(description='Mem',
162        srcRegsRelativeLats=[1], extraAssumedLat=2)]
163    opLat = 1
164
165class MinorDefaultMiscFU(MinorFU):
166    opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch'])
167    opLat = 1
168
169class MinorDefaultFUPool(MinorFUPool):
170    funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(),
171        MinorDefaultIntMulFU(), MinorDefaultIntDivFU(),
172        MinorDefaultFloatSimdFU(), MinorDefaultMemFU(),
173        MinorDefaultMiscFU()]
174
175class ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random']
176
177class MinorCPU(BaseCPU):
178    type = 'MinorCPU'
179    cxx_header = "cpu/minor/cpu.hh"
180
181    @classmethod
182    def memory_mode(cls):
183        return 'timing'
184
185    @classmethod
186    def require_caches(cls):
187        return True
188
189    @classmethod
190    def support_take_over(cls):
191        return True
192
193    threadPolicy = Param.ThreadPolicy('RoundRobin',
194            "Thread scheduling policy")
195    fetch1FetchLimit = Param.Unsigned(1,
196        "Number of line fetches allowable in flight at once")
197    fetch1LineSnapWidth = Param.Unsigned(0,
198        "Fetch1 'line' fetch snap size in bytes"
199        " (0 means use system cache line size)")
200    fetch1LineWidth = Param.Unsigned(0,
201        "Fetch1 maximum fetch size in bytes (0 means use system cache"
202        " line size)")
203    fetch1ToFetch2ForwardDelay = Param.Cycles(1,
204        "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)")
205    fetch1ToFetch2BackwardDelay = Param.Cycles(1,
206        "Backward cycle delay from Fetch2 to Fetch1 for branch prediction"
207        " signalling (0 means in the same cycle, 1 mean the next cycle)")
208
209    fetch2InputBufferSize = Param.Unsigned(2,
210        "Size of input buffer to Fetch2 in cycles-worth of insts.")
211    fetch2ToDecodeForwardDelay = Param.Cycles(1,
212        "Forward cycle delay from Fetch2 to Decode (1 means next cycle)")
213    fetch2CycleInput = Param.Bool(True,
214        "Allow Fetch2 to cross input lines to generate full output each"
215        " cycle")
216
217    decodeInputBufferSize = Param.Unsigned(3,
218        "Size of input buffer to Decode in cycles-worth of insts.")
219    decodeToExecuteForwardDelay = Param.Cycles(1,
220        "Forward cycle delay from Decode to Execute (1 means next cycle)")
221    decodeInputWidth = Param.Unsigned(2,
222        "Width (in instructions) of input to Decode (and implicitly"
223        " Decode's own width)")
224    decodeCycleInput = Param.Bool(True,
225        "Allow Decode to pack instructions from more than one input cycle"
226        " to fill its output each cycle")
227
228    executeInputWidth = Param.Unsigned(2,
229        "Width (in instructions) of input to Execute")
230    executeCycleInput = Param.Bool(True,
231        "Allow Execute to use instructions from more than one input cycle"
232        " each cycle")
233    executeIssueLimit = Param.Unsigned(2,
234        "Number of issuable instructions in Execute each cycle")
235    executeMemoryIssueLimit = Param.Unsigned(1,
236        "Number of issuable memory instructions in Execute each cycle")
237    executeCommitLimit = Param.Unsigned(2,
238        "Number of committable instructions in Execute each cycle")
239    executeMemoryCommitLimit = Param.Unsigned(1,
240        "Number of committable memory references in Execute each cycle")
241    executeInputBufferSize = Param.Unsigned(7,
242        "Size of input buffer to Execute in cycles-worth of insts.")
243    executeMemoryWidth = Param.Unsigned(0,
244        "Width (and snap) in bytes of the data memory interface. (0 mean use"
245        " the system cacheLineSize)")
246    executeMaxAccessesInMemory = Param.Unsigned(2,
247        "Maximum number of concurrent accesses allowed to the memory system"
248        " from the dcache port")
249    executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2,
250        "Maximum number of stores that the store buffer can issue per cycle")
251    executeLSQRequestsQueueSize = Param.Unsigned(1,
252        "Size of LSQ requests queue (address translation queue)")
253    executeLSQTransfersQueueSize = Param.Unsigned(2,
254        "Size of LSQ transfers queue (memory transaction queue)")
255    executeLSQStoreBufferSize = Param.Unsigned(5,
256        "Size of LSQ store buffer")
257    executeBranchDelay = Param.Cycles(1,
258        "Delay from Execute deciding to branch and Fetch1 reacting"
259        " (1 means next cycle)")
260
261    executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(),
262        "FUlines for this processor")
263
264    executeSetTraceTimeOnCommit = Param.Bool(True,
265        "Set inst. trace times to be commit times")
266    executeSetTraceTimeOnIssue = Param.Bool(False,
267        "Set inst. trace times to be issue times")
268
269    executeAllowEarlyMemoryIssue = Param.Bool(True,
270        "Allow mem refs to be issued to the LSQ before reaching the head of"
271        " the in flight insts queue")
272
273    enableIdling = Param.Bool(True,
274        "Enable cycle skipping when the processor is idle\n");
275
276    branchPred = Param.BranchPredictor(TournamentBP(
277        numThreads = Parent.numThreads), "Branch Predictor")
278
279    def addCheckerCpu(self):
280        print("Checker not yet supported by MinorCPU")
281        exit(1)
282