MinorCPU.py revision 11567
1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Gabe Black 40# Nathan Binkert 41# Andrew Bardsley 42 43from m5.defines import buildEnv 44from m5.params import * 45from m5.proxy import * 46from m5.SimObject import SimObject 47from BaseCPU import BaseCPU 48from DummyChecker import DummyChecker 49from BranchPredictor import * 50from TimingExpr import TimingExpr 51 52from FuncUnit import OpClass 53 54class MinorOpClass(SimObject): 55 """Boxing of OpClass to get around build problems and provide a hook for 56 future additions to OpClass checks""" 57 58 type = 'MinorOpClass' 59 cxx_header = "cpu/minor/func_unit.hh" 60 61 opClass = Param.OpClass("op class to match") 62 63class MinorOpClassSet(SimObject): 64 """A set of matchable op classes""" 65 66 type = 'MinorOpClassSet' 67 cxx_header = "cpu/minor/func_unit.hh" 68 69 opClasses = VectorParam.MinorOpClass([], "op classes to be matched." 70 " An empty list means any class") 71 72class MinorFUTiming(SimObject): 73 type = 'MinorFUTiming' 74 cxx_header = "cpu/minor/func_unit.hh" 75 76 mask = Param.UInt64(0, "mask for testing ExtMachInst") 77 match = Param.UInt64(0, "match value for testing ExtMachInst:" 78 " (ext_mach_inst & mask) == match") 79 suppress = Param.Bool(False, "if true, this inst. is not executed by" 80 " this FU") 81 extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for" 82 " this inst.") 83 extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a" 84 " run-time evaluated expression") 85 extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard" 86 " retire time for this insts dest registers once it leaves the" 87 " functional unit. For mem refs, if this is 0, the result's time" 88 " is marked as unpredictable and no forwarding can take place.") 89 srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles" 90 " after inst. issue that each src reg can be available for this" 91 " inst. to issue") 92 opClasses = Param.MinorOpClassSet(MinorOpClassSet(), 93 "op classes to be considered for this decode. An empty set means any" 94 " class") 95 description = Param.String('', "description string of the decoding/inst." 96 " class") 97 98def minorMakeOpClassSet(op_classes): 99 """Make a MinorOpClassSet from a list of OpClass enum value strings""" 100 def boxOpClass(op_class): 101 return MinorOpClass(opClass=op_class) 102 103 return MinorOpClassSet(opClasses=map(boxOpClass, op_classes)) 104 105class MinorFU(SimObject): 106 type = 'MinorFU' 107 cxx_header = "cpu/minor/func_unit.hh" 108 109 opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations" 110 " allowed on this functional unit") 111 opLat = Param.Cycles(1, "latency in cycles") 112 issueLat = Param.Cycles(1, "cycles until another instruction can be" 113 " issued") 114 timings = VectorParam.MinorFUTiming([], "extra decoding rules") 115 116 cantForwardFromFUIndices = VectorParam.Unsigned([], 117 "list of FU indices from which this FU can't receive and early" 118 " (forwarded) result") 119 120class MinorFUPool(SimObject): 121 type = 'MinorFUPool' 122 cxx_header = "cpu/minor/func_unit.hh" 123 124 funcUnits = VectorParam.MinorFU("functional units") 125 126class MinorDefaultIntFU(MinorFU): 127 opClasses = minorMakeOpClassSet(['IntAlu']) 128 timings = [MinorFUTiming(description="Int", 129 srcRegsRelativeLats=[2])] 130 opLat = 3 131 132class MinorDefaultIntMulFU(MinorFU): 133 opClasses = minorMakeOpClassSet(['IntMult']) 134 timings = [MinorFUTiming(description='Mul', 135 srcRegsRelativeLats=[0])] 136 opLat = 3 137 138class MinorDefaultIntDivFU(MinorFU): 139 opClasses = minorMakeOpClassSet(['IntDiv']) 140 issueLat = 9 141 opLat = 9 142 143class MinorDefaultFloatSimdFU(MinorFU): 144 opClasses = minorMakeOpClassSet([ 145 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 146 'FloatSqrt', 147 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 148 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 149 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 150 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 151 'SimdFloatMultAcc', 'SimdFloatSqrt']) 152 timings = [MinorFUTiming(description='FloatSimd', 153 srcRegsRelativeLats=[2])] 154 opLat = 6 155 156class MinorDefaultMemFU(MinorFU): 157 opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite']) 158 timings = [MinorFUTiming(description='Mem', 159 srcRegsRelativeLats=[1], extraAssumedLat=2)] 160 opLat = 1 161 162class MinorDefaultMiscFU(MinorFU): 163 opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch']) 164 opLat = 1 165 166class MinorDefaultFUPool(MinorFUPool): 167 funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(), 168 MinorDefaultIntMulFU(), MinorDefaultIntDivFU(), 169 MinorDefaultFloatSimdFU(), MinorDefaultMemFU(), 170 MinorDefaultMiscFU()] 171 172class ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random'] 173 174class MinorCPU(BaseCPU): 175 type = 'MinorCPU' 176 cxx_header = "cpu/minor/cpu.hh" 177 178 @classmethod 179 def memory_mode(cls): 180 return 'timing' 181 182 @classmethod 183 def require_caches(cls): 184 return True 185 186 @classmethod 187 def support_take_over(cls): 188 return True 189 190 threadPolicy = Param.ThreadPolicy('RoundRobin', 191 "Thread scheduling policy") 192 fetch1FetchLimit = Param.Unsigned(1, 193 "Number of line fetches allowable in flight at once") 194 fetch1LineSnapWidth = Param.Unsigned(0, 195 "Fetch1 'line' fetch snap size in bytes" 196 " (0 means use system cache line size)") 197 fetch1LineWidth = Param.Unsigned(0, 198 "Fetch1 maximum fetch size in bytes (0 means use system cache" 199 " line size)") 200 fetch1ToFetch2ForwardDelay = Param.Cycles(1, 201 "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)") 202 fetch1ToFetch2BackwardDelay = Param.Cycles(1, 203 "Backward cycle delay from Fetch2 to Fetch1 for branch prediction" 204 " signalling (0 means in the same cycle, 1 mean the next cycle)") 205 206 fetch2InputBufferSize = Param.Unsigned(2, 207 "Size of input buffer to Fetch2 in cycles-worth of insts.") 208 fetch2ToDecodeForwardDelay = Param.Cycles(1, 209 "Forward cycle delay from Fetch2 to Decode (1 means next cycle)") 210 fetch2CycleInput = Param.Bool(True, 211 "Allow Fetch2 to cross input lines to generate full output each" 212 " cycle") 213 214 decodeInputBufferSize = Param.Unsigned(3, 215 "Size of input buffer to Decode in cycles-worth of insts.") 216 decodeToExecuteForwardDelay = Param.Cycles(1, 217 "Forward cycle delay from Decode to Execute (1 means next cycle)") 218 decodeInputWidth = Param.Unsigned(2, 219 "Width (in instructions) of input to Decode (and implicitly" 220 " Decode's own width)") 221 decodeCycleInput = Param.Bool(True, 222 "Allow Decode to pack instructions from more than one input cycle" 223 " to fill its output each cycle") 224 225 executeInputWidth = Param.Unsigned(2, 226 "Width (in instructions) of input to Execute") 227 executeCycleInput = Param.Bool(True, 228 "Allow Execute to use instructions from more than one input cycle" 229 " each cycle") 230 executeIssueLimit = Param.Unsigned(2, 231 "Number of issuable instructions in Execute each cycle") 232 executeMemoryIssueLimit = Param.Unsigned(1, 233 "Number of issuable memory instructions in Execute each cycle") 234 executeCommitLimit = Param.Unsigned(2, 235 "Number of committable instructions in Execute each cycle") 236 executeMemoryCommitLimit = Param.Unsigned(1, 237 "Number of committable memory references in Execute each cycle") 238 executeInputBufferSize = Param.Unsigned(7, 239 "Size of input buffer to Execute in cycles-worth of insts.") 240 executeMemoryWidth = Param.Unsigned(0, 241 "Width (and snap) in bytes of the data memory interface. (0 mean use" 242 " the system cacheLineSize)") 243 executeMaxAccessesInMemory = Param.Unsigned(2, 244 "Maximum number of concurrent accesses allowed to the memory system" 245 " from the dcache port") 246 executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2, 247 "Maximum number of stores that the store buffer can issue per cycle") 248 executeLSQRequestsQueueSize = Param.Unsigned(1, 249 "Size of LSQ requests queue (address translation queue)") 250 executeLSQTransfersQueueSize = Param.Unsigned(2, 251 "Size of LSQ transfers queue (memory transaction queue)") 252 executeLSQStoreBufferSize = Param.Unsigned(5, 253 "Size of LSQ store buffer") 254 executeBranchDelay = Param.Cycles(1, 255 "Delay from Execute deciding to branch and Fetch1 reacting" 256 " (1 means next cycle)") 257 258 executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(), 259 "FUlines for this processor") 260 261 executeSetTraceTimeOnCommit = Param.Bool(True, 262 "Set inst. trace times to be commit times") 263 executeSetTraceTimeOnIssue = Param.Bool(False, 264 "Set inst. trace times to be issue times") 265 266 executeAllowEarlyMemoryIssue = Param.Bool(True, 267 "Allow mem refs to be issued to the LSQ before reaching the head of" 268 " the in flight insts queue") 269 270 enableIdling = Param.Bool(True, 271 "Enable cycle skipping when the processor is idle\n"); 272 273 branchPred = Param.BranchPredictor(TournamentBP( 274 numThreads = Parent.numThreads), "Branch Predictor") 275 276 def addCheckerCpu(self): 277 print "Checker not yet supported by MinorCPU" 278 exit(1) 279