MinorCPU.py revision 13709
113559Snikos.nikoleris@arm.com# Copyright (c) 2012-2014,2018 ARM Limited 212109SRekai.GonzalezAlberquilla@arm.com# All rights reserved. 312109SRekai.GonzalezAlberquilla@arm.com# 412109SRekai.GonzalezAlberquilla@arm.com# The license below extends only to copyright in the software and shall 512109SRekai.GonzalezAlberquilla@arm.com# not be construed as granting a license to any other intellectual 612109SRekai.GonzalezAlberquilla@arm.com# property including but not limited to intellectual property relating 712109SRekai.GonzalezAlberquilla@arm.com# to a hardware implementation of the functionality of the software 812109SRekai.GonzalezAlberquilla@arm.com# licensed hereunder. You may use the software subject to the license 912109SRekai.GonzalezAlberquilla@arm.com# terms below provided that you ensure that this notice is replicated 1012109SRekai.GonzalezAlberquilla@arm.com# unmodified and in its entirety in all distributions of the software, 1112109SRekai.GonzalezAlberquilla@arm.com# modified or unmodified, in source code or in binary form. 1212109SRekai.GonzalezAlberquilla@arm.com# 134486Sbinkertn@umich.edu# Copyright (c) 2007 The Regents of The University of Michigan 144486Sbinkertn@umich.edu# All rights reserved. 154486Sbinkertn@umich.edu# 164486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 174486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 184486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 194486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 204486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 214486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 224486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 234486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 244486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 254486Sbinkertn@umich.edu# this software without specific prior written permission. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486Sbinkertn@umich.edu# 394486Sbinkertn@umich.edu# Authors: Gabe Black 404486Sbinkertn@umich.edu# Nathan Binkert 4112563Sgabeblack@google.com# Andrew Bardsley 4212563Sgabeblack@google.com 436654Snate@binkert.orgfrom __future__ import print_function 443102SN/A 453102SN/Afrom m5.defines import buildEnv 4613665Sandreas.sandberg@arm.comfrom m5.params import * 4713665Sandreas.sandberg@arm.comfrom m5.proxy import * 4813665Sandreas.sandberg@arm.comfrom m5.SimObject import SimObject 4913665Sandreas.sandberg@arm.comfrom m5.objects.BaseCPU import BaseCPU 5013665Sandreas.sandberg@arm.comfrom m5.objects.DummyChecker import DummyChecker 514486Sbinkertn@umich.edufrom m5.objects.BranchPredictor import * 5213559Snikos.nikoleris@arm.comfrom m5.objects.TimingExpr import TimingExpr 5313559Snikos.nikoleris@arm.com 5413559Snikos.nikoleris@arm.comfrom m5.objects.FuncUnit import OpClass 5513560Snikos.nikoleris@arm.com 5613560Snikos.nikoleris@arm.comclass MinorOpClass(SimObject): 5713560Snikos.nikoleris@arm.com """Boxing of OpClass to get around build problems and provide a hook for 5813563Snikos.nikoleris@arm.com future additions to OpClass checks""" 5913563Snikos.nikoleris@arm.com 6013563Snikos.nikoleris@arm.com type = 'MinorOpClass' 612817SN/A cxx_header = "cpu/minor/func_unit.hh" 622817SN/A 639341SAndreas.Sandberg@arm.com opClass = Param.OpClass("op class to match") 649341SAndreas.Sandberg@arm.com 659518SAndreas.Sandberg@ARM.comclass MinorOpClassSet(SimObject): 669518SAndreas.Sandberg@ARM.com """A set of matchable op classes""" 679518SAndreas.Sandberg@ARM.com 689518SAndreas.Sandberg@ARM.com type = 'MinorOpClassSet' 699518SAndreas.Sandberg@ARM.com cxx_header = "cpu/minor/func_unit.hh" 709518SAndreas.Sandberg@ARM.com 719518SAndreas.Sandberg@ARM.com opClasses = VectorParam.MinorOpClass([], "op classes to be matched." 729518SAndreas.Sandberg@ARM.com " An empty list means any class") 739518SAndreas.Sandberg@ARM.com 749518SAndreas.Sandberg@ARM.comclass MinorFUTiming(SimObject): 759518SAndreas.Sandberg@ARM.com type = 'MinorFUTiming' 769518SAndreas.Sandberg@ARM.com cxx_header = "cpu/minor/func_unit.hh" 772932SN/A 781681SN/A mask = Param.UInt64(0, "mask for testing ExtMachInst") 7911780Sarthur.perais@inria.fr match = Param.UInt64(0, "match value for testing ExtMachInst:" 8011780Sarthur.perais@inria.fr " (ext_mach_inst & mask) == match") 811681SN/A suppress = Param.Bool(False, "if true, this inst. is not executed by" 829184Sandreas.hansson@arm.com " this FU") 839184Sandreas.hansson@arm.com extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for" 849184Sandreas.hansson@arm.com " this inst.") 859184Sandreas.hansson@arm.com extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a" 869184Sandreas.hansson@arm.com " run-time evaluated expression") 872932SN/A extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard" 889982Satgutier@umich.edu " retire time for this insts dest registers once it leaves the" 8910331Smitch.hayenga@arm.com " functional unit. For mem refs, if this is 0, the result's time" 9010331Smitch.hayenga@arm.com " is marked as unpredictable and no forwarding can take place.") 912932SN/A srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles" 929184Sandreas.hansson@arm.com " after inst. issue that each src reg can be available for this" 939184Sandreas.hansson@arm.com " inst. to issue") 949184Sandreas.hansson@arm.com opClasses = Param.MinorOpClassSet(MinorOpClassSet(), 959184Sandreas.hansson@arm.com "op classes to be considered for this decode. An empty set means any" 969184Sandreas.hansson@arm.com " class") 972932SN/A description = Param.String('', "description string of the decoding/inst." 981681SN/A " class") 999184Sandreas.hansson@arm.com 1009184Sandreas.hansson@arm.comdef minorMakeOpClassSet(op_classes): 1019184Sandreas.hansson@arm.com """Make a MinorOpClassSet from a list of OpClass enum value strings""" 1029184Sandreas.hansson@arm.com def boxOpClass(op_class): 1032932SN/A return MinorOpClass(opClass=op_class) 1041681SN/A 1059184Sandreas.hansson@arm.com return MinorOpClassSet(opClasses=[ boxOpClass(o) for o in op_classes ]) 1062932SN/A 1079184Sandreas.hansson@arm.comclass MinorFU(SimObject): 1082932SN/A type = 'MinorFU' 1099184Sandreas.hansson@arm.com cxx_header = "cpu/minor/func_unit.hh" 1102932SN/A 1112932SN/A opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations" 1122932SN/A " allowed on this functional unit") 1132932SN/A opLat = Param.Cycles(1, "latency in cycles") 1143223SN/A issueLat = Param.Cycles(1, "cycles until another instruction can be" 1152932SN/A " issued") 1169184Sandreas.hansson@arm.com timings = VectorParam.MinorFUTiming([], "extra decoding rules") 1171681SN/A 1189184Sandreas.hansson@arm.com cantForwardFromFUIndices = VectorParam.Unsigned([], 1192932SN/A "list of FU indices from which this FU can't receive and early" 1202932SN/A " (forwarded) result") 1219184Sandreas.hansson@arm.com 1229184Sandreas.hansson@arm.comclass MinorFUPool(SimObject): 1231681SN/A type = 'MinorFUPool' 1242932SN/A cxx_header = "cpu/minor/func_unit.hh" 1252932SN/A 1261681SN/A funcUnits = VectorParam.MinorFU("functional units") 1272932SN/A 1282932SN/Aclass MinorDefaultIntFU(MinorFU): 1298199SAli.Saidi@ARM.com opClasses = minorMakeOpClassSet(['IntAlu']) 1308199SAli.Saidi@ARM.com timings = [MinorFUTiming(description="Int", 1318199SAli.Saidi@ARM.com srcRegsRelativeLats=[2])] 1328519SAli.Saidi@ARM.com opLat = 3 1338519SAli.Saidi@ARM.com 1342932SN/Aclass MinorDefaultIntMulFU(MinorFU): 1352932SN/A opClasses = minorMakeOpClassSet(['IntMult']) 1361681SN/A timings = [MinorFUTiming(description='Mul', 1372932SN/A srcRegsRelativeLats=[0])] 1381681SN/A opLat = 3 1392932SN/A 1402932SN/Aclass MinorDefaultIntDivFU(MinorFU): 1412932SN/A opClasses = minorMakeOpClassSet(['IntDiv']) 1429921Syasuko.eckert@amd.com issueLat = 9 1439921Syasuko.eckert@amd.com opLat = 9 14410338SCurtis.Dunham@arm.com 1459921Syasuko.eckert@amd.comclass MinorDefaultFloatSimdFU(MinorFU): 1469921Syasuko.eckert@amd.com opClasses = minorMakeOpClassSet([ 1479921Syasuko.eckert@amd.com 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult', 1489921Syasuko.eckert@amd.com 'FloatMultAcc', 'FloatDiv', 'FloatSqrt', 1499921Syasuko.eckert@amd.com 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 1509921Syasuko.eckert@amd.com 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 1519921Syasuko.eckert@amd.com 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 15212109SRekai.GonzalezAlberquilla@arm.com 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 15312109SRekai.GonzalezAlberquilla@arm.com 'SimdFloatMultAcc', 'SimdFloatSqrt', 'SimdAes', 'SimdAesMix', 15413610Sgiacomo.gabrielli@arm.com 'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash', 15513610Sgiacomo.gabrielli@arm.com 'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3']) 1569921Syasuko.eckert@amd.com timings = [MinorFUTiming(description='FloatSimd', 1579921Syasuko.eckert@amd.com srcRegsRelativeLats=[2])] 1582932SN/A opLat = 6 1592932SN/A 1601681SN/Aclass MinorDefaultMemFU(MinorFU): 1614597Sbinkertn@umich.edu opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead', 16213559Snikos.nikoleris@arm.com 'FloatMemWrite']) 16313560Snikos.nikoleris@arm.com timings = [MinorFUTiming(description='Mem', 16413560Snikos.nikoleris@arm.com srcRegsRelativeLats=[1], extraAssumedLat=2)] 1654597Sbinkertn@umich.edu opLat = 1 16613561Snikos.nikoleris@arm.com 16713561Snikos.nikoleris@arm.comclass MinorDefaultMiscFU(MinorFU): 1684597Sbinkertn@umich.edu opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch']) 16913562Snikos.nikoleris@arm.com opLat = 1 17013562Snikos.nikoleris@arm.com 1714597Sbinkertn@umich.educlass MinorDefaultFUPool(MinorFUPool): 17213563Snikos.nikoleris@arm.com funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(), 1734303SN/A MinorDefaultIntMulFU(), MinorDefaultIntDivFU(), 17410785Sgope@wisc.edu MinorDefaultFloatSimdFU(), MinorDefaultMemFU(), 1759849Sandreas.hansson@arm.com MinorDefaultMiscFU()] 1769849Sandreas.hansson@arm.com 1778727Snilay@cs.wisc.educlass ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random'] 1788727Snilay@cs.wisc.edu 1798887Sgeoffrey.blake@arm.comclass MinorCPU(BaseCPU): 1808887Sgeoffrey.blake@arm.com type = 'MinorCPU' 1818887Sgeoffrey.blake@arm.com cxx_header = "cpu/minor/cpu.hh" 18213665Sandreas.sandberg@arm.com 1838887Sgeoffrey.blake@arm.com @classmethod 1848887Sgeoffrey.blake@arm.com def memory_mode(cls): 1858887Sgeoffrey.blake@arm.com return 'timing' 1868887Sgeoffrey.blake@arm.com 1878887Sgeoffrey.blake@arm.com @classmethod 1888887Sgeoffrey.blake@arm.com def require_caches(cls): 1898887Sgeoffrey.blake@arm.com return True 1909132Satgutier@umich.edu 1918887Sgeoffrey.blake@arm.com @classmethod 1928887Sgeoffrey.blake@arm.com def support_take_over(cls): 19312563Sgabeblack@google.com return True 1948887Sgeoffrey.blake@arm.com 195 threadPolicy = Param.ThreadPolicy('RoundRobin', 196 "Thread scheduling policy") 197 fetch1FetchLimit = Param.Unsigned(1, 198 "Number of line fetches allowable in flight at once") 199 fetch1LineSnapWidth = Param.Unsigned(0, 200 "Fetch1 'line' fetch snap size in bytes" 201 " (0 means use system cache line size)") 202 fetch1LineWidth = Param.Unsigned(0, 203 "Fetch1 maximum fetch size in bytes (0 means use system cache" 204 " line size)") 205 fetch1ToFetch2ForwardDelay = Param.Cycles(1, 206 "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)") 207 fetch1ToFetch2BackwardDelay = Param.Cycles(1, 208 "Backward cycle delay from Fetch2 to Fetch1 for branch prediction" 209 " signalling (0 means in the same cycle, 1 mean the next cycle)") 210 211 fetch2InputBufferSize = Param.Unsigned(2, 212 "Size of input buffer to Fetch2 in cycles-worth of insts.") 213 fetch2ToDecodeForwardDelay = Param.Cycles(1, 214 "Forward cycle delay from Fetch2 to Decode (1 means next cycle)") 215 fetch2CycleInput = Param.Bool(True, 216 "Allow Fetch2 to cross input lines to generate full output each" 217 " cycle") 218 219 decodeInputBufferSize = Param.Unsigned(3, 220 "Size of input buffer to Decode in cycles-worth of insts.") 221 decodeToExecuteForwardDelay = Param.Cycles(1, 222 "Forward cycle delay from Decode to Execute (1 means next cycle)") 223 decodeInputWidth = Param.Unsigned(2, 224 "Width (in instructions) of input to Decode (and implicitly" 225 " Decode's own width)") 226 decodeCycleInput = Param.Bool(True, 227 "Allow Decode to pack instructions from more than one input cycle" 228 " to fill its output each cycle") 229 230 executeInputWidth = Param.Unsigned(2, 231 "Width (in instructions) of input to Execute") 232 executeCycleInput = Param.Bool(True, 233 "Allow Execute to use instructions from more than one input cycle" 234 " each cycle") 235 executeIssueLimit = Param.Unsigned(2, 236 "Number of issuable instructions in Execute each cycle") 237 executeMemoryIssueLimit = Param.Unsigned(1, 238 "Number of issuable memory instructions in Execute each cycle") 239 executeCommitLimit = Param.Unsigned(2, 240 "Number of committable instructions in Execute each cycle") 241 executeMemoryCommitLimit = Param.Unsigned(1, 242 "Number of committable memory references in Execute each cycle") 243 executeInputBufferSize = Param.Unsigned(7, 244 "Size of input buffer to Execute in cycles-worth of insts.") 245 executeMemoryWidth = Param.Unsigned(0, 246 "Width (and snap) in bytes of the data memory interface. (0 mean use" 247 " the system cacheLineSize)") 248 executeMaxAccessesInMemory = Param.Unsigned(2, 249 "Maximum number of concurrent accesses allowed to the memory system" 250 " from the dcache port") 251 executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2, 252 "Maximum number of stores that the store buffer can issue per cycle") 253 executeLSQRequestsQueueSize = Param.Unsigned(1, 254 "Size of LSQ requests queue (address translation queue)") 255 executeLSQTransfersQueueSize = Param.Unsigned(2, 256 "Size of LSQ transfers queue (memory transaction queue)") 257 executeLSQStoreBufferSize = Param.Unsigned(5, 258 "Size of LSQ store buffer") 259 executeBranchDelay = Param.Cycles(1, 260 "Delay from Execute deciding to branch and Fetch1 reacting" 261 " (1 means next cycle)") 262 263 executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(), 264 "FUlines for this processor") 265 266 executeSetTraceTimeOnCommit = Param.Bool(True, 267 "Set inst. trace times to be commit times") 268 executeSetTraceTimeOnIssue = Param.Bool(False, 269 "Set inst. trace times to be issue times") 270 271 executeAllowEarlyMemoryIssue = Param.Bool(True, 272 "Allow mem refs to be issued to the LSQ before reaching the head of" 273 " the in flight insts queue") 274 275 enableIdling = Param.Bool(True, 276 "Enable cycle skipping when the processor is idle\n"); 277 278 branchPred = Param.BranchPredictor(TournamentBP( 279 numThreads = Parent.numThreads), "Branch Predictor") 280 281 def addCheckerCpu(self): 282 print("Checker not yet supported by MinorCPU") 283 exit(1) 284