MinorCPU.py revision 13665
113558Snikos.nikoleris@arm.com# Copyright (c) 2012-2014,2018 ARM Limited 28839Sandreas.hansson@arm.com# All rights reserved. 38839Sandreas.hansson@arm.com# 48839Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58839Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68839Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78839Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88839Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98839Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108839Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118839Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128839Sandreas.hansson@arm.com# 133101Sstever@eecs.umich.edu# Copyright (c) 2007 The Regents of The University of Michigan 148579Ssteve.reinhardt@amd.com# All rights reserved. 153101Sstever@eecs.umich.edu# 163101Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173101Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 183101Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193101Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203101Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213101Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223101Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233101Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243101Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253101Sstever@eecs.umich.edu# this software without specific prior written permission. 263101Sstever@eecs.umich.edu# 273101Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283101Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293101Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303101Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313101Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323101Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333101Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343101Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353101Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363101Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373101Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383101Sstever@eecs.umich.edu# 393101Sstever@eecs.umich.edu# Authors: Gabe Black 403101Sstever@eecs.umich.edu# Nathan Binkert 413101Sstever@eecs.umich.edu# Andrew Bardsley 427778Sgblack@eecs.umich.edu 438839Sandreas.hansson@arm.comfrom __future__ import print_function 443101Sstever@eecs.umich.edu 453101Sstever@eecs.umich.edufrom m5.defines import buildEnv 463101Sstever@eecs.umich.edufrom m5.params import * 473101Sstever@eecs.umich.edufrom m5.proxy import * 483101Sstever@eecs.umich.edufrom m5.SimObject import SimObject 493101Sstever@eecs.umich.edufrom m5.objects.BaseCPU import BaseCPU 503101Sstever@eecs.umich.edufrom m5.objects.DummyChecker import DummyChecker 513101Sstever@eecs.umich.edufrom m5.objects.BranchPredictor import * 523101Sstever@eecs.umich.edufrom m5.objects.TimingExpr import TimingExpr 533101Sstever@eecs.umich.edu 543101Sstever@eecs.umich.edufrom m5.objects.FuncUnit import OpClass 553101Sstever@eecs.umich.edu 563101Sstever@eecs.umich.educlass MinorOpClass(SimObject): 573101Sstever@eecs.umich.edu """Boxing of OpClass to get around build problems and provide a hook for 583101Sstever@eecs.umich.edu future additions to OpClass checks""" 593101Sstever@eecs.umich.edu 603101Sstever@eecs.umich.edu type = 'MinorOpClass' 613101Sstever@eecs.umich.edu cxx_header = "cpu/minor/func_unit.hh" 6212563Sgabeblack@google.com 6312563Sgabeblack@google.com opClass = Param.OpClass("op class to match") 643885Sbinkertn@umich.edu 653885Sbinkertn@umich.educlass MinorOpClassSet(SimObject): 664762Snate@binkert.org """A set of matchable op classes""" 673885Sbinkertn@umich.edu 683885Sbinkertn@umich.edu type = 'MinorOpClassSet' 697528Ssteve.reinhardt@amd.com cxx_header = "cpu/minor/func_unit.hh" 703885Sbinkertn@umich.edu 714380Sbinkertn@umich.edu opClasses = VectorParam.MinorOpClass([], "op classes to be matched." 724167Sbinkertn@umich.edu " An empty list means any class") 733102Sstever@eecs.umich.edu 743101Sstever@eecs.umich.educlass MinorFUTiming(SimObject): 754762Snate@binkert.org type = 'MinorFUTiming' 764762Snate@binkert.org cxx_header = "cpu/minor/func_unit.hh" 774762Snate@binkert.org 784762Snate@binkert.org mask = Param.UInt64(0, "mask for testing ExtMachInst") 794762Snate@binkert.org match = Param.UInt64(0, "match value for testing ExtMachInst:" 804762Snate@binkert.org " (ext_mach_inst & mask) == match") 814762Snate@binkert.org suppress = Param.Bool(False, "if true, this inst. is not executed by" 824762Snate@binkert.org " this FU") 834762Snate@binkert.org extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for" 845033Smilesck@eecs.umich.edu " this inst.") 855033Smilesck@eecs.umich.edu extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a" 865033Smilesck@eecs.umich.edu " run-time evaluated expression") 875033Smilesck@eecs.umich.edu extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard" 885033Smilesck@eecs.umich.edu " retire time for this insts dest registers once it leaves the" 895033Smilesck@eecs.umich.edu " functional unit. For mem refs, if this is 0, the result's time" 905033Smilesck@eecs.umich.edu " is marked as unpredictable and no forwarding can take place.") 915033Smilesck@eecs.umich.edu srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles" 925033Smilesck@eecs.umich.edu " after inst. issue that each src reg can be available for this" 935033Smilesck@eecs.umich.edu " inst. to issue") 943101Sstever@eecs.umich.edu opClasses = Param.MinorOpClassSet(MinorOpClassSet(), 953101Sstever@eecs.umich.edu "op classes to be considered for this decode. An empty set means any" 963101Sstever@eecs.umich.edu " class") 975033Smilesck@eecs.umich.edu description = Param.String('', "description string of the decoding/inst." 9810267SGeoffrey.Blake@arm.com " class") 998596Ssteve.reinhardt@amd.com 1008596Ssteve.reinhardt@amd.comdef minorMakeOpClassSet(op_classes): 1018596Ssteve.reinhardt@amd.com """Make a MinorOpClassSet from a list of OpClass enum value strings""" 1028596Ssteve.reinhardt@amd.com def boxOpClass(op_class): 1037673Snate@binkert.org return MinorOpClass(opClass=op_class) 1047673Snate@binkert.org 1057673Snate@binkert.org return MinorOpClassSet(opClasses=map(boxOpClass, op_classes)) 1067673Snate@binkert.org 10711988Sandreas.sandberg@arm.comclass MinorFU(SimObject): 10811988Sandreas.sandberg@arm.com type = 'MinorFU' 10911988Sandreas.sandberg@arm.com cxx_header = "cpu/minor/func_unit.hh" 11011988Sandreas.sandberg@arm.com 1113101Sstever@eecs.umich.edu opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations" 1123101Sstever@eecs.umich.edu " allowed on this functional unit") 1133101Sstever@eecs.umich.edu opLat = Param.Cycles(1, "latency in cycles") 1143101Sstever@eecs.umich.edu issueLat = Param.Cycles(1, "cycles until another instruction can be" 1153101Sstever@eecs.umich.edu " issued") 11610380SAndrew.Bardsley@arm.com timings = VectorParam.MinorFUTiming([], "extra decoding rules") 11710380SAndrew.Bardsley@arm.com 11810380SAndrew.Bardsley@arm.com cantForwardFromFUIndices = VectorParam.Unsigned([], 11910380SAndrew.Bardsley@arm.com "list of FU indices from which this FU can't receive and early" 12010380SAndrew.Bardsley@arm.com " (forwarded) result") 12110380SAndrew.Bardsley@arm.com 12210458Sandreas.hansson@arm.comclass MinorFUPool(SimObject): 12310458Sandreas.hansson@arm.com type = 'MinorFUPool' 12410458Sandreas.hansson@arm.com cxx_header = "cpu/minor/func_unit.hh" 12510458Sandreas.hansson@arm.com 12610458Sandreas.hansson@arm.com funcUnits = VectorParam.MinorFU("functional units") 12710458Sandreas.hansson@arm.com 12810458Sandreas.hansson@arm.comclass MinorDefaultIntFU(MinorFU): 12910458Sandreas.hansson@arm.com opClasses = minorMakeOpClassSet(['IntAlu']) 13010458Sandreas.hansson@arm.com timings = [MinorFUTiming(description="Int", 13110458Sandreas.hansson@arm.com srcRegsRelativeLats=[2])] 13210458Sandreas.hansson@arm.com opLat = 3 13310458Sandreas.hansson@arm.com 1343101Sstever@eecs.umich.educlass MinorDefaultIntMulFU(MinorFU): 1353101Sstever@eecs.umich.edu opClasses = minorMakeOpClassSet(['IntMult']) 1363101Sstever@eecs.umich.edu timings = [MinorFUTiming(description='Mul', 1373101Sstever@eecs.umich.edu srcRegsRelativeLats=[0])] 1383101Sstever@eecs.umich.edu opLat = 3 13910267SGeoffrey.Blake@arm.com 14010267SGeoffrey.Blake@arm.comclass MinorDefaultIntDivFU(MinorFU): 14110267SGeoffrey.Blake@arm.com opClasses = minorMakeOpClassSet(['IntDiv']) 14210267SGeoffrey.Blake@arm.com issueLat = 9 1433101Sstever@eecs.umich.edu opLat = 9 1443101Sstever@eecs.umich.edu 1453101Sstever@eecs.umich.educlass MinorDefaultFloatSimdFU(MinorFU): 1463101Sstever@eecs.umich.edu opClasses = minorMakeOpClassSet([ 1473101Sstever@eecs.umich.edu 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult', 1483101Sstever@eecs.umich.edu 'FloatMultAcc', 'FloatDiv', 'FloatSqrt', 1493101Sstever@eecs.umich.edu 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 1503101Sstever@eecs.umich.edu 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 1513101Sstever@eecs.umich.edu 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 1523101Sstever@eecs.umich.edu 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 1533101Sstever@eecs.umich.edu 'SimdFloatMultAcc', 'SimdFloatSqrt', 'SimdAes', 'SimdAesMix', 1543101Sstever@eecs.umich.edu 'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash', 1553101Sstever@eecs.umich.edu 'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3']) 1563101Sstever@eecs.umich.edu timings = [MinorFUTiming(description='FloatSimd', 1573101Sstever@eecs.umich.edu srcRegsRelativeLats=[2])] 15813663Sandreas.sandberg@arm.com opLat = 6 1593101Sstever@eecs.umich.edu 16013675Sandreas.sandberg@arm.comclass MinorDefaultMemFU(MinorFU): 1613101Sstever@eecs.umich.edu opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead', 1623101Sstever@eecs.umich.edu 'FloatMemWrite']) 1633101Sstever@eecs.umich.edu timings = [MinorFUTiming(description='Mem', 1643101Sstever@eecs.umich.edu srcRegsRelativeLats=[1], extraAssumedLat=2)] 16513675Sandreas.sandberg@arm.com opLat = 1 1663101Sstever@eecs.umich.edu 1673101Sstever@eecs.umich.educlass MinorDefaultMiscFU(MinorFU): 1683101Sstever@eecs.umich.edu opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch']) 1693101Sstever@eecs.umich.edu opLat = 1 1703101Sstever@eecs.umich.edu 17113663Sandreas.sandberg@arm.comclass MinorDefaultFUPool(MinorFUPool): 1723101Sstever@eecs.umich.edu funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(), 1733101Sstever@eecs.umich.edu MinorDefaultIntMulFU(), MinorDefaultIntDivFU(), 17413663Sandreas.sandberg@arm.com MinorDefaultFloatSimdFU(), MinorDefaultMemFU(), 1753101Sstever@eecs.umich.edu MinorDefaultMiscFU()] 1763101Sstever@eecs.umich.edu 1773101Sstever@eecs.umich.educlass ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random'] 1785033Smilesck@eecs.umich.edu 1796656Snate@binkert.orgclass MinorCPU(BaseCPU): 1805033Smilesck@eecs.umich.edu type = 'MinorCPU' 1815033Smilesck@eecs.umich.edu cxx_header = "cpu/minor/cpu.hh" 1825033Smilesck@eecs.umich.edu 18313663Sandreas.sandberg@arm.com @classmethod 18413663Sandreas.sandberg@arm.com def memory_mode(cls): 1853101Sstever@eecs.umich.edu return 'timing' 18610267SGeoffrey.Blake@arm.com 18710267SGeoffrey.Blake@arm.com @classmethod 18810267SGeoffrey.Blake@arm.com def require_caches(cls): 18910267SGeoffrey.Blake@arm.com return True 19010267SGeoffrey.Blake@arm.com 19110267SGeoffrey.Blake@arm.com @classmethod 19210267SGeoffrey.Blake@arm.com def support_take_over(cls): 19310267SGeoffrey.Blake@arm.com return True 19410267SGeoffrey.Blake@arm.com 19510267SGeoffrey.Blake@arm.com threadPolicy = Param.ThreadPolicy('RoundRobin', 19610267SGeoffrey.Blake@arm.com "Thread scheduling policy") 19710267SGeoffrey.Blake@arm.com fetch1FetchLimit = Param.Unsigned(1, 19810267SGeoffrey.Blake@arm.com "Number of line fetches allowable in flight at once") 1993101Sstever@eecs.umich.edu fetch1LineSnapWidth = Param.Unsigned(0, 2003101Sstever@eecs.umich.edu "Fetch1 'line' fetch snap size in bytes" 2013101Sstever@eecs.umich.edu " (0 means use system cache line size)") 2023101Sstever@eecs.umich.edu fetch1LineWidth = Param.Unsigned(0, 2033101Sstever@eecs.umich.edu "Fetch1 maximum fetch size in bytes (0 means use system cache" 2043101Sstever@eecs.umich.edu " line size)") 2053101Sstever@eecs.umich.edu fetch1ToFetch2ForwardDelay = Param.Cycles(1, 2063101Sstever@eecs.umich.edu "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)") 2073101Sstever@eecs.umich.edu fetch1ToFetch2BackwardDelay = Param.Cycles(1, 2083101Sstever@eecs.umich.edu "Backward cycle delay from Fetch2 to Fetch1 for branch prediction" 2093102Sstever@eecs.umich.edu " signalling (0 means in the same cycle, 1 mean the next cycle)") 2103101Sstever@eecs.umich.edu 2113101Sstever@eecs.umich.edu fetch2InputBufferSize = Param.Unsigned(2, 2123101Sstever@eecs.umich.edu "Size of input buffer to Fetch2 in cycles-worth of insts.") 21310267SGeoffrey.Blake@arm.com fetch2ToDecodeForwardDelay = Param.Cycles(1, 21410267SGeoffrey.Blake@arm.com "Forward cycle delay from Fetch2 to Decode (1 means next cycle)") 21510267SGeoffrey.Blake@arm.com fetch2CycleInput = Param.Bool(True, 21610267SGeoffrey.Blake@arm.com "Allow Fetch2 to cross input lines to generate full output each" 21710267SGeoffrey.Blake@arm.com " cycle") 21810267SGeoffrey.Blake@arm.com 21910267SGeoffrey.Blake@arm.com decodeInputBufferSize = Param.Unsigned(3, 2207673Snate@binkert.org "Size of input buffer to Decode in cycles-worth of insts.") 2218607Sgblack@eecs.umich.edu decodeToExecuteForwardDelay = Param.Cycles(1, 2227673Snate@binkert.org "Forward cycle delay from Decode to Execute (1 means next cycle)") 2233101Sstever@eecs.umich.edu decodeInputWidth = Param.Unsigned(2, 22411988Sandreas.sandberg@arm.com "Width (in instructions) of input to Decode (and implicitly" 22511988Sandreas.sandberg@arm.com " Decode's own width)") 22611988Sandreas.sandberg@arm.com decodeCycleInput = Param.Bool(True, 2277673Snate@binkert.org "Allow Decode to pack instructions from more than one input cycle" 2287673Snate@binkert.org " to fill its output each cycle") 2293101Sstever@eecs.umich.edu 2303101Sstever@eecs.umich.edu executeInputWidth = Param.Unsigned(2, 2313101Sstever@eecs.umich.edu "Width (in instructions) of input to Execute") 2323101Sstever@eecs.umich.edu executeCycleInput = Param.Bool(True, 2333101Sstever@eecs.umich.edu "Allow Execute to use instructions from more than one input cycle" 2343101Sstever@eecs.umich.edu " each cycle") 2355033Smilesck@eecs.umich.edu executeIssueLimit = Param.Unsigned(2, 2365475Snate@binkert.org "Number of issuable instructions in Execute each cycle") 23713663Sandreas.sandberg@arm.com executeMemoryIssueLimit = Param.Unsigned(1, 23813663Sandreas.sandberg@arm.com "Number of issuable memory instructions in Execute each cycle") 2395475Snate@binkert.org executeCommitLimit = Param.Unsigned(2, 24010380SAndrew.Bardsley@arm.com "Number of committable instructions in Execute each cycle") 24110380SAndrew.Bardsley@arm.com executeMemoryCommitLimit = Param.Unsigned(1, 24210380SAndrew.Bardsley@arm.com "Number of committable memory references in Execute each cycle") 2433101Sstever@eecs.umich.edu executeInputBufferSize = Param.Unsigned(7, 2443101Sstever@eecs.umich.edu "Size of input buffer to Execute in cycles-worth of insts.") 2453101Sstever@eecs.umich.edu executeMemoryWidth = Param.Unsigned(0, 2464762Snate@binkert.org "Width (and snap) in bytes of the data memory interface. (0 mean use" 2474762Snate@binkert.org " the system cacheLineSize)") 2484762Snate@binkert.org executeMaxAccessesInMemory = Param.Unsigned(2, 2493101Sstever@eecs.umich.edu "Maximum number of concurrent accesses allowed to the memory system" 25012050Snikos.nikoleris@arm.com " from the dcache port") 25112050Snikos.nikoleris@arm.com executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2, 25212050Snikos.nikoleris@arm.com "Maximum number of stores that the store buffer can issue per cycle") 2538459SAli.Saidi@ARM.com executeLSQRequestsQueueSize = Param.Unsigned(1, 2548459SAli.Saidi@ARM.com "Size of LSQ requests queue (address translation queue)") 25512050Snikos.nikoleris@arm.com executeLSQTransfersQueueSize = Param.Unsigned(2, 2563101Sstever@eecs.umich.edu "Size of LSQ transfers queue (memory transaction queue)") 2577528Ssteve.reinhardt@amd.com executeLSQStoreBufferSize = Param.Unsigned(5, 2587528Ssteve.reinhardt@amd.com "Size of LSQ store buffer") 2597528Ssteve.reinhardt@amd.com executeBranchDelay = Param.Cycles(1, 2607528Ssteve.reinhardt@amd.com "Delay from Execute deciding to branch and Fetch1 reacting" 2617528Ssteve.reinhardt@amd.com " (1 means next cycle)") 2627528Ssteve.reinhardt@amd.com 2633101Sstever@eecs.umich.edu executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(), 2647528Ssteve.reinhardt@amd.com "FUlines for this processor") 2657528Ssteve.reinhardt@amd.com 2667528Ssteve.reinhardt@amd.com executeSetTraceTimeOnCommit = Param.Bool(True, 2677528Ssteve.reinhardt@amd.com "Set inst. trace times to be commit times") 2687528Ssteve.reinhardt@amd.com executeSetTraceTimeOnIssue = Param.Bool(False, 2697528Ssteve.reinhardt@amd.com "Set inst. trace times to be issue times") 2707528Ssteve.reinhardt@amd.com 2717528Ssteve.reinhardt@amd.com executeAllowEarlyMemoryIssue = Param.Bool(True, 2727528Ssteve.reinhardt@amd.com "Allow mem refs to be issued to the LSQ before reaching the head of" 2737528Ssteve.reinhardt@amd.com " the in flight insts queue") 2748321Ssteve.reinhardt@amd.com 27512194Sgabeblack@google.com enableIdling = Param.Bool(True, 2767528Ssteve.reinhardt@amd.com "Enable cycle skipping when the processor is idle\n"); 2777528Ssteve.reinhardt@amd.com 2787528Ssteve.reinhardt@amd.com branchPred = Param.BranchPredictor(TournamentBP( 2797528Ssteve.reinhardt@amd.com numThreads = Parent.numThreads), "Branch Predictor") 2807528Ssteve.reinhardt@amd.com 2817528Ssteve.reinhardt@amd.com def addCheckerCpu(self): 2827528Ssteve.reinhardt@amd.com print("Checker not yet supported by MinorCPU") 2837528Ssteve.reinhardt@amd.com exit(1) 2847528Ssteve.reinhardt@amd.com