MinorCPU.py revision 12563
18706Sandreas.hansson@arm.com# Copyright (c) 2012-2014 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2007 The Regents of The University of Michigan 145323Sgblack@eecs.umich.edu# All rights reserved. 152934Sktlim@umich.edu# 162934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 172934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 182934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 192934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 202934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 212934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 222934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 232934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 242934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 252934Sktlim@umich.edu# this software without specific prior written permission. 262934Sktlim@umich.edu# 272934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382934Sktlim@umich.edu# 392934Sktlim@umich.edu# Authors: Gabe Black 402934Sktlim@umich.edu# Nathan Binkert 412934Sktlim@umich.edu# Andrew Bardsley 422934Sktlim@umich.edu 432995Ssaidi@eecs.umich.edufrom __future__ import print_function 448528SAli.Saidi@ARM.com 452934Sktlim@umich.edufrom m5.defines import buildEnv 462934Sktlim@umich.edufrom m5.params import * 472934Sktlim@umich.edufrom m5.proxy import * 482934Sktlim@umich.edufrom m5.SimObject import SimObject 492934Sktlim@umich.edufrom BaseCPU import BaseCPU 502934Sktlim@umich.edufrom DummyChecker import DummyChecker 512934Sktlim@umich.edufrom BranchPredictor import * 522934Sktlim@umich.edufrom TimingExpr import TimingExpr 539036Sandreas.hansson@arm.com 546122SSteve.Reinhardt@amd.comfrom FuncUnit import OpClass 556122SSteve.Reinhardt@amd.com 566122SSteve.Reinhardt@amd.comclass MinorOpClass(SimObject): 576122SSteve.Reinhardt@amd.com """Boxing of OpClass to get around build problems and provide a hook for 584520Ssaidi@eecs.umich.edu future additions to OpClass checks""" 598713Sandreas.hansson@arm.com 604520Ssaidi@eecs.umich.edu type = 'MinorOpClass' 614982Ssaidi@eecs.umich.edu cxx_header = "cpu/minor/func_unit.hh" 624520Ssaidi@eecs.umich.edu 634520Ssaidi@eecs.umich.edu opClass = Param.OpClass("op class to match") 642934Sktlim@umich.edu 652934Sktlim@umich.educlass MinorOpClassSet(SimObject): 663005Sstever@eecs.umich.edu """A set of matchable op classes""" 673005Sstever@eecs.umich.edu 683304Sstever@eecs.umich.edu type = 'MinorOpClassSet' 692995Ssaidi@eecs.umich.edu cxx_header = "cpu/minor/func_unit.hh" 709036Sandreas.hansson@arm.com 719036Sandreas.hansson@arm.com opClasses = VectorParam.MinorOpClass([], "op classes to be matched." 728713Sandreas.hansson@arm.com " An empty list means any class") 738713Sandreas.hansson@arm.com 749164Sandreas.hansson@arm.comclass MinorFUTiming(SimObject): 758713Sandreas.hansson@arm.com type = 'MinorFUTiming' 768931Sandreas.hansson@arm.com cxx_header = "cpu/minor/func_unit.hh" 778839Sandreas.hansson@arm.com 788839Sandreas.hansson@arm.com mask = Param.UInt64(0, "mask for testing ExtMachInst") 798839Sandreas.hansson@arm.com match = Param.UInt64(0, "match value for testing ExtMachInst:" 802934Sktlim@umich.edu " (ext_mach_inst & mask) == match") 812934Sktlim@umich.edu suppress = Param.Bool(False, "if true, this inst. is not executed by" 822995Ssaidi@eecs.umich.edu " this FU") 832934Sktlim@umich.edu extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for" 842934Sktlim@umich.edu " this inst.") 852934Sktlim@umich.edu extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a" 868839Sandreas.hansson@arm.com " run-time evaluated expression") 878839Sandreas.hansson@arm.com extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard" 888839Sandreas.hansson@arm.com " retire time for this insts dest registers once it leaves the" 898839Sandreas.hansson@arm.com " functional unit. For mem refs, if this is 0, the result's time" 908839Sandreas.hansson@arm.com " is marked as unpredictable and no forwarding can take place.") 918839Sandreas.hansson@arm.com srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles" 922995Ssaidi@eecs.umich.edu " after inst. issue that each src reg can be available for this" 932934Sktlim@umich.edu " inst. to issue") 942934Sktlim@umich.edu opClasses = Param.MinorOpClassSet(MinorOpClassSet(), 952953Sktlim@umich.edu "op classes to be considered for this decode. An empty set means any" 965478Snate@binkert.org " class") 972934Sktlim@umich.edu description = Param.String('', "description string of the decoding/inst." 983449Shsul@eecs.umich.edu " class") 992934Sktlim@umich.edu 1002934Sktlim@umich.edudef minorMakeOpClassSet(op_classes): 1012934Sktlim@umich.edu """Make a MinorOpClassSet from a list of OpClass enum value strings""" 1028839Sandreas.hansson@arm.com def boxOpClass(op_class): 1038706Sandreas.hansson@arm.com return MinorOpClass(opClass=op_class) 1042934Sktlim@umich.edu 1052934Sktlim@umich.edu return MinorOpClassSet(opClasses=map(boxOpClass, op_classes)) 1067014SBrad.Beckmann@amd.com 1076765SBrad.Beckmann@amd.comclass MinorFU(SimObject): 1086765SBrad.Beckmann@amd.com type = 'MinorFU' 1096765SBrad.Beckmann@amd.com cxx_header = "cpu/minor/func_unit.hh" 1106765SBrad.Beckmann@amd.com 1116765SBrad.Beckmann@amd.com opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations" 1128931Sandreas.hansson@arm.com " allowed on this functional unit") 1137014SBrad.Beckmann@amd.com opLat = Param.Cycles(1, "latency in cycles") 1146765SBrad.Beckmann@amd.com issueLat = Param.Cycles(1, "cycles until another instruction can be" 1156765SBrad.Beckmann@amd.com " issued") 1166765SBrad.Beckmann@amd.com timings = VectorParam.MinorFUTiming([], "extra decoding rules") 1176765SBrad.Beckmann@amd.com 1186765SBrad.Beckmann@amd.com cantForwardFromFUIndices = VectorParam.Unsigned([], 1196765SBrad.Beckmann@amd.com "list of FU indices from which this FU can't receive and early" 1209036Sandreas.hansson@arm.com " (forwarded) result") 1216893SBrad.Beckmann@amd.com 1226893SBrad.Beckmann@amd.comclass MinorFUPool(SimObject): 1236893SBrad.Beckmann@amd.com type = 'MinorFUPool' 1246893SBrad.Beckmann@amd.com cxx_header = "cpu/minor/func_unit.hh" 1256893SBrad.Beckmann@amd.com 1266893SBrad.Beckmann@amd.com funcUnits = VectorParam.MinorFU("functional units") 1278898Snilay@cs.wisc.edu 1286893SBrad.Beckmann@amd.comclass MinorDefaultIntFU(MinorFU): 1296765SBrad.Beckmann@amd.com opClasses = minorMakeOpClassSet(['IntAlu']) 1306765SBrad.Beckmann@amd.com timings = [MinorFUTiming(description="Int", 1316765SBrad.Beckmann@amd.com srcRegsRelativeLats=[2])] 1326765SBrad.Beckmann@amd.com opLat = 3 1336765SBrad.Beckmann@amd.com 1346765SBrad.Beckmann@amd.comclass MinorDefaultIntMulFU(MinorFU): 1358839Sandreas.hansson@arm.com opClasses = minorMakeOpClassSet(['IntMult']) 1368839Sandreas.hansson@arm.com timings = [MinorFUTiming(description='Mul', 1378839Sandreas.hansson@arm.com srcRegsRelativeLats=[0])] 1388839Sandreas.hansson@arm.com opLat = 3 1396765SBrad.Beckmann@amd.com 1406893SBrad.Beckmann@amd.comclass MinorDefaultIntDivFU(MinorFU): 1417633SBrad.Beckmann@amd.com opClasses = minorMakeOpClassSet(['IntDiv']) 1427633SBrad.Beckmann@amd.com issueLat = 9 1436893SBrad.Beckmann@amd.com opLat = 9 1448929Snilay@cs.wisc.edu 1456765SBrad.Beckmann@amd.comclass MinorDefaultFloatSimdFU(MinorFU): 1466765SBrad.Beckmann@amd.com opClasses = minorMakeOpClassSet([ 1476765SBrad.Beckmann@amd.com 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult', 1486765SBrad.Beckmann@amd.com 'FloatMultAcc', 'FloatDiv', 'FloatSqrt', 1496765SBrad.Beckmann@amd.com 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 1506765SBrad.Beckmann@amd.com 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 1516765SBrad.Beckmann@amd.com 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 1526765SBrad.Beckmann@amd.com 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 1536765SBrad.Beckmann@amd.com 'SimdFloatMultAcc', 'SimdFloatSqrt']) 1546765SBrad.Beckmann@amd.com timings = [MinorFUTiming(description='FloatSimd', 1556765SBrad.Beckmann@amd.com srcRegsRelativeLats=[2])] 1566765SBrad.Beckmann@amd.com opLat = 6 1576765SBrad.Beckmann@amd.com 1583584Ssaidi@eecs.umich.educlass MinorDefaultMemFU(MinorFU): 1598713Sandreas.hansson@arm.com opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead', 1608713Sandreas.hansson@arm.com 'FloatMemWrite']) 1618713Sandreas.hansson@arm.com timings = [MinorFUTiming(description='Mem', 1628713Sandreas.hansson@arm.com srcRegsRelativeLats=[1], extraAssumedLat=2)] 1634486Sbinkertn@umich.edu opLat = 1 1644486Sbinkertn@umich.edu 1654486Sbinkertn@umich.educlass MinorDefaultMiscFU(MinorFU): 1664486Sbinkertn@umich.edu opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch']) 1674486Sbinkertn@umich.edu opLat = 1 1684486Sbinkertn@umich.edu 1694486Sbinkertn@umich.educlass MinorDefaultFUPool(MinorFUPool): 1703584Ssaidi@eecs.umich.edu funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(), 1713584Ssaidi@eecs.umich.edu MinorDefaultIntMulFU(), MinorDefaultIntDivFU(), 1723584Ssaidi@eecs.umich.edu MinorDefaultFloatSimdFU(), MinorDefaultMemFU(), 1733584Ssaidi@eecs.umich.edu MinorDefaultMiscFU()] 1743584Ssaidi@eecs.umich.edu 1759036Sandreas.hansson@arm.comclass ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random'] 1769036Sandreas.hansson@arm.com 1779164Sandreas.hansson@arm.comclass MinorCPU(BaseCPU): 1783743Sgblack@eecs.umich.edu type = 'MinorCPU' 1794104Ssaidi@eecs.umich.edu cxx_header = "cpu/minor/cpu.hh" 1803743Sgblack@eecs.umich.edu 1818931Sandreas.hansson@arm.com @classmethod 1828931Sandreas.hansson@arm.com def memory_mode(cls): 1838931Sandreas.hansson@arm.com return 'timing' 1848931Sandreas.hansson@arm.com 1858839Sandreas.hansson@arm.com @classmethod 1868839Sandreas.hansson@arm.com def require_caches(cls): 1878839Sandreas.hansson@arm.com return True 1888839Sandreas.hansson@arm.com 1898839Sandreas.hansson@arm.com @classmethod 1908839Sandreas.hansson@arm.com def support_take_over(cls): 1918839Sandreas.hansson@arm.com return True 1928839Sandreas.hansson@arm.com 1933584Ssaidi@eecs.umich.edu threadPolicy = Param.ThreadPolicy('RoundRobin', 1943898Ssaidi@eecs.umich.edu "Thread scheduling policy") 1953898Ssaidi@eecs.umich.edu fetch1FetchLimit = Param.Unsigned(1, 1968839Sandreas.hansson@arm.com "Number of line fetches allowable in flight at once") 1978713Sandreas.hansson@arm.com fetch1LineSnapWidth = Param.Unsigned(0, 1988713Sandreas.hansson@arm.com "Fetch1 'line' fetch snap size in bytes" 1998713Sandreas.hansson@arm.com " (0 means use system cache line size)") 2008713Sandreas.hansson@arm.com fetch1LineWidth = Param.Unsigned(0, 2018713Sandreas.hansson@arm.com "Fetch1 maximum fetch size in bytes (0 means use system cache" 2028713Sandreas.hansson@arm.com " line size)") 2038713Sandreas.hansson@arm.com fetch1ToFetch2ForwardDelay = Param.Cycles(1, 2048713Sandreas.hansson@arm.com "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)") 2058713Sandreas.hansson@arm.com fetch1ToFetch2BackwardDelay = Param.Cycles(1, 2068713Sandreas.hansson@arm.com "Backward cycle delay from Fetch2 to Fetch1 for branch prediction" 2078713Sandreas.hansson@arm.com " signalling (0 means in the same cycle, 1 mean the next cycle)") 2088713Sandreas.hansson@arm.com 2098713Sandreas.hansson@arm.com fetch2InputBufferSize = Param.Unsigned(2, 2108713Sandreas.hansson@arm.com "Size of input buffer to Fetch2 in cycles-worth of insts.") 2118713Sandreas.hansson@arm.com fetch2ToDecodeForwardDelay = Param.Cycles(1, 2128713Sandreas.hansson@arm.com "Forward cycle delay from Fetch2 to Decode (1 means next cycle)") 2138713Sandreas.hansson@arm.com fetch2CycleInput = Param.Bool(True, 2148713Sandreas.hansson@arm.com "Allow Fetch2 to cross input lines to generate full output each" 2158713Sandreas.hansson@arm.com " cycle") 2164103Ssaidi@eecs.umich.edu 2174103Ssaidi@eecs.umich.edu decodeInputBufferSize = Param.Unsigned(3, 2184103Ssaidi@eecs.umich.edu "Size of input buffer to Decode in cycles-worth of insts.") 2193745Sgblack@eecs.umich.edu decodeToExecuteForwardDelay = Param.Cycles(1, 2203745Sgblack@eecs.umich.edu "Forward cycle delay from Decode to Execute (1 means next cycle)") 2213745Sgblack@eecs.umich.edu decodeInputWidth = Param.Unsigned(2, 2223584Ssaidi@eecs.umich.edu "Width (in instructions) of input to Decode (and implicitly" 2238839Sandreas.hansson@arm.com " Decode's own width)") 2248706Sandreas.hansson@arm.com decodeCycleInput = Param.Bool(True, 2253584Ssaidi@eecs.umich.edu "Allow Decode to pack instructions from more than one input cycle" 2263584Ssaidi@eecs.umich.edu " to fill its output each cycle") 2278061SAli.Saidi@ARM.com 2288061SAli.Saidi@ARM.com executeInputWidth = Param.Unsigned(2, 2298061SAli.Saidi@ARM.com "Width (in instructions) of input to Execute") 2307586SAli.Saidi@arm.com executeCycleInput = Param.Bool(True, 2317586SAli.Saidi@arm.com "Allow Execute to use instructions from more than one input cycle" 2327586SAli.Saidi@arm.com " each cycle") 2337586SAli.Saidi@arm.com executeIssueLimit = Param.Unsigned(2, 2347586SAli.Saidi@arm.com "Number of issuable instructions in Execute each cycle") 2357586SAli.Saidi@arm.com executeMemoryIssueLimit = Param.Unsigned(1, 2367586SAli.Saidi@arm.com "Number of issuable memory instructions in Execute each cycle") 2377586SAli.Saidi@arm.com executeCommitLimit = Param.Unsigned(2, 2387586SAli.Saidi@arm.com "Number of committable instructions in Execute each cycle") 2397586SAli.Saidi@arm.com executeMemoryCommitLimit = Param.Unsigned(1, 2409036Sandreas.hansson@arm.com "Number of committable memory references in Execute each cycle") 2419036Sandreas.hansson@arm.com executeInputBufferSize = Param.Unsigned(7, 2427586SAli.Saidi@arm.com "Size of input buffer to Execute in cycles-worth of insts.") 2439164Sandreas.hansson@arm.com executeMemoryWidth = Param.Unsigned(0, 2448839Sandreas.hansson@arm.com "Width (and snap) in bytes of the data memory interface. (0 mean use" 2458839Sandreas.hansson@arm.com " the system cacheLineSize)") 2467586SAli.Saidi@arm.com executeMaxAccessesInMemory = Param.Unsigned(2, 2477586SAli.Saidi@arm.com "Maximum number of concurrent accesses allowed to the memory system" 2487586SAli.Saidi@arm.com " from the dcache port") 2497586SAli.Saidi@arm.com executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2, 2507586SAli.Saidi@arm.com "Maximum number of stores that the store buffer can issue per cycle") 2517586SAli.Saidi@arm.com executeLSQRequestsQueueSize = Param.Unsigned(1, 2527586SAli.Saidi@arm.com "Size of LSQ requests queue (address translation queue)") 2538525SAli.Saidi@ARM.com executeLSQTransfersQueueSize = Param.Unsigned(2, 2548525SAli.Saidi@ARM.com "Size of LSQ transfers queue (memory transaction queue)") 2558870SAli.Saidi@ARM.com executeLSQStoreBufferSize = Param.Unsigned(5, 2568870SAli.Saidi@ARM.com "Size of LSQ store buffer") 2578870SAli.Saidi@ARM.com executeBranchDelay = Param.Cycles(1, 2587586SAli.Saidi@arm.com "Delay from Execute deciding to branch and Fetch1 reacting" 2597586SAli.Saidi@arm.com " (1 means next cycle)") 2607586SAli.Saidi@arm.com 2617586SAli.Saidi@arm.com executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(), 2628528SAli.Saidi@ARM.com "FUlines for this processor") 2638528SAli.Saidi@ARM.com 2648528SAli.Saidi@ARM.com executeSetTraceTimeOnCommit = Param.Bool(True, 2658528SAli.Saidi@ARM.com "Set inst. trace times to be commit times") 2668528SAli.Saidi@ARM.com executeSetTraceTimeOnIssue = Param.Bool(False, 2678528SAli.Saidi@ARM.com "Set inst. trace times to be issue times") 2688528SAli.Saidi@ARM.com 2698528SAli.Saidi@ARM.com executeAllowEarlyMemoryIssue = Param.Bool(True, 2708528SAli.Saidi@ARM.com "Allow mem refs to be issued to the LSQ before reaching the head of" 2718061SAli.Saidi@ARM.com " the in flight insts queue") 2728061SAli.Saidi@ARM.com 2738061SAli.Saidi@ARM.com enableIdling = Param.Bool(True, 2748931Sandreas.hansson@arm.com "Enable cycle skipping when the processor is idle\n"); 2758931Sandreas.hansson@arm.com 2768061SAli.Saidi@ARM.com branchPred = Param.BranchPredictor(TournamentBP( 2778528SAli.Saidi@ARM.com numThreads = Parent.numThreads), "Branch Predictor") 2787586SAli.Saidi@arm.com 2798894Ssaidi@eecs.umich.edu def addCheckerCpu(self): 2808870SAli.Saidi@ARM.com print("Checker not yet supported by MinorCPU") 2818870SAli.Saidi@ARM.com exit(1) 2828870SAli.Saidi@ARM.com