MinorCPU.py revision 12563
110259SAndrew.Bardsley@arm.com# Copyright (c) 2012-2014 ARM Limited 210259SAndrew.Bardsley@arm.com# All rights reserved. 310259SAndrew.Bardsley@arm.com# 410259SAndrew.Bardsley@arm.com# The license below extends only to copyright in the software and shall 510259SAndrew.Bardsley@arm.com# not be construed as granting a license to any other intellectual 610259SAndrew.Bardsley@arm.com# property including but not limited to intellectual property relating 710259SAndrew.Bardsley@arm.com# to a hardware implementation of the functionality of the software 810259SAndrew.Bardsley@arm.com# licensed hereunder. You may use the software subject to the license 910259SAndrew.Bardsley@arm.com# terms below provided that you ensure that this notice is replicated 1010259SAndrew.Bardsley@arm.com# unmodified and in its entirety in all distributions of the software, 1110259SAndrew.Bardsley@arm.com# modified or unmodified, in source code or in binary form. 1210259SAndrew.Bardsley@arm.com# 1310259SAndrew.Bardsley@arm.com# Copyright (c) 2007 The Regents of The University of Michigan 1410259SAndrew.Bardsley@arm.com# All rights reserved. 1510259SAndrew.Bardsley@arm.com# 1610259SAndrew.Bardsley@arm.com# Redistribution and use in source and binary forms, with or without 1710259SAndrew.Bardsley@arm.com# modification, are permitted provided that the following conditions are 1810259SAndrew.Bardsley@arm.com# met: redistributions of source code must retain the above copyright 1910259SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer; 2010259SAndrew.Bardsley@arm.com# redistributions in binary form must reproduce the above copyright 2110259SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer in the 2210259SAndrew.Bardsley@arm.com# documentation and/or other materials provided with the distribution; 2310259SAndrew.Bardsley@arm.com# neither the name of the copyright holders nor the names of its 2410259SAndrew.Bardsley@arm.com# contributors may be used to endorse or promote products derived from 2510259SAndrew.Bardsley@arm.com# this software without specific prior written permission. 2610259SAndrew.Bardsley@arm.com# 2710259SAndrew.Bardsley@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2810259SAndrew.Bardsley@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2910259SAndrew.Bardsley@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3010259SAndrew.Bardsley@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3110259SAndrew.Bardsley@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3210259SAndrew.Bardsley@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3310259SAndrew.Bardsley@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3410259SAndrew.Bardsley@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3510259SAndrew.Bardsley@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3610259SAndrew.Bardsley@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3710259SAndrew.Bardsley@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3810259SAndrew.Bardsley@arm.com# 3910259SAndrew.Bardsley@arm.com# Authors: Gabe Black 4010259SAndrew.Bardsley@arm.com# Nathan Binkert 4110259SAndrew.Bardsley@arm.com# Andrew Bardsley 4210259SAndrew.Bardsley@arm.com 4312563Sgabeblack@google.comfrom __future__ import print_function 4412563Sgabeblack@google.com 4510259SAndrew.Bardsley@arm.comfrom m5.defines import buildEnv 4610259SAndrew.Bardsley@arm.comfrom m5.params import * 4710259SAndrew.Bardsley@arm.comfrom m5.proxy import * 4810259SAndrew.Bardsley@arm.comfrom m5.SimObject import SimObject 4910259SAndrew.Bardsley@arm.comfrom BaseCPU import BaseCPU 5010259SAndrew.Bardsley@arm.comfrom DummyChecker import DummyChecker 5110785Sgope@wisc.edufrom BranchPredictor import * 5210259SAndrew.Bardsley@arm.comfrom TimingExpr import TimingExpr 5310259SAndrew.Bardsley@arm.com 5410259SAndrew.Bardsley@arm.comfrom FuncUnit import OpClass 5510259SAndrew.Bardsley@arm.com 5610259SAndrew.Bardsley@arm.comclass MinorOpClass(SimObject): 5710259SAndrew.Bardsley@arm.com """Boxing of OpClass to get around build problems and provide a hook for 5810259SAndrew.Bardsley@arm.com future additions to OpClass checks""" 5910259SAndrew.Bardsley@arm.com 6010259SAndrew.Bardsley@arm.com type = 'MinorOpClass' 6110259SAndrew.Bardsley@arm.com cxx_header = "cpu/minor/func_unit.hh" 6210259SAndrew.Bardsley@arm.com 6310259SAndrew.Bardsley@arm.com opClass = Param.OpClass("op class to match") 6410259SAndrew.Bardsley@arm.com 6510259SAndrew.Bardsley@arm.comclass MinorOpClassSet(SimObject): 6610259SAndrew.Bardsley@arm.com """A set of matchable op classes""" 6710259SAndrew.Bardsley@arm.com 6810259SAndrew.Bardsley@arm.com type = 'MinorOpClassSet' 6910259SAndrew.Bardsley@arm.com cxx_header = "cpu/minor/func_unit.hh" 7010259SAndrew.Bardsley@arm.com 7110259SAndrew.Bardsley@arm.com opClasses = VectorParam.MinorOpClass([], "op classes to be matched." 7210259SAndrew.Bardsley@arm.com " An empty list means any class") 7310259SAndrew.Bardsley@arm.com 7410259SAndrew.Bardsley@arm.comclass MinorFUTiming(SimObject): 7510259SAndrew.Bardsley@arm.com type = 'MinorFUTiming' 7610259SAndrew.Bardsley@arm.com cxx_header = "cpu/minor/func_unit.hh" 7710259SAndrew.Bardsley@arm.com 7810259SAndrew.Bardsley@arm.com mask = Param.UInt64(0, "mask for testing ExtMachInst") 7910259SAndrew.Bardsley@arm.com match = Param.UInt64(0, "match value for testing ExtMachInst:" 8010259SAndrew.Bardsley@arm.com " (ext_mach_inst & mask) == match") 8110259SAndrew.Bardsley@arm.com suppress = Param.Bool(False, "if true, this inst. is not executed by" 8210259SAndrew.Bardsley@arm.com " this FU") 8310259SAndrew.Bardsley@arm.com extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for" 8410259SAndrew.Bardsley@arm.com " this inst.") 8510259SAndrew.Bardsley@arm.com extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a" 8610259SAndrew.Bardsley@arm.com " run-time evaluated expression") 8710259SAndrew.Bardsley@arm.com extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard" 8810259SAndrew.Bardsley@arm.com " retire time for this insts dest registers once it leaves the" 8910259SAndrew.Bardsley@arm.com " functional unit. For mem refs, if this is 0, the result's time" 9010259SAndrew.Bardsley@arm.com " is marked as unpredictable and no forwarding can take place.") 9110259SAndrew.Bardsley@arm.com srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles" 9210259SAndrew.Bardsley@arm.com " after inst. issue that each src reg can be available for this" 9310259SAndrew.Bardsley@arm.com " inst. to issue") 9410259SAndrew.Bardsley@arm.com opClasses = Param.MinorOpClassSet(MinorOpClassSet(), 9510259SAndrew.Bardsley@arm.com "op classes to be considered for this decode. An empty set means any" 9610259SAndrew.Bardsley@arm.com " class") 9710259SAndrew.Bardsley@arm.com description = Param.String('', "description string of the decoding/inst." 9810259SAndrew.Bardsley@arm.com " class") 9910259SAndrew.Bardsley@arm.com 10010259SAndrew.Bardsley@arm.comdef minorMakeOpClassSet(op_classes): 10110259SAndrew.Bardsley@arm.com """Make a MinorOpClassSet from a list of OpClass enum value strings""" 10210259SAndrew.Bardsley@arm.com def boxOpClass(op_class): 10310259SAndrew.Bardsley@arm.com return MinorOpClass(opClass=op_class) 10410259SAndrew.Bardsley@arm.com 10510259SAndrew.Bardsley@arm.com return MinorOpClassSet(opClasses=map(boxOpClass, op_classes)) 10610259SAndrew.Bardsley@arm.com 10710259SAndrew.Bardsley@arm.comclass MinorFU(SimObject): 10810259SAndrew.Bardsley@arm.com type = 'MinorFU' 10910259SAndrew.Bardsley@arm.com cxx_header = "cpu/minor/func_unit.hh" 11010259SAndrew.Bardsley@arm.com 11110259SAndrew.Bardsley@arm.com opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations" 11210259SAndrew.Bardsley@arm.com " allowed on this functional unit") 11310259SAndrew.Bardsley@arm.com opLat = Param.Cycles(1, "latency in cycles") 11410259SAndrew.Bardsley@arm.com issueLat = Param.Cycles(1, "cycles until another instruction can be" 11510259SAndrew.Bardsley@arm.com " issued") 11610259SAndrew.Bardsley@arm.com timings = VectorParam.MinorFUTiming([], "extra decoding rules") 11710259SAndrew.Bardsley@arm.com 11810259SAndrew.Bardsley@arm.com cantForwardFromFUIndices = VectorParam.Unsigned([], 11910259SAndrew.Bardsley@arm.com "list of FU indices from which this FU can't receive and early" 12010259SAndrew.Bardsley@arm.com " (forwarded) result") 12110259SAndrew.Bardsley@arm.com 12210259SAndrew.Bardsley@arm.comclass MinorFUPool(SimObject): 12310259SAndrew.Bardsley@arm.com type = 'MinorFUPool' 12410259SAndrew.Bardsley@arm.com cxx_header = "cpu/minor/func_unit.hh" 12510259SAndrew.Bardsley@arm.com 12610259SAndrew.Bardsley@arm.com funcUnits = VectorParam.MinorFU("functional units") 12710259SAndrew.Bardsley@arm.com 12810259SAndrew.Bardsley@arm.comclass MinorDefaultIntFU(MinorFU): 12910259SAndrew.Bardsley@arm.com opClasses = minorMakeOpClassSet(['IntAlu']) 13010259SAndrew.Bardsley@arm.com timings = [MinorFUTiming(description="Int", 13110259SAndrew.Bardsley@arm.com srcRegsRelativeLats=[2])] 13210259SAndrew.Bardsley@arm.com opLat = 3 13310259SAndrew.Bardsley@arm.com 13410259SAndrew.Bardsley@arm.comclass MinorDefaultIntMulFU(MinorFU): 13510259SAndrew.Bardsley@arm.com opClasses = minorMakeOpClassSet(['IntMult']) 13610259SAndrew.Bardsley@arm.com timings = [MinorFUTiming(description='Mul', 13710259SAndrew.Bardsley@arm.com srcRegsRelativeLats=[0])] 13810259SAndrew.Bardsley@arm.com opLat = 3 13910259SAndrew.Bardsley@arm.com 14010259SAndrew.Bardsley@arm.comclass MinorDefaultIntDivFU(MinorFU): 14110259SAndrew.Bardsley@arm.com opClasses = minorMakeOpClassSet(['IntDiv']) 14210259SAndrew.Bardsley@arm.com issueLat = 9 14310259SAndrew.Bardsley@arm.com opLat = 9 14410259SAndrew.Bardsley@arm.com 14510259SAndrew.Bardsley@arm.comclass MinorDefaultFloatSimdFU(MinorFU): 14610259SAndrew.Bardsley@arm.com opClasses = minorMakeOpClassSet([ 14711683Sfernando.endo2@gmail.com 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult', 14811683Sfernando.endo2@gmail.com 'FloatMultAcc', 'FloatDiv', 'FloatSqrt', 14910259SAndrew.Bardsley@arm.com 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 15010259SAndrew.Bardsley@arm.com 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 15110259SAndrew.Bardsley@arm.com 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 15210259SAndrew.Bardsley@arm.com 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 15310259SAndrew.Bardsley@arm.com 'SimdFloatMultAcc', 'SimdFloatSqrt']) 15410259SAndrew.Bardsley@arm.com timings = [MinorFUTiming(description='FloatSimd', 15510259SAndrew.Bardsley@arm.com srcRegsRelativeLats=[2])] 15610259SAndrew.Bardsley@arm.com opLat = 6 15710259SAndrew.Bardsley@arm.com 15810259SAndrew.Bardsley@arm.comclass MinorDefaultMemFU(MinorFU): 15911683Sfernando.endo2@gmail.com opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead', 16011683Sfernando.endo2@gmail.com 'FloatMemWrite']) 16110259SAndrew.Bardsley@arm.com timings = [MinorFUTiming(description='Mem', 16210259SAndrew.Bardsley@arm.com srcRegsRelativeLats=[1], extraAssumedLat=2)] 16310259SAndrew.Bardsley@arm.com opLat = 1 16410259SAndrew.Bardsley@arm.com 16510259SAndrew.Bardsley@arm.comclass MinorDefaultMiscFU(MinorFU): 16610259SAndrew.Bardsley@arm.com opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch']) 16710259SAndrew.Bardsley@arm.com opLat = 1 16810259SAndrew.Bardsley@arm.com 16910259SAndrew.Bardsley@arm.comclass MinorDefaultFUPool(MinorFUPool): 17010259SAndrew.Bardsley@arm.com funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(), 17110259SAndrew.Bardsley@arm.com MinorDefaultIntMulFU(), MinorDefaultIntDivFU(), 17210259SAndrew.Bardsley@arm.com MinorDefaultFloatSimdFU(), MinorDefaultMemFU(), 17310259SAndrew.Bardsley@arm.com MinorDefaultMiscFU()] 17410259SAndrew.Bardsley@arm.com 17511567Smitch.hayenga@arm.comclass ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random'] 17611567Smitch.hayenga@arm.com 17710259SAndrew.Bardsley@arm.comclass MinorCPU(BaseCPU): 17810259SAndrew.Bardsley@arm.com type = 'MinorCPU' 17910259SAndrew.Bardsley@arm.com cxx_header = "cpu/minor/cpu.hh" 18010259SAndrew.Bardsley@arm.com 18110259SAndrew.Bardsley@arm.com @classmethod 18210259SAndrew.Bardsley@arm.com def memory_mode(cls): 18310259SAndrew.Bardsley@arm.com return 'timing' 18410259SAndrew.Bardsley@arm.com 18510259SAndrew.Bardsley@arm.com @classmethod 18610259SAndrew.Bardsley@arm.com def require_caches(cls): 18710259SAndrew.Bardsley@arm.com return True 18810259SAndrew.Bardsley@arm.com 18910259SAndrew.Bardsley@arm.com @classmethod 19010259SAndrew.Bardsley@arm.com def support_take_over(cls): 19110259SAndrew.Bardsley@arm.com return True 19210259SAndrew.Bardsley@arm.com 19311567Smitch.hayenga@arm.com threadPolicy = Param.ThreadPolicy('RoundRobin', 19411567Smitch.hayenga@arm.com "Thread scheduling policy") 19510259SAndrew.Bardsley@arm.com fetch1FetchLimit = Param.Unsigned(1, 19610259SAndrew.Bardsley@arm.com "Number of line fetches allowable in flight at once") 19710259SAndrew.Bardsley@arm.com fetch1LineSnapWidth = Param.Unsigned(0, 19810259SAndrew.Bardsley@arm.com "Fetch1 'line' fetch snap size in bytes" 19910259SAndrew.Bardsley@arm.com " (0 means use system cache line size)") 20010259SAndrew.Bardsley@arm.com fetch1LineWidth = Param.Unsigned(0, 20110259SAndrew.Bardsley@arm.com "Fetch1 maximum fetch size in bytes (0 means use system cache" 20210259SAndrew.Bardsley@arm.com " line size)") 20310259SAndrew.Bardsley@arm.com fetch1ToFetch2ForwardDelay = Param.Cycles(1, 20410259SAndrew.Bardsley@arm.com "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)") 20510259SAndrew.Bardsley@arm.com fetch1ToFetch2BackwardDelay = Param.Cycles(1, 20610259SAndrew.Bardsley@arm.com "Backward cycle delay from Fetch2 to Fetch1 for branch prediction" 20710259SAndrew.Bardsley@arm.com " signalling (0 means in the same cycle, 1 mean the next cycle)") 20810259SAndrew.Bardsley@arm.com 20910259SAndrew.Bardsley@arm.com fetch2InputBufferSize = Param.Unsigned(2, 21010259SAndrew.Bardsley@arm.com "Size of input buffer to Fetch2 in cycles-worth of insts.") 21110259SAndrew.Bardsley@arm.com fetch2ToDecodeForwardDelay = Param.Cycles(1, 21210259SAndrew.Bardsley@arm.com "Forward cycle delay from Fetch2 to Decode (1 means next cycle)") 21310259SAndrew.Bardsley@arm.com fetch2CycleInput = Param.Bool(True, 21410259SAndrew.Bardsley@arm.com "Allow Fetch2 to cross input lines to generate full output each" 21510259SAndrew.Bardsley@arm.com " cycle") 21610259SAndrew.Bardsley@arm.com 21710259SAndrew.Bardsley@arm.com decodeInputBufferSize = Param.Unsigned(3, 21810259SAndrew.Bardsley@arm.com "Size of input buffer to Decode in cycles-worth of insts.") 21910259SAndrew.Bardsley@arm.com decodeToExecuteForwardDelay = Param.Cycles(1, 22010259SAndrew.Bardsley@arm.com "Forward cycle delay from Decode to Execute (1 means next cycle)") 22110259SAndrew.Bardsley@arm.com decodeInputWidth = Param.Unsigned(2, 22210259SAndrew.Bardsley@arm.com "Width (in instructions) of input to Decode (and implicitly" 22310259SAndrew.Bardsley@arm.com " Decode's own width)") 22410259SAndrew.Bardsley@arm.com decodeCycleInput = Param.Bool(True, 22510259SAndrew.Bardsley@arm.com "Allow Decode to pack instructions from more than one input cycle" 22610259SAndrew.Bardsley@arm.com " to fill its output each cycle") 22710259SAndrew.Bardsley@arm.com 22810259SAndrew.Bardsley@arm.com executeInputWidth = Param.Unsigned(2, 22910259SAndrew.Bardsley@arm.com "Width (in instructions) of input to Execute") 23010259SAndrew.Bardsley@arm.com executeCycleInput = Param.Bool(True, 23110259SAndrew.Bardsley@arm.com "Allow Execute to use instructions from more than one input cycle" 23210259SAndrew.Bardsley@arm.com " each cycle") 23310259SAndrew.Bardsley@arm.com executeIssueLimit = Param.Unsigned(2, 23410259SAndrew.Bardsley@arm.com "Number of issuable instructions in Execute each cycle") 23510259SAndrew.Bardsley@arm.com executeMemoryIssueLimit = Param.Unsigned(1, 23610259SAndrew.Bardsley@arm.com "Number of issuable memory instructions in Execute each cycle") 23710259SAndrew.Bardsley@arm.com executeCommitLimit = Param.Unsigned(2, 23810259SAndrew.Bardsley@arm.com "Number of committable instructions in Execute each cycle") 23910259SAndrew.Bardsley@arm.com executeMemoryCommitLimit = Param.Unsigned(1, 24010259SAndrew.Bardsley@arm.com "Number of committable memory references in Execute each cycle") 24110259SAndrew.Bardsley@arm.com executeInputBufferSize = Param.Unsigned(7, 24210259SAndrew.Bardsley@arm.com "Size of input buffer to Execute in cycles-worth of insts.") 24310259SAndrew.Bardsley@arm.com executeMemoryWidth = Param.Unsigned(0, 24410259SAndrew.Bardsley@arm.com "Width (and snap) in bytes of the data memory interface. (0 mean use" 24510259SAndrew.Bardsley@arm.com " the system cacheLineSize)") 24610259SAndrew.Bardsley@arm.com executeMaxAccessesInMemory = Param.Unsigned(2, 24710259SAndrew.Bardsley@arm.com "Maximum number of concurrent accesses allowed to the memory system" 24810259SAndrew.Bardsley@arm.com " from the dcache port") 24910259SAndrew.Bardsley@arm.com executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2, 25010259SAndrew.Bardsley@arm.com "Maximum number of stores that the store buffer can issue per cycle") 25110259SAndrew.Bardsley@arm.com executeLSQRequestsQueueSize = Param.Unsigned(1, 25210259SAndrew.Bardsley@arm.com "Size of LSQ requests queue (address translation queue)") 25310259SAndrew.Bardsley@arm.com executeLSQTransfersQueueSize = Param.Unsigned(2, 25410259SAndrew.Bardsley@arm.com "Size of LSQ transfers queue (memory transaction queue)") 25510259SAndrew.Bardsley@arm.com executeLSQStoreBufferSize = Param.Unsigned(5, 25610259SAndrew.Bardsley@arm.com "Size of LSQ store buffer") 25710259SAndrew.Bardsley@arm.com executeBranchDelay = Param.Cycles(1, 25810259SAndrew.Bardsley@arm.com "Delay from Execute deciding to branch and Fetch1 reacting" 25910259SAndrew.Bardsley@arm.com " (1 means next cycle)") 26010259SAndrew.Bardsley@arm.com 26110259SAndrew.Bardsley@arm.com executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(), 26210259SAndrew.Bardsley@arm.com "FUlines for this processor") 26310259SAndrew.Bardsley@arm.com 26410259SAndrew.Bardsley@arm.com executeSetTraceTimeOnCommit = Param.Bool(True, 26510259SAndrew.Bardsley@arm.com "Set inst. trace times to be commit times") 26610259SAndrew.Bardsley@arm.com executeSetTraceTimeOnIssue = Param.Bool(False, 26710259SAndrew.Bardsley@arm.com "Set inst. trace times to be issue times") 26810259SAndrew.Bardsley@arm.com 26910259SAndrew.Bardsley@arm.com executeAllowEarlyMemoryIssue = Param.Bool(True, 27010259SAndrew.Bardsley@arm.com "Allow mem refs to be issued to the LSQ before reaching the head of" 27110259SAndrew.Bardsley@arm.com " the in flight insts queue") 27210259SAndrew.Bardsley@arm.com 27310259SAndrew.Bardsley@arm.com enableIdling = Param.Bool(True, 27410259SAndrew.Bardsley@arm.com "Enable cycle skipping when the processor is idle\n"); 27510259SAndrew.Bardsley@arm.com 27610785Sgope@wisc.edu branchPred = Param.BranchPredictor(TournamentBP( 27710259SAndrew.Bardsley@arm.com numThreads = Parent.numThreads), "Branch Predictor") 27810259SAndrew.Bardsley@arm.com 27910259SAndrew.Bardsley@arm.com def addCheckerCpu(self): 28012563Sgabeblack@google.com print("Checker not yet supported by MinorCPU") 28110259SAndrew.Bardsley@arm.com exit(1) 282