MinorCPU.py revision 10259
110201SAndrew.Bardsley@arm.com# Copyright (c) 2012-2014 ARM Limited 210201SAndrew.Bardsley@arm.com# All rights reserved. 310201SAndrew.Bardsley@arm.com# 410201SAndrew.Bardsley@arm.com# The license below extends only to copyright in the software and shall 510201SAndrew.Bardsley@arm.com# not be construed as granting a license to any other intellectual 610201SAndrew.Bardsley@arm.com# property including but not limited to intellectual property relating 710201SAndrew.Bardsley@arm.com# to a hardware implementation of the functionality of the software 810201SAndrew.Bardsley@arm.com# licensed hereunder. You may use the software subject to the license 910201SAndrew.Bardsley@arm.com# terms below provided that you ensure that this notice is replicated 1010201SAndrew.Bardsley@arm.com# unmodified and in its entirety in all distributions of the software, 1110201SAndrew.Bardsley@arm.com# modified or unmodified, in source code or in binary form. 1210201SAndrew.Bardsley@arm.com# 1310201SAndrew.Bardsley@arm.com# Copyright (c) 2007 The Regents of The University of Michigan 1410201SAndrew.Bardsley@arm.com# All rights reserved. 1510201SAndrew.Bardsley@arm.com# 1610201SAndrew.Bardsley@arm.com# Redistribution and use in source and binary forms, with or without 1710201SAndrew.Bardsley@arm.com# modification, are permitted provided that the following conditions are 1810201SAndrew.Bardsley@arm.com# met: redistributions of source code must retain the above copyright 1910201SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer; 2010201SAndrew.Bardsley@arm.com# redistributions in binary form must reproduce the above copyright 2110201SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer in the 2210201SAndrew.Bardsley@arm.com# documentation and/or other materials provided with the distribution; 2310201SAndrew.Bardsley@arm.com# neither the name of the copyright holders nor the names of its 2410201SAndrew.Bardsley@arm.com# contributors may be used to endorse or promote products derived from 2510201SAndrew.Bardsley@arm.com# this software without specific prior written permission. 2610201SAndrew.Bardsley@arm.com# 2710201SAndrew.Bardsley@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2810201SAndrew.Bardsley@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2910201SAndrew.Bardsley@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3010201SAndrew.Bardsley@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3110201SAndrew.Bardsley@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3210201SAndrew.Bardsley@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3310201SAndrew.Bardsley@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3410201SAndrew.Bardsley@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3510201SAndrew.Bardsley@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3610201SAndrew.Bardsley@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3710201SAndrew.Bardsley@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3810201SAndrew.Bardsley@arm.com# 3910201SAndrew.Bardsley@arm.com# Authors: Gabe Black 4010201SAndrew.Bardsley@arm.com# Nathan Binkert 4110201SAndrew.Bardsley@arm.com# Andrew Bardsley 4210201SAndrew.Bardsley@arm.com 4310201SAndrew.Bardsley@arm.comfrom m5.defines import buildEnv 4410201SAndrew.Bardsley@arm.comfrom m5.params import * 4510201SAndrew.Bardsley@arm.comfrom m5.proxy import * 4610201SAndrew.Bardsley@arm.comfrom m5.SimObject import SimObject 4710201SAndrew.Bardsley@arm.comfrom BaseCPU import BaseCPU 4810201SAndrew.Bardsley@arm.comfrom DummyChecker import DummyChecker 4910201SAndrew.Bardsley@arm.comfrom BranchPredictor import BranchPredictor 5010201SAndrew.Bardsley@arm.comfrom TimingExpr import TimingExpr 5110201SAndrew.Bardsley@arm.com 5210201SAndrew.Bardsley@arm.comfrom FuncUnit import OpClass 5310201SAndrew.Bardsley@arm.com 5410201SAndrew.Bardsley@arm.comclass MinorOpClass(SimObject): 5510201SAndrew.Bardsley@arm.com """Boxing of OpClass to get around build problems and provide a hook for 5610201SAndrew.Bardsley@arm.com future additions to OpClass checks""" 5710201SAndrew.Bardsley@arm.com 5810201SAndrew.Bardsley@arm.com type = 'MinorOpClass' 5910201SAndrew.Bardsley@arm.com cxx_header = "cpu/minor/func_unit.hh" 6010201SAndrew.Bardsley@arm.com 6110201SAndrew.Bardsley@arm.com opClass = Param.OpClass("op class to match") 6210201SAndrew.Bardsley@arm.com 6310201SAndrew.Bardsley@arm.comclass MinorOpClassSet(SimObject): 6410201SAndrew.Bardsley@arm.com """A set of matchable op classes""" 6510201SAndrew.Bardsley@arm.com 6610201SAndrew.Bardsley@arm.com type = 'MinorOpClassSet' 6710201SAndrew.Bardsley@arm.com cxx_header = "cpu/minor/func_unit.hh" 6810201SAndrew.Bardsley@arm.com 6910201SAndrew.Bardsley@arm.com opClasses = VectorParam.MinorOpClass([], "op classes to be matched." 7010201SAndrew.Bardsley@arm.com " An empty list means any class") 7110201SAndrew.Bardsley@arm.com 7210201SAndrew.Bardsley@arm.comclass MinorFUTiming(SimObject): 7310201SAndrew.Bardsley@arm.com type = 'MinorFUTiming' 7410201SAndrew.Bardsley@arm.com cxx_header = "cpu/minor/func_unit.hh" 7510201SAndrew.Bardsley@arm.com 7610201SAndrew.Bardsley@arm.com mask = Param.UInt64(0, "mask for testing ExtMachInst") 7710201SAndrew.Bardsley@arm.com match = Param.UInt64(0, "match value for testing ExtMachInst:" 7810201SAndrew.Bardsley@arm.com " (ext_mach_inst & mask) == match") 7910201SAndrew.Bardsley@arm.com suppress = Param.Bool(False, "if true, this inst. is not executed by" 8010201SAndrew.Bardsley@arm.com " this FU") 8110201SAndrew.Bardsley@arm.com extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for" 8210201SAndrew.Bardsley@arm.com " this inst.") 8310201SAndrew.Bardsley@arm.com extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a" 8410201SAndrew.Bardsley@arm.com " run-time evaluated expression") 8510201SAndrew.Bardsley@arm.com extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard" 8610201SAndrew.Bardsley@arm.com " retire time for this insts dest registers once it leaves the" 8710201SAndrew.Bardsley@arm.com " functional unit. For mem refs, if this is 0, the result's time" 8810201SAndrew.Bardsley@arm.com " is marked as unpredictable and no forwarding can take place.") 8910201SAndrew.Bardsley@arm.com srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles" 9010201SAndrew.Bardsley@arm.com " after inst. issue that each src reg can be available for this" 9110201SAndrew.Bardsley@arm.com " inst. to issue") 9210201SAndrew.Bardsley@arm.com opClasses = Param.MinorOpClassSet(MinorOpClassSet(), 9310201SAndrew.Bardsley@arm.com "op classes to be considered for this decode. An empty set means any" 9410201SAndrew.Bardsley@arm.com " class") 9510201SAndrew.Bardsley@arm.com description = Param.String('', "description string of the decoding/inst." 9610201SAndrew.Bardsley@arm.com " class") 9710201SAndrew.Bardsley@arm.com 9810201SAndrew.Bardsley@arm.comdef minorMakeOpClassSet(op_classes): 9910201SAndrew.Bardsley@arm.com """Make a MinorOpClassSet from a list of OpClass enum value strings""" 10010201SAndrew.Bardsley@arm.com def boxOpClass(op_class): 10110201SAndrew.Bardsley@arm.com return MinorOpClass(opClass=op_class) 10210201SAndrew.Bardsley@arm.com 10310201SAndrew.Bardsley@arm.com return MinorOpClassSet(opClasses=map(boxOpClass, op_classes)) 10410201SAndrew.Bardsley@arm.com 10510201SAndrew.Bardsley@arm.comclass MinorFU(SimObject): 10610201SAndrew.Bardsley@arm.com type = 'MinorFU' 10710201SAndrew.Bardsley@arm.com cxx_header = "cpu/minor/func_unit.hh" 10810201SAndrew.Bardsley@arm.com 10910201SAndrew.Bardsley@arm.com opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations" 11010201SAndrew.Bardsley@arm.com " allowed on this functional unit") 11110201SAndrew.Bardsley@arm.com opLat = Param.Cycles(1, "latency in cycles") 11210201SAndrew.Bardsley@arm.com issueLat = Param.Cycles(1, "cycles until another instruction can be" 113 " issued") 114 timings = VectorParam.MinorFUTiming([], "extra decoding rules") 115 116 cantForwardFromFUIndices = VectorParam.Unsigned([], 117 "list of FU indices from which this FU can't receive and early" 118 " (forwarded) result") 119 120class MinorFUPool(SimObject): 121 type = 'MinorFUPool' 122 cxx_header = "cpu/minor/func_unit.hh" 123 124 funcUnits = VectorParam.MinorFU("functional units") 125 126class MinorDefaultIntFU(MinorFU): 127 opClasses = minorMakeOpClassSet(['IntAlu']) 128 timings = [MinorFUTiming(description="Int", 129 srcRegsRelativeLats=[2])] 130 opLat = 3 131 132class MinorDefaultIntMulFU(MinorFU): 133 opClasses = minorMakeOpClassSet(['IntMult']) 134 timings = [MinorFUTiming(description='Mul', 135 srcRegsRelativeLats=[0])] 136 opLat = 3 137 138class MinorDefaultIntDivFU(MinorFU): 139 opClasses = minorMakeOpClassSet(['IntDiv']) 140 issueLat = 9 141 opLat = 9 142 143class MinorDefaultFloatSimdFU(MinorFU): 144 opClasses = minorMakeOpClassSet([ 145 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 146 'FloatSqrt', 147 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 148 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 149 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 150 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 151 'SimdFloatMultAcc', 'SimdFloatSqrt']) 152 timings = [MinorFUTiming(description='FloatSimd', 153 srcRegsRelativeLats=[2])] 154 opLat = 6 155 156class MinorDefaultMemFU(MinorFU): 157 opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite']) 158 timings = [MinorFUTiming(description='Mem', 159 srcRegsRelativeLats=[1], extraAssumedLat=2)] 160 opLat = 1 161 162class MinorDefaultMiscFU(MinorFU): 163 opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch']) 164 opLat = 1 165 166class MinorDefaultFUPool(MinorFUPool): 167 funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(), 168 MinorDefaultIntMulFU(), MinorDefaultIntDivFU(), 169 MinorDefaultFloatSimdFU(), MinorDefaultMemFU(), 170 MinorDefaultMiscFU()] 171 172class MinorCPU(BaseCPU): 173 type = 'MinorCPU' 174 cxx_header = "cpu/minor/cpu.hh" 175 176 @classmethod 177 def memory_mode(cls): 178 return 'timing' 179 180 @classmethod 181 def require_caches(cls): 182 return True 183 184 @classmethod 185 def support_take_over(cls): 186 return True 187 188 fetch1FetchLimit = Param.Unsigned(1, 189 "Number of line fetches allowable in flight at once") 190 fetch1LineSnapWidth = Param.Unsigned(0, 191 "Fetch1 'line' fetch snap size in bytes" 192 " (0 means use system cache line size)") 193 fetch1LineWidth = Param.Unsigned(0, 194 "Fetch1 maximum fetch size in bytes (0 means use system cache" 195 " line size)") 196 fetch1ToFetch2ForwardDelay = Param.Cycles(1, 197 "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)") 198 fetch1ToFetch2BackwardDelay = Param.Cycles(1, 199 "Backward cycle delay from Fetch2 to Fetch1 for branch prediction" 200 " signalling (0 means in the same cycle, 1 mean the next cycle)") 201 202 fetch2InputBufferSize = Param.Unsigned(2, 203 "Size of input buffer to Fetch2 in cycles-worth of insts.") 204 fetch2ToDecodeForwardDelay = Param.Cycles(1, 205 "Forward cycle delay from Fetch2 to Decode (1 means next cycle)") 206 fetch2CycleInput = Param.Bool(True, 207 "Allow Fetch2 to cross input lines to generate full output each" 208 " cycle") 209 210 decodeInputBufferSize = Param.Unsigned(3, 211 "Size of input buffer to Decode in cycles-worth of insts.") 212 decodeToExecuteForwardDelay = Param.Cycles(1, 213 "Forward cycle delay from Decode to Execute (1 means next cycle)") 214 decodeInputWidth = Param.Unsigned(2, 215 "Width (in instructions) of input to Decode (and implicitly" 216 " Decode's own width)") 217 decodeCycleInput = Param.Bool(True, 218 "Allow Decode to pack instructions from more than one input cycle" 219 " to fill its output each cycle") 220 221 executeInputWidth = Param.Unsigned(2, 222 "Width (in instructions) of input to Execute") 223 executeCycleInput = Param.Bool(True, 224 "Allow Execute to use instructions from more than one input cycle" 225 " each cycle") 226 executeIssueLimit = Param.Unsigned(2, 227 "Number of issuable instructions in Execute each cycle") 228 executeMemoryIssueLimit = Param.Unsigned(1, 229 "Number of issuable memory instructions in Execute each cycle") 230 executeCommitLimit = Param.Unsigned(2, 231 "Number of committable instructions in Execute each cycle") 232 executeMemoryCommitLimit = Param.Unsigned(1, 233 "Number of committable memory references in Execute each cycle") 234 executeInputBufferSize = Param.Unsigned(7, 235 "Size of input buffer to Execute in cycles-worth of insts.") 236 executeMemoryWidth = Param.Unsigned(0, 237 "Width (and snap) in bytes of the data memory interface. (0 mean use" 238 " the system cacheLineSize)") 239 executeMaxAccessesInMemory = Param.Unsigned(2, 240 "Maximum number of concurrent accesses allowed to the memory system" 241 " from the dcache port") 242 executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2, 243 "Maximum number of stores that the store buffer can issue per cycle") 244 executeLSQRequestsQueueSize = Param.Unsigned(1, 245 "Size of LSQ requests queue (address translation queue)") 246 executeLSQTransfersQueueSize = Param.Unsigned(2, 247 "Size of LSQ transfers queue (memory transaction queue)") 248 executeLSQStoreBufferSize = Param.Unsigned(5, 249 "Size of LSQ store buffer") 250 executeBranchDelay = Param.Cycles(1, 251 "Delay from Execute deciding to branch and Fetch1 reacting" 252 " (1 means next cycle)") 253 254 executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(), 255 "FUlines for this processor") 256 257 executeSetTraceTimeOnCommit = Param.Bool(True, 258 "Set inst. trace times to be commit times") 259 executeSetTraceTimeOnIssue = Param.Bool(False, 260 "Set inst. trace times to be issue times") 261 262 executeAllowEarlyMemoryIssue = Param.Bool(True, 263 "Allow mem refs to be issued to the LSQ before reaching the head of" 264 " the in flight insts queue") 265 266 enableIdling = Param.Bool(True, 267 "Enable cycle skipping when the processor is idle\n"); 268 269 branchPred = Param.BranchPredictor(BranchPredictor( 270 numThreads = Parent.numThreads), "Branch Predictor") 271 272 def addCheckerCpu(self): 273 print "Checker not yet supported by MinorCPU" 274 exit(1) 275