x86_cpu.cc revision 10157:5c2ecad1a3c9
1/* 2 * Copyright (c) 2013 Andreas Sandberg 3 * All rights reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Andreas Sandberg 29 */ 30 31#include <linux/kvm.h> 32 33#include <algorithm> 34#include <cerrno> 35#include <memory> 36 37#include "arch/x86/regs/msr.hh" 38#include "arch/x86/cpuid.hh" 39#include "arch/x86/utility.hh" 40#include "arch/registers.hh" 41#include "cpu/kvm/base.hh" 42#include "cpu/kvm/x86_cpu.hh" 43#include "debug/Drain.hh" 44#include "debug/Kvm.hh" 45#include "debug/KvmContext.hh" 46#include "debug/KvmIO.hh" 47#include "debug/KvmInt.hh" 48 49using namespace X86ISA; 50 51#define MSR_TSC 0x10 52 53#define IO_PCI_CONF_ADDR 0xCF8 54#define IO_PCI_CONF_DATA_BASE 0xCFC 55 56// Task segment type of an inactive 32-bit or 64-bit task 57#define SEG_SYS_TYPE_TSS_AVAILABLE 9 58// Task segment type of an active 32-bit or 64-bit task 59#define SEG_SYS_TYPE_TSS_BUSY 11 60 61// Non-conforming accessed code segment 62#define SEG_CS_TYPE_ACCESSED 9 63// Non-conforming accessed code segment that can be read 64#define SEG_CS_TYPE_READ_ACCESSED 11 65 66// The lowest bit of the type field for normal segments (code and 67// data) is used to indicate that a segment has been accessed. 68#define SEG_TYPE_BIT_ACCESSED 1 69 70struct FXSave 71{ 72 uint16_t fcw; 73 uint16_t fsw; 74 uint8_t ftwx; 75 uint8_t pad0; 76 uint16_t last_opcode; 77 union { 78 struct { 79 uint32_t fpu_ip; 80 uint16_t fpu_cs; 81 uint16_t pad1; 82 uint32_t fpu_dp; 83 uint16_t fpu_ds; 84 uint16_t pad2; 85 } ctrl32; 86 87 struct { 88 uint64_t fpu_ip; 89 uint64_t fpu_dp; 90 } ctrl64; 91 }; 92 uint32_t mxcsr; 93 uint32_t mxcsr_mask; 94 95 uint8_t fpr[8][16]; 96 uint8_t xmm[16][16]; 97 98 uint64_t reserved[12]; 99} M5_ATTR_PACKED; 100 101static_assert(sizeof(FXSave) == 512, "Unexpected size of FXSave"); 102 103#define FOREACH_IREG() \ 104 do { \ 105 APPLY_IREG(rax, INTREG_RAX); \ 106 APPLY_IREG(rbx, INTREG_RBX); \ 107 APPLY_IREG(rcx, INTREG_RCX); \ 108 APPLY_IREG(rdx, INTREG_RDX); \ 109 APPLY_IREG(rsi, INTREG_RSI); \ 110 APPLY_IREG(rdi, INTREG_RDI); \ 111 APPLY_IREG(rsp, INTREG_RSP); \ 112 APPLY_IREG(rbp, INTREG_RBP); \ 113 APPLY_IREG(r8, INTREG_R8); \ 114 APPLY_IREG(r9, INTREG_R9); \ 115 APPLY_IREG(r10, INTREG_R10); \ 116 APPLY_IREG(r11, INTREG_R11); \ 117 APPLY_IREG(r12, INTREG_R12); \ 118 APPLY_IREG(r13, INTREG_R13); \ 119 APPLY_IREG(r14, INTREG_R14); \ 120 APPLY_IREG(r15, INTREG_R15); \ 121 } while(0) 122 123#define FOREACH_SREG() \ 124 do { \ 125 APPLY_SREG(cr0, MISCREG_CR0); \ 126 APPLY_SREG(cr2, MISCREG_CR2); \ 127 APPLY_SREG(cr3, MISCREG_CR3); \ 128 APPLY_SREG(cr4, MISCREG_CR4); \ 129 APPLY_SREG(cr8, MISCREG_CR8); \ 130 APPLY_SREG(efer, MISCREG_EFER); \ 131 APPLY_SREG(apic_base, MISCREG_APIC_BASE); \ 132 } while(0) 133 134#define FOREACH_DREG() \ 135 do { \ 136 APPLY_DREG(db[0], MISCREG_DR0); \ 137 APPLY_DREG(db[1], MISCREG_DR1); \ 138 APPLY_DREG(db[2], MISCREG_DR2); \ 139 APPLY_DREG(db[3], MISCREG_DR3); \ 140 APPLY_DREG(dr6, MISCREG_DR6); \ 141 APPLY_DREG(dr7, MISCREG_DR7); \ 142 } while(0) 143 144#define FOREACH_SEGMENT() \ 145 do { \ 146 APPLY_SEGMENT(cs, MISCREG_CS - MISCREG_SEG_SEL_BASE); \ 147 APPLY_SEGMENT(ds, MISCREG_DS - MISCREG_SEG_SEL_BASE); \ 148 APPLY_SEGMENT(es, MISCREG_ES - MISCREG_SEG_SEL_BASE); \ 149 APPLY_SEGMENT(fs, MISCREG_FS - MISCREG_SEG_SEL_BASE); \ 150 APPLY_SEGMENT(gs, MISCREG_GS - MISCREG_SEG_SEL_BASE); \ 151 APPLY_SEGMENT(ss, MISCREG_SS - MISCREG_SEG_SEL_BASE); \ 152 APPLY_SEGMENT(tr, MISCREG_TR - MISCREG_SEG_SEL_BASE); \ 153 APPLY_SEGMENT(ldt, MISCREG_TSL - MISCREG_SEG_SEL_BASE); \ 154 } while(0) 155 156#define FOREACH_DTABLE() \ 157 do { \ 158 APPLY_DTABLE(gdt, MISCREG_TSG - MISCREG_SEG_SEL_BASE); \ 159 APPLY_DTABLE(idt, MISCREG_IDTR - MISCREG_SEG_SEL_BASE); \ 160 } while(0) 161 162template<typename STRUCT, typename ENTRY> 163static STRUCT *newVarStruct(size_t entries) 164{ 165 return (STRUCT *)operator new(sizeof(STRUCT) + entries * sizeof(ENTRY)); 166} 167 168static void 169dumpKvm(const struct kvm_regs ®s) 170{ 171 inform("KVM register state:\n"); 172 173#define APPLY_IREG(kreg, mreg) \ 174 inform("\t" # kreg ": 0x%llx\n", regs.kreg) 175 176 FOREACH_IREG(); 177 178#undef APPLY_IREG 179 180 inform("\trip: 0x%llx\n", regs.rip); 181 inform("\trflags: 0x%llx\n", regs.rflags); 182} 183 184static void 185dumpKvm(const char *reg_name, const struct kvm_segment &seg) 186{ 187 inform("\t%s: @0x%llx+%x [sel: 0x%x, type: 0x%x]\n" 188 "\t\tpres.: %u, dpl: %u, db: %u, s: %u, l: %u, g: %u, avl: %u, unus.: %u\n", 189 reg_name, 190 seg.base, seg.limit, seg.selector, seg.type, 191 seg.present, seg.dpl, seg.db, seg.s, seg.l, seg.g, seg.avl, seg.unusable); 192} 193 194static void 195dumpKvm(const char *reg_name, const struct kvm_dtable &dtable) 196{ 197 inform("\t%s: @0x%llx+%x\n", 198 reg_name, dtable.base, dtable.limit); 199} 200 201static void 202dumpKvm(const struct kvm_sregs &sregs) 203{ 204#define APPLY_SREG(kreg, mreg) \ 205 inform("\t" # kreg ": 0x%llx\n", sregs.kreg); 206#define APPLY_SEGMENT(kreg, idx) \ 207 dumpKvm(# kreg, sregs.kreg); 208#define APPLY_DTABLE(kreg, idx) \ 209 dumpKvm(# kreg, sregs.kreg); 210 211 inform("Special registers:\n"); 212 FOREACH_SEGMENT(); 213 FOREACH_SREG(); 214 FOREACH_DTABLE(); 215 216 inform("Interrupt Bitmap:"); 217 for (int i = 0; i < KVM_NR_INTERRUPTS; i += 64) 218 inform(" 0x%.8x", sregs.interrupt_bitmap[i / 64]); 219 220#undef APPLY_SREG 221#undef APPLY_SEGMENT 222#undef APPLY_DTABLE 223} 224 225#ifdef KVM_GET_DEBUGREGS 226static void 227dumpKvm(const struct kvm_debugregs ®s) 228{ 229 inform("KVM debug state:\n"); 230 231#define APPLY_DREG(kreg, mreg) \ 232 inform("\t" # kreg ": 0x%llx\n", regs.kreg) 233 234 FOREACH_DREG(); 235 236#undef APPLY_DREG 237 238 inform("\tflags: 0x%llx\n", regs.flags); 239} 240#endif 241 242static void 243dumpFpuSpec(const struct FXSave &xs) 244{ 245 inform("\tlast_ip: 0x%x\n", xs.ctrl64.fpu_ip); 246 inform("\tlast_dp: 0x%x\n", xs.ctrl64.fpu_dp); 247 inform("\tmxcsr_mask: 0x%x\n", xs.mxcsr_mask); 248} 249 250static void 251dumpFpuSpec(const struct kvm_fpu &fpu) 252{ 253 inform("\tlast_ip: 0x%x\n", fpu.last_ip); 254 inform("\tlast_dp: 0x%x\n", fpu.last_dp); 255} 256 257template<typename T> 258static void 259dumpFpuCommon(const T &fpu) 260{ 261 const unsigned top((fpu.fsw >> 11) & 0x7); 262 inform("\tfcw: 0x%x\n", fpu.fcw); 263 264 inform("\tfsw: 0x%x (top: %i, " 265 "conditions: %s%s%s%s, exceptions: %s%s%s%s%s%s %s%s%s)\n", 266 fpu.fsw, top, 267 268 (fpu.fsw & CC0Bit) ? "C0" : "", 269 (fpu.fsw & CC1Bit) ? "C1" : "", 270 (fpu.fsw & CC2Bit) ? "C2" : "", 271 (fpu.fsw & CC3Bit) ? "C3" : "", 272 273 (fpu.fsw & IEBit) ? "I" : "", 274 (fpu.fsw & DEBit) ? "D" : "", 275 (fpu.fsw & ZEBit) ? "Z" : "", 276 (fpu.fsw & OEBit) ? "O" : "", 277 (fpu.fsw & UEBit) ? "U" : "", 278 (fpu.fsw & PEBit) ? "P" : "", 279 280 (fpu.fsw & StackFaultBit) ? "SF " : "", 281 (fpu.fsw & ErrSummaryBit) ? "ES " : "", 282 (fpu.fsw & BusyBit) ? "BUSY " : "" 283 ); 284 inform("\tftwx: 0x%x\n", fpu.ftwx); 285 inform("\tlast_opcode: 0x%x\n", fpu.last_opcode); 286 dumpFpuSpec(fpu); 287 inform("\tmxcsr: 0x%x\n", fpu.mxcsr); 288 inform("\tFP Stack:\n"); 289 for (int i = 0; i < 8; ++i) { 290 const unsigned reg_idx((i + top) & 0x7); 291 const bool empty(!((fpu.ftwx >> reg_idx) & 0x1)); 292 const double value(X86ISA::loadFloat80(fpu.fpr[i])); 293 char hex[33]; 294 for (int j = 0; j < 10; ++j) 295 snprintf(&hex[j*2], 3, "%.2x", fpu.fpr[i][j]); 296 inform("\t\tST%i/%i: 0x%s (%f)%s\n", i, reg_idx, 297 hex, value, empty ? " (e)" : ""); 298 } 299 inform("\tXMM registers:\n"); 300 for (int i = 0; i < 16; ++i) { 301 char hex[33]; 302 for (int j = 0; j < 16; ++j) 303 snprintf(&hex[j*2], 3, "%.2x", fpu.xmm[i][j]); 304 inform("\t\t%i: 0x%s\n", i, hex); 305 } 306} 307 308static void 309dumpKvm(const struct kvm_fpu &fpu) 310{ 311 inform("FPU registers:\n"); 312 dumpFpuCommon(fpu); 313} 314 315static void 316dumpKvm(const struct kvm_xsave &xsave) 317{ 318 inform("FPU registers (XSave):\n"); 319 dumpFpuCommon(*(FXSave *)xsave.region); 320} 321 322static void 323dumpKvm(const struct kvm_msrs &msrs) 324{ 325 inform("MSRs:\n"); 326 327 for (int i = 0; i < msrs.nmsrs; ++i) { 328 const struct kvm_msr_entry &e(msrs.entries[i]); 329 330 inform("\t0x%x: 0x%x\n", e.index, e.data); 331 } 332} 333 334static void 335dumpKvm(const struct kvm_xcrs ®s) 336{ 337 inform("KVM XCR registers:\n"); 338 339 inform("\tFlags: 0x%x\n", regs.flags); 340 for (int i = 0; i < regs.nr_xcrs; ++i) { 341 inform("\tXCR[0x%x]: 0x%x\n", 342 regs.xcrs[i].xcr, 343 regs.xcrs[i].value); 344 } 345} 346 347static void 348dumpKvm(const struct kvm_vcpu_events &events) 349{ 350 inform("vCPU events:\n"); 351 352 inform("\tException: [inj: %i, nr: %i, has_ec: %i, ec: %i]\n", 353 events.exception.injected, events.exception.nr, 354 events.exception.has_error_code, events.exception.error_code); 355 356 inform("\tInterrupt: [inj: %i, nr: %i, soft: %i]\n", 357 events.interrupt.injected, events.interrupt.nr, 358 events.interrupt.soft); 359 360 inform("\tNMI: [inj: %i, pending: %i, masked: %i]\n", 361 events.nmi.injected, events.nmi.pending, 362 events.nmi.masked); 363 364 inform("\tSIPI vector: 0x%x\n", events.sipi_vector); 365 inform("\tFlags: 0x%x\n", events.flags); 366} 367 368static bool 369isCanonicalAddress(uint64_t addr) 370{ 371 // x86-64 doesn't currently use the full 64-bit virtual address 372 // space, instead it uses signed 48 bit addresses that are 373 // sign-extended to 64 bits. Such addresses are known as 374 // "canonical". 375 uint64_t upper_half(addr & 0xffff800000000000ULL); 376 return upper_half == 0 || upper_half == 0xffff800000000000; 377} 378 379static void 380checkSeg(const char *name, const int idx, const struct kvm_segment &seg, 381 struct kvm_sregs sregs) 382{ 383 // Check the register base 384 switch (idx) { 385 case MISCREG_TSL: 386 case MISCREG_TR: 387 case MISCREG_FS: 388 case MISCREG_GS: 389 if (!isCanonicalAddress(seg.base)) 390 warn("Illegal %s base: 0x%x\n", name, seg.base); 391 break; 392 393 case MISCREG_SS: 394 case MISCREG_DS: 395 case MISCREG_ES: 396 if (seg.unusable) 397 break; 398 case MISCREG_CS: 399 if (seg.base & 0xffffffff00000000ULL) 400 warn("Illegal %s base: 0x%x\n", name, seg.base); 401 break; 402 } 403 404 // Check the type 405 switch (idx) { 406 case MISCREG_CS: 407 switch (seg.type) { 408 case 3: 409 if (seg.dpl != 0) 410 warn("CS type is 3 but dpl != 0.\n"); 411 break; 412 case 9: 413 case 11: 414 if (seg.dpl != sregs.ss.dpl) 415 warn("CS type is %i but CS DPL != SS DPL\n", seg.type); 416 break; 417 case 13: 418 case 15: 419 if (seg.dpl > sregs.ss.dpl) 420 warn("CS type is %i but CS DPL > SS DPL\n", seg.type); 421 break; 422 default: 423 warn("Illegal CS type: %i\n", seg.type); 424 break; 425 } 426 break; 427 428 case MISCREG_SS: 429 if (seg.unusable) 430 break; 431 switch (seg.type) { 432 case 3: 433 if (sregs.cs.type == 3 && seg.dpl != 0) 434 warn("CS type is 3, but SS DPL is != 0.\n"); 435 /* FALLTHROUGH */ 436 case 7: 437 if (!(sregs.cr0 & 1) && seg.dpl != 0) 438 warn("SS DPL is %i, but CR0 PE is 0\n", seg.dpl); 439 break; 440 default: 441 warn("Illegal SS type: %i\n", seg.type); 442 break; 443 } 444 break; 445 446 case MISCREG_DS: 447 case MISCREG_ES: 448 case MISCREG_FS: 449 case MISCREG_GS: 450 if (seg.unusable) 451 break; 452 if (!(seg.type & 0x1) || 453 ((seg.type & 0x8) && !(seg.type & 0x2))) 454 warn("%s has an illegal type field: %i\n", name, seg.type); 455 break; 456 457 case MISCREG_TR: 458 // TODO: We should check the CPU mode 459 if (seg.type != 3 && seg.type != 11) 460 warn("%s: Illegal segment type (%i)\n", name, seg.type); 461 break; 462 463 case MISCREG_TSL: 464 if (seg.unusable) 465 break; 466 if (seg.type != 2) 467 warn("%s: Illegal segment type (%i)\n", name, seg.type); 468 break; 469 } 470 471 switch (idx) { 472 case MISCREG_SS: 473 case MISCREG_DS: 474 case MISCREG_ES: 475 case MISCREG_FS: 476 case MISCREG_GS: 477 if (seg.unusable) 478 break; 479 case MISCREG_CS: 480 if (!seg.s) 481 warn("%s: S flag not set\n", name); 482 break; 483 484 case MISCREG_TSL: 485 if (seg.unusable) 486 break; 487 case MISCREG_TR: 488 if (seg.s) 489 warn("%s: S flag is set\n", name); 490 break; 491 } 492 493 switch (idx) { 494 case MISCREG_SS: 495 case MISCREG_DS: 496 case MISCREG_ES: 497 case MISCREG_FS: 498 case MISCREG_GS: 499 case MISCREG_TSL: 500 if (seg.unusable) 501 break; 502 case MISCREG_TR: 503 case MISCREG_CS: 504 if (!seg.present) 505 warn("%s: P flag not set\n", name); 506 507 if (((seg.limit & 0xFFF) == 0 && seg.g) || 508 ((seg.limit & 0xFFF00000) != 0 && !seg.g)) { 509 warn("%s limit (0x%x) and g (%i) combination is illegal.\n", 510 name, seg.limit, seg.g); 511 } 512 break; 513 } 514 515 // TODO: Check CS DB 516} 517 518X86KvmCPU::X86KvmCPU(X86KvmCPUParams *params) 519 : BaseKvmCPU(params), 520 useXSave(params->useXSave) 521{ 522 Kvm &kvm(vm.kvm); 523 524 if (!kvm.capSetTSSAddress()) 525 panic("KVM: Missing capability (KVM_CAP_SET_TSS_ADDR)\n"); 526 if (!kvm.capExtendedCPUID()) 527 panic("KVM: Missing capability (KVM_CAP_EXT_CPUID)\n"); 528 if (!kvm.capUserNMI()) 529 warn("KVM: Missing capability (KVM_CAP_USER_NMI)\n"); 530 if (!kvm.capVCPUEvents()) 531 warn("KVM: Missing capability (KVM_CAP_VCPU_EVENTS)\n"); 532 533 haveDebugRegs = kvm.capDebugRegs(); 534 haveXSave = kvm.capXSave(); 535 haveXCRs = kvm.capXCRs(); 536 537 if (useXSave && !haveXSave) { 538 warn("KVM: XSAVE not supported by host. MXCSR synchronization might be " 539 "unreliable due to kernel bugs.\n"); 540 useXSave = false; 541 } else if (!useXSave) { 542 warn("KVM: XSave FPU/SIMD synchronization disabled by user.\n"); 543 } 544} 545 546X86KvmCPU::~X86KvmCPU() 547{ 548} 549 550void 551X86KvmCPU::startup() 552{ 553 BaseKvmCPU::startup(); 554 555 updateCPUID(); 556 557 io_req.setThreadContext(tc->contextId(), 0); 558 559 // TODO: Do we need to create an identity mapped TSS area? We 560 // should call kvm.vm.setTSSAddress() here in that case. It should 561 // only be needed for old versions of the virtualization 562 // extensions. We should make sure that the identity range is 563 // reserved in the e820 memory map in that case. 564} 565 566void 567X86KvmCPU::dump() 568{ 569 dumpIntRegs(); 570 if (useXSave) 571 dumpXSave(); 572 else 573 dumpFpuRegs(); 574 dumpSpecRegs(); 575 dumpDebugRegs(); 576 dumpXCRs(); 577 dumpVCpuEvents(); 578 dumpMSRs(); 579} 580 581void 582X86KvmCPU::dumpFpuRegs() const 583{ 584 struct kvm_fpu fpu; 585 getFPUState(fpu); 586 dumpKvm(fpu); 587} 588 589void 590X86KvmCPU::dumpIntRegs() const 591{ 592 struct kvm_regs regs; 593 getRegisters(regs); 594 dumpKvm(regs); 595} 596 597void 598X86KvmCPU::dumpSpecRegs() const 599{ 600 struct kvm_sregs sregs; 601 getSpecialRegisters(sregs); 602 dumpKvm(sregs); 603} 604 605void 606X86KvmCPU::dumpDebugRegs() const 607{ 608 if (haveDebugRegs) { 609#ifdef KVM_GET_DEBUGREGS 610 struct kvm_debugregs dregs; 611 getDebugRegisters(dregs); 612 dumpKvm(dregs); 613#endif 614 } else { 615 inform("Debug registers not supported by kernel.\n"); 616 } 617} 618 619void 620X86KvmCPU::dumpXCRs() const 621{ 622 if (haveXCRs) { 623 struct kvm_xcrs xcrs; 624 getXCRs(xcrs); 625 dumpKvm(xcrs); 626 } else { 627 inform("XCRs not supported by kernel.\n"); 628 } 629} 630 631void 632X86KvmCPU::dumpXSave() const 633{ 634 if (haveXSave) { 635 struct kvm_xsave xsave; 636 getXSave(xsave); 637 dumpKvm(xsave); 638 } else { 639 inform("XSave not supported by kernel.\n"); 640 } 641} 642 643void 644X86KvmCPU::dumpVCpuEvents() const 645{ 646 struct kvm_vcpu_events events; 647 getVCpuEvents(events); 648 dumpKvm(events); 649} 650 651void 652X86KvmCPU::dumpMSRs() const 653{ 654 const Kvm::MSRIndexVector &supported_msrs(vm.kvm.getSupportedMSRs()); 655 std::unique_ptr<struct kvm_msrs> msrs( 656 newVarStruct<struct kvm_msrs, struct kvm_msr_entry>( 657 supported_msrs.size())); 658 659 msrs->nmsrs = supported_msrs.size(); 660 for (int i = 0; i < supported_msrs.size(); ++i) { 661 struct kvm_msr_entry &e(msrs->entries[i]); 662 e.index = supported_msrs[i]; 663 e.reserved = 0; 664 e.data = 0; 665 } 666 getMSRs(*msrs.get()); 667 668 dumpKvm(*msrs.get()); 669} 670 671void 672X86KvmCPU::updateKvmState() 673{ 674 updateKvmStateRegs(); 675 updateKvmStateSRegs(); 676 updateKvmStateFPU(); 677 updateKvmStateMSRs(); 678 679 DPRINTF(KvmContext, "X86KvmCPU::updateKvmState():\n"); 680 if (DTRACE(KvmContext)) 681 dump(); 682} 683 684void 685X86KvmCPU::updateKvmStateRegs() 686{ 687 struct kvm_regs regs; 688 689#define APPLY_IREG(kreg, mreg) regs.kreg = tc->readIntReg(mreg) 690 FOREACH_IREG(); 691#undef APPLY_IREG 692 693 regs.rip = tc->instAddr() - tc->readMiscReg(MISCREG_CS_BASE); 694 695 /* You might think that setting regs.rflags to the contents 696 * MISCREG_RFLAGS here would suffice. In that case you're 697 * mistaken. We need to reconstruct it from a bunch of ucode 698 * registers and wave a dead chicken over it (aka mask out and set 699 * reserved bits) to get it to work. 700 */ 701 regs.rflags = X86ISA::getRFlags(tc); 702 703 setRegisters(regs); 704} 705 706static inline void 707setKvmSegmentReg(ThreadContext *tc, struct kvm_segment &kvm_seg, 708 const int index) 709{ 710 SegAttr attr(tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(index))); 711 712 kvm_seg.base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(index)); 713 kvm_seg.limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(index)); 714 kvm_seg.selector = tc->readMiscRegNoEffect(MISCREG_SEG_SEL(index)); 715 kvm_seg.type = attr.type; 716 kvm_seg.present = attr.present; 717 kvm_seg.dpl = attr.dpl; 718 kvm_seg.db = attr.defaultSize; 719 kvm_seg.s = attr.system; 720 kvm_seg.l = attr.longMode; 721 kvm_seg.g = attr.granularity; 722 kvm_seg.avl = attr.avl; 723 724 // A segment is normally unusable when the selector is zero. There 725 // is a attr.unusable flag in gem5, but it seems unused. qemu 726 // seems to set this to 0 all the time, so we just do the same and 727 // hope for the best. 728 kvm_seg.unusable = 0; 729} 730 731static inline void 732setKvmDTableReg(ThreadContext *tc, struct kvm_dtable &kvm_dtable, 733 const int index) 734{ 735 kvm_dtable.base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(index)); 736 kvm_dtable.limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(index)); 737} 738 739static void 740forceSegAccessed(struct kvm_segment &seg) 741{ 742 // Intel's VMX requires that (some) usable segments are flagged as 743 // 'accessed' (i.e., the lowest bit in the segment type is set) 744 // when entering VMX. This wouldn't necessary be the case even if 745 // gem5 did set the access bits correctly, so we force it to one 746 // in that case. 747 if (!seg.unusable) 748 seg.type |= SEG_TYPE_BIT_ACCESSED; 749} 750 751void 752X86KvmCPU::updateKvmStateSRegs() 753{ 754 struct kvm_sregs sregs; 755 756#define APPLY_SREG(kreg, mreg) sregs.kreg = tc->readMiscRegNoEffect(mreg) 757#define APPLY_SEGMENT(kreg, idx) setKvmSegmentReg(tc, sregs.kreg, idx) 758#define APPLY_DTABLE(kreg, idx) setKvmDTableReg(tc, sregs.kreg, idx) 759 760 FOREACH_SREG(); 761 FOREACH_SEGMENT(); 762 FOREACH_DTABLE(); 763 764#undef APPLY_SREG 765#undef APPLY_SEGMENT 766#undef APPLY_DTABLE 767 768 // Clear the interrupt bitmap 769 memset(&sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); 770 771 // VMX requires CS, SS, DS, ES, FS, and GS to have the accessed 772 // bit in the type field set. 773 forceSegAccessed(sregs.cs); 774 forceSegAccessed(sregs.ss); 775 forceSegAccessed(sregs.ds); 776 forceSegAccessed(sregs.es); 777 forceSegAccessed(sregs.fs); 778 forceSegAccessed(sregs.gs); 779 780 // There are currently some cases where the active task isn't 781 // marked as busy. This is illegal in VMX, so we force it to busy. 782 if (sregs.tr.type == SEG_SYS_TYPE_TSS_AVAILABLE) { 783 hack("tr.type (%i) is not busy. Forcing the busy bit.\n", 784 sregs.tr.type); 785 sregs.tr.type = SEG_SYS_TYPE_TSS_BUSY; 786 } 787 788 // VMX requires the DPL of SS and CS to be the same for 789 // non-conforming code segments. It seems like m5 doesn't set the 790 // DPL of SS correctly when taking interrupts, so we need to fix 791 // that here. 792 if ((sregs.cs.type == SEG_CS_TYPE_ACCESSED || 793 sregs.cs.type == SEG_CS_TYPE_READ_ACCESSED) && 794 sregs.cs.dpl != sregs.ss.dpl) { 795 796 hack("CS.DPL (%i) != SS.DPL (%i): Forcing SS.DPL to %i\n", 797 sregs.cs.dpl, sregs.ss.dpl, sregs.cs.dpl); 798 sregs.ss.dpl = sregs.cs.dpl; 799 } 800 801 // Do checks after fixing up the state to avoid getting excessive 802 // amounts of warnings. 803 RFLAGS rflags_nocc(tc->readMiscReg(MISCREG_RFLAGS)); 804 if (!rflags_nocc.vm) { 805 // Do segment verification if the CPU isn't entering virtual 806 // 8086 mode. We currently assume that unrestricted guest 807 // mode is available. 808 809#define APPLY_SEGMENT(kreg, idx) \ 810 checkSeg(# kreg, idx + MISCREG_SEG_SEL_BASE, sregs.kreg, sregs) 811 812 FOREACH_SEGMENT(); 813#undef APPLY_SEGMENT 814 } 815 816 setSpecialRegisters(sregs); 817} 818 819template <typename T> 820static void 821updateKvmStateFPUCommon(ThreadContext *tc, T &fpu) 822{ 823 static_assert(sizeof(X86ISA::FloatRegBits) == 8, 824 "Unexpected size of X86ISA::FloatRegBits"); 825 826 fpu.mxcsr = tc->readMiscRegNoEffect(MISCREG_MXCSR); 827 fpu.fcw = tc->readMiscRegNoEffect(MISCREG_FCW); 828 // No need to rebuild from MISCREG_FSW and MISCREG_TOP if we read 829 // with effects. 830 fpu.fsw = tc->readMiscReg(MISCREG_FSW); 831 832 uint64_t ftw(tc->readMiscRegNoEffect(MISCREG_FTW)); 833 fpu.ftwx = X86ISA::convX87TagsToXTags(ftw); 834 835 fpu.last_opcode = tc->readMiscRegNoEffect(MISCREG_FOP); 836 837 const unsigned top((fpu.fsw >> 11) & 0x7); 838 for (int i = 0; i < 8; ++i) { 839 const unsigned reg_idx((i + top) & 0x7); 840 const double value(tc->readFloatReg(FLOATREG_FPR(reg_idx))); 841 DPRINTF(KvmContext, "Setting KVM FP reg %i (st[%i]) := %f\n", 842 reg_idx, i, value); 843 X86ISA::storeFloat80(fpu.fpr[i], value); 844 } 845 846 // TODO: We should update the MMX state 847 848 for (int i = 0; i < 16; ++i) { 849 *(X86ISA::FloatRegBits *)&fpu.xmm[i][0] = 850 tc->readFloatRegBits(FLOATREG_XMM_LOW(i)); 851 *(X86ISA::FloatRegBits *)&fpu.xmm[i][8] = 852 tc->readFloatRegBits(FLOATREG_XMM_HIGH(i)); 853 } 854} 855 856void 857X86KvmCPU::updateKvmStateFPULegacy() 858{ 859 struct kvm_fpu fpu; 860 861 // There is some padding in the FP registers, so we'd better zero 862 // the whole struct. 863 memset(&fpu, 0, sizeof(fpu)); 864 865 updateKvmStateFPUCommon(tc, fpu); 866 867 if (tc->readMiscRegNoEffect(MISCREG_FISEG)) 868 warn_once("MISCREG_FISEG is non-zero.\n"); 869 870 fpu.last_ip = tc->readMiscRegNoEffect(MISCREG_FIOFF); 871 872 if (tc->readMiscRegNoEffect(MISCREG_FOSEG)) 873 warn_once("MISCREG_FOSEG is non-zero.\n"); 874 875 fpu.last_dp = tc->readMiscRegNoEffect(MISCREG_FOOFF); 876 877 setFPUState(fpu); 878} 879 880void 881X86KvmCPU::updateKvmStateFPUXSave() 882{ 883 struct kvm_xsave kxsave; 884 FXSave &xsave(*(FXSave *)kxsave.region); 885 886 // There is some padding and reserved fields in the structure, so 887 // we'd better zero the whole thing. 888 memset(&kxsave, 0, sizeof(kxsave)); 889 890 updateKvmStateFPUCommon(tc, xsave); 891 892 if (tc->readMiscRegNoEffect(MISCREG_FISEG)) 893 warn_once("MISCREG_FISEG is non-zero.\n"); 894 895 xsave.ctrl64.fpu_ip = tc->readMiscRegNoEffect(MISCREG_FIOFF); 896 897 if (tc->readMiscRegNoEffect(MISCREG_FOSEG)) 898 warn_once("MISCREG_FOSEG is non-zero.\n"); 899 900 xsave.ctrl64.fpu_dp = tc->readMiscRegNoEffect(MISCREG_FOOFF); 901 902 setXSave(kxsave); 903} 904 905void 906X86KvmCPU::updateKvmStateFPU() 907{ 908 if (useXSave) 909 updateKvmStateFPUXSave(); 910 else 911 updateKvmStateFPULegacy(); 912} 913 914void 915X86KvmCPU::updateKvmStateMSRs() 916{ 917 KvmMSRVector msrs; 918 919 const Kvm::MSRIndexVector &indices(getMsrIntersection()); 920 921 for (auto it = indices.cbegin(); it != indices.cend(); ++it) { 922 struct kvm_msr_entry e; 923 924 e.index = *it; 925 e.reserved = 0; 926 e.data = tc->readMiscReg(msrMap.at(*it)); 927 DPRINTF(KvmContext, "Adding MSR: idx: 0x%x, data: 0x%x\n", 928 e.index, e.data); 929 930 msrs.push_back(e); 931 } 932 933 setMSRs(msrs); 934} 935 936void 937X86KvmCPU::updateThreadContext() 938{ 939 struct kvm_regs regs; 940 struct kvm_sregs sregs; 941 942 getRegisters(regs); 943 getSpecialRegisters(sregs); 944 945 DPRINTF(KvmContext, "X86KvmCPU::updateThreadContext():\n"); 946 if (DTRACE(KvmContext)) 947 dump(); 948 949 updateThreadContextRegs(regs, sregs); 950 updateThreadContextSRegs(sregs); 951 if (useXSave) { 952 struct kvm_xsave xsave; 953 getXSave(xsave); 954 955 updateThreadContextXSave(xsave); 956 } else { 957 struct kvm_fpu fpu; 958 getFPUState(fpu); 959 960 updateThreadContextFPU(fpu); 961 } 962 updateThreadContextMSRs(); 963 964 // The M5 misc reg caches some values from other 965 // registers. Writing to it with side effects causes it to be 966 // updated from its source registers. 967 tc->setMiscReg(MISCREG_M5_REG, 0); 968} 969 970void 971X86KvmCPU::updateThreadContextRegs(const struct kvm_regs ®s, 972 const struct kvm_sregs &sregs) 973{ 974#define APPLY_IREG(kreg, mreg) tc->setIntReg(mreg, regs.kreg) 975 976 FOREACH_IREG(); 977 978#undef APPLY_IREG 979 980 tc->pcState(PCState(regs.rip + sregs.cs.base)); 981 982 // Flags are spread out across multiple semi-magic registers so we 983 // need some special care when updating them. 984 X86ISA::setRFlags(tc, regs.rflags); 985} 986 987 988inline void 989setContextSegment(ThreadContext *tc, const struct kvm_segment &kvm_seg, 990 const int index) 991{ 992 SegAttr attr(0); 993 994 attr.type = kvm_seg.type; 995 attr.present = kvm_seg.present; 996 attr.dpl = kvm_seg.dpl; 997 attr.defaultSize = kvm_seg.db; 998 attr.system = kvm_seg.s; 999 attr.longMode = kvm_seg.l; 1000 attr.granularity = kvm_seg.g; 1001 attr.avl = kvm_seg.avl; 1002 attr.unusable = kvm_seg.unusable; 1003 1004 // We need some setMiscReg magic here to keep the effective base 1005 // addresses in sync. We need an up-to-date version of EFER, so 1006 // make sure this is called after the sregs have been synced. 1007 tc->setMiscReg(MISCREG_SEG_BASE(index), kvm_seg.base); 1008 tc->setMiscReg(MISCREG_SEG_LIMIT(index), kvm_seg.limit); 1009 tc->setMiscReg(MISCREG_SEG_SEL(index), kvm_seg.selector); 1010 tc->setMiscReg(MISCREG_SEG_ATTR(index), attr); 1011} 1012 1013inline void 1014setContextSegment(ThreadContext *tc, const struct kvm_dtable &kvm_dtable, 1015 const int index) 1016{ 1017 // We need some setMiscReg magic here to keep the effective base 1018 // addresses in sync. We need an up-to-date version of EFER, so 1019 // make sure this is called after the sregs have been synced. 1020 tc->setMiscReg(MISCREG_SEG_BASE(index), kvm_dtable.base); 1021 tc->setMiscReg(MISCREG_SEG_LIMIT(index), kvm_dtable.limit); 1022} 1023 1024void 1025X86KvmCPU::updateThreadContextSRegs(const struct kvm_sregs &sregs) 1026{ 1027 assert(getKvmRunState()->apic_base == sregs.apic_base); 1028 assert(getKvmRunState()->cr8 == sregs.cr8); 1029 1030#define APPLY_SREG(kreg, mreg) tc->setMiscRegNoEffect(mreg, sregs.kreg) 1031#define APPLY_SEGMENT(kreg, idx) setContextSegment(tc, sregs.kreg, idx) 1032#define APPLY_DTABLE(kreg, idx) setContextSegment(tc, sregs.kreg, idx) 1033 FOREACH_SREG(); 1034 FOREACH_SEGMENT(); 1035 FOREACH_DTABLE(); 1036#undef APPLY_SREG 1037#undef APPLY_SEGMENT 1038#undef APPLY_DTABLE 1039} 1040 1041template<typename T> 1042static void 1043updateThreadContextFPUCommon(ThreadContext *tc, const T &fpu) 1044{ 1045 const unsigned top((fpu.fsw >> 11) & 0x7); 1046 1047 static_assert(sizeof(X86ISA::FloatRegBits) == 8, 1048 "Unexpected size of X86ISA::FloatRegBits"); 1049 1050 for (int i = 0; i < 8; ++i) { 1051 const unsigned reg_idx((i + top) & 0x7); 1052 const double value(X86ISA::loadFloat80(fpu.fpr[i])); 1053 DPRINTF(KvmContext, "Setting gem5 FP reg %i (st[%i]) := %f\n", 1054 reg_idx, i, value); 1055 tc->setFloatReg(FLOATREG_FPR(reg_idx), value); 1056 } 1057 1058 // TODO: We should update the MMX state 1059 1060 tc->setMiscRegNoEffect(MISCREG_X87_TOP, top); 1061 tc->setMiscRegNoEffect(MISCREG_MXCSR, fpu.mxcsr); 1062 tc->setMiscRegNoEffect(MISCREG_FCW, fpu.fcw); 1063 tc->setMiscRegNoEffect(MISCREG_FSW, fpu.fsw); 1064 1065 uint64_t ftw(convX87XTagsToTags(fpu.ftwx)); 1066 // TODO: Are these registers really the same? 1067 tc->setMiscRegNoEffect(MISCREG_FTW, ftw); 1068 tc->setMiscRegNoEffect(MISCREG_FTAG, ftw); 1069 1070 tc->setMiscRegNoEffect(MISCREG_FOP, fpu.last_opcode); 1071 1072 for (int i = 0; i < 16; ++i) { 1073 tc->setFloatRegBits(FLOATREG_XMM_LOW(i), 1074 *(X86ISA::FloatRegBits *)&fpu.xmm[i][0]); 1075 tc->setFloatRegBits(FLOATREG_XMM_HIGH(i), 1076 *(X86ISA::FloatRegBits *)&fpu.xmm[i][8]); 1077 } 1078} 1079 1080void 1081X86KvmCPU::updateThreadContextFPU(const struct kvm_fpu &fpu) 1082{ 1083 updateThreadContextFPUCommon(tc, fpu); 1084 1085 tc->setMiscRegNoEffect(MISCREG_FISEG, 0); 1086 tc->setMiscRegNoEffect(MISCREG_FIOFF, fpu.last_ip); 1087 tc->setMiscRegNoEffect(MISCREG_FOSEG, 0); 1088 tc->setMiscRegNoEffect(MISCREG_FOOFF, fpu.last_dp); 1089} 1090 1091void 1092X86KvmCPU::updateThreadContextXSave(const struct kvm_xsave &kxsave) 1093{ 1094 const FXSave &xsave(*(const FXSave *)kxsave.region); 1095 1096 updateThreadContextFPUCommon(tc, xsave); 1097 1098 tc->setMiscRegNoEffect(MISCREG_FISEG, 0); 1099 tc->setMiscRegNoEffect(MISCREG_FIOFF, xsave.ctrl64.fpu_ip); 1100 tc->setMiscRegNoEffect(MISCREG_FOSEG, 0); 1101 tc->setMiscRegNoEffect(MISCREG_FOOFF, xsave.ctrl64.fpu_dp); 1102} 1103 1104void 1105X86KvmCPU::updateThreadContextMSRs() 1106{ 1107 const Kvm::MSRIndexVector &msrs(getMsrIntersection()); 1108 1109 std::unique_ptr<struct kvm_msrs> kvm_msrs( 1110 newVarStruct<struct kvm_msrs, struct kvm_msr_entry>(msrs.size())); 1111 struct kvm_msr_entry *entry; 1112 1113 // Create a list of MSRs to read 1114 kvm_msrs->nmsrs = msrs.size(); 1115 entry = &kvm_msrs->entries[0]; 1116 for (auto it = msrs.cbegin(); it != msrs.cend(); ++it, ++entry) { 1117 entry->index = *it; 1118 entry->reserved = 0; 1119 entry->data = 0; 1120 } 1121 1122 getMSRs(*kvm_msrs.get()); 1123 1124 // Update M5's state 1125 entry = &kvm_msrs->entries[0]; 1126 for (int i = 0; i < kvm_msrs->nmsrs; ++i, ++entry) { 1127 DPRINTF(KvmContext, "Setting M5 MSR: idx: 0x%x, data: 0x%x\n", 1128 entry->index, entry->data); 1129 1130 tc->setMiscReg(X86ISA::msrMap.at(entry->index), entry->data); 1131 } 1132} 1133 1134void 1135X86KvmCPU::deliverInterrupts() 1136{ 1137 Fault fault; 1138 1139 syncThreadContext(); 1140 1141 { 1142 // Migrate to the interrupt controller's thread to get the 1143 // interrupt. Even though the individual methods are safe to 1144 // call across threads, we might still lose interrupts unless 1145 // they are getInterrupt() and updateIntrInfo() are called 1146 // atomically. 1147 EventQueue::ScopedMigration migrate(interrupts->eventQueue()); 1148 fault = interrupts->getInterrupt(tc); 1149 interrupts->updateIntrInfo(tc); 1150 } 1151 1152 X86Interrupt *x86int(dynamic_cast<X86Interrupt *>(fault.get())); 1153 if (dynamic_cast<NonMaskableInterrupt *>(fault.get())) { 1154 DPRINTF(KvmInt, "Delivering NMI\n"); 1155 kvmNonMaskableInterrupt(); 1156 } else if (dynamic_cast<InitInterrupt *>(fault.get())) { 1157 DPRINTF(KvmInt, "INIT interrupt\n"); 1158 fault.get()->invoke(tc); 1159 // Delay the kvm state update since we won't enter KVM on this 1160 // tick. 1161 threadContextDirty = true; 1162 // HACK: gem5 doesn't actually have any BIOS code, which means 1163 // that we need to halt the thread and wait for a startup 1164 // interrupt before restarting the thread. The simulated CPUs 1165 // use the same kind of hack using a microcode routine. 1166 thread->suspend(); 1167 } else if (dynamic_cast<StartupInterrupt *>(fault.get())) { 1168 DPRINTF(KvmInt, "STARTUP interrupt\n"); 1169 fault.get()->invoke(tc); 1170 // The kvm state is assumed to have been updated when entering 1171 // kvmRun(), so we need to update manually it here. 1172 updateKvmState(); 1173 } else if (x86int) { 1174 struct kvm_interrupt kvm_int; 1175 kvm_int.irq = x86int->getVector(); 1176 1177 DPRINTF(KvmInt, "Delivering interrupt: %s (%u)\n", 1178 fault->name(), kvm_int.irq); 1179 1180 kvmInterrupt(kvm_int); 1181 } else { 1182 panic("KVM: Unknown interrupt type\n"); 1183 } 1184 1185} 1186 1187Tick 1188X86KvmCPU::kvmRun(Tick ticks) 1189{ 1190 struct kvm_run &kvm_run(*getKvmRunState()); 1191 1192 if (interrupts->checkInterruptsRaw()) { 1193 if (interrupts->hasPendingUnmaskable()) { 1194 DPRINTF(KvmInt, 1195 "Delivering unmaskable interrupt.\n"); 1196 syncThreadContext(); 1197 deliverInterrupts(); 1198 } else if (kvm_run.ready_for_interrupt_injection) { 1199 // KVM claims that it is ready for an interrupt. It might 1200 // be lying if we just updated rflags and disabled 1201 // interrupts (e.g., by doing a CPU handover). Let's sync 1202 // the thread context and check if there are /really/ 1203 // interrupts that should be delivered now. 1204 syncThreadContext(); 1205 if (interrupts->checkInterrupts(tc)) { 1206 DPRINTF(KvmInt, 1207 "M5 has pending interrupts, delivering interrupt.\n"); 1208 1209 deliverInterrupts(); 1210 } else { 1211 DPRINTF(KvmInt, 1212 "Interrupt delivery delayed due to KVM confusion.\n"); 1213 kvm_run.request_interrupt_window = 1; 1214 } 1215 } else if (!kvm_run.request_interrupt_window) { 1216 DPRINTF(KvmInt, 1217 "M5 has pending interrupts, requesting interrupt " 1218 "window.\n"); 1219 kvm_run.request_interrupt_window = 1; 1220 } 1221 } else { 1222 kvm_run.request_interrupt_window = 0; 1223 } 1224 1225 // The CPU might have been suspended as a result of the INIT 1226 // interrupt delivery hack. In that case, don't enter into KVM. 1227 if (_status == Idle) 1228 return 0; 1229 else 1230 return kvmRunWrapper(ticks); 1231} 1232 1233Tick 1234X86KvmCPU::kvmRunDrain() 1235{ 1236 struct kvm_run &kvm_run(*getKvmRunState()); 1237 1238 if (!archIsDrained()) { 1239 DPRINTF(Drain, "kvmRunDrain: Architecture code isn't drained\n"); 1240 1241 // Tell KVM to find a suitable place to deliver interrupts. This 1242 // should ensure that pending interrupts have been delivered and 1243 // things are reasonably consistent (i.e., no interrupts pending 1244 // in the guest). 1245 kvm_run.request_interrupt_window = 1; 1246 1247 // Limit the run to 1 millisecond. That is hopefully enough to 1248 // reach an interrupt window. Otherwise, we'll just try again 1249 // later. 1250 return kvmRunWrapper(1 * SimClock::Float::ms); 1251 } else { 1252 DPRINTF(Drain, "kvmRunDrain: Delivering pending IO\n"); 1253 1254 return kvmRunWrapper(0); 1255 } 1256} 1257 1258Tick 1259X86KvmCPU::kvmRunWrapper(Tick ticks) 1260{ 1261 struct kvm_run &kvm_run(*getKvmRunState()); 1262 1263 // Synchronize the APIC base and CR8 here since they are present 1264 // in the kvm_run struct, which makes the synchronization really 1265 // cheap. 1266 kvm_run.apic_base = tc->readMiscReg(MISCREG_APIC_BASE); 1267 kvm_run.cr8 = tc->readMiscReg(MISCREG_CR8); 1268 1269 const Tick run_ticks(BaseKvmCPU::kvmRun(ticks)); 1270 1271 tc->setMiscReg(MISCREG_APIC_BASE, kvm_run.apic_base); 1272 kvm_run.cr8 = tc->readMiscReg(MISCREG_CR8); 1273 1274 return run_ticks; 1275} 1276 1277uint64_t 1278X86KvmCPU::getHostCycles() const 1279{ 1280 return getMSR(MSR_TSC); 1281} 1282 1283void 1284X86KvmCPU::handleIOMiscReg32(int miscreg) 1285{ 1286 struct kvm_run &kvm_run(*getKvmRunState()); 1287 const uint16_t port(kvm_run.io.port); 1288 1289 assert(kvm_run.exit_reason == KVM_EXIT_IO); 1290 1291 if (kvm_run.io.size != 4) { 1292 panic("Unexpected IO size (%u) for address 0x%x.\n", 1293 kvm_run.io.size, port); 1294 } 1295 1296 if (kvm_run.io.count != 1) { 1297 panic("Unexpected IO count (%u) for address 0x%x.\n", 1298 kvm_run.io.count, port); 1299 } 1300 1301 uint32_t *data((uint32_t *)getGuestData(kvm_run.io.data_offset)); 1302 if (kvm_run.io.direction == KVM_EXIT_IO_OUT) 1303 tc->setMiscReg(miscreg, *data); 1304 else 1305 *data = tc->readMiscRegNoEffect(miscreg); 1306} 1307 1308Tick 1309X86KvmCPU::handleKvmExitIO() 1310{ 1311 struct kvm_run &kvm_run(*getKvmRunState()); 1312 bool isWrite(kvm_run.io.direction == KVM_EXIT_IO_OUT); 1313 unsigned char *guestData(getGuestData(kvm_run.io.data_offset)); 1314 Tick delay(0); 1315 uint16_t port(kvm_run.io.port); 1316 Addr pAddr; 1317 const int count(kvm_run.io.count); 1318 1319 assert(kvm_run.io.direction == KVM_EXIT_IO_IN || 1320 kvm_run.io.direction == KVM_EXIT_IO_OUT); 1321 1322 DPRINTF(KvmIO, "KVM-x86: Handling IO instruction (%s) (port: 0x%x)\n", 1323 (isWrite ? "out" : "in"), kvm_run.io.port); 1324 1325 /* Vanilla gem5 handles PCI discovery in the TLB(!). Since we 1326 * don't use the TLB component, we need to intercept and handle 1327 * the PCI configuration space IO ports here. 1328 * 1329 * The IO port PCI discovery mechanism uses one address register 1330 * and one data register. We map the address register to a misc 1331 * reg and use that to re-route data register accesses to the 1332 * right location in the PCI configuration space. 1333 */ 1334 if (port == IO_PCI_CONF_ADDR) { 1335 handleIOMiscReg32(MISCREG_PCI_CONFIG_ADDRESS); 1336 return 0; 1337 } else if ((port & ~0x3) == IO_PCI_CONF_DATA_BASE) { 1338 Addr pciConfigAddr(tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS)); 1339 if (pciConfigAddr & 0x80000000) { 1340 pAddr = X86ISA::x86PciConfigAddress((pciConfigAddr & 0x7ffffffc) | 1341 (port & 0x3)); 1342 } else { 1343 pAddr = X86ISA::x86IOAddress(port); 1344 } 1345 } else { 1346 pAddr = X86ISA::x86IOAddress(port); 1347 } 1348 1349 io_req.setPhys(pAddr, kvm_run.io.size, Request::UNCACHEABLE, 1350 dataMasterId()); 1351 1352 const MemCmd cmd(isWrite ? MemCmd::WriteReq : MemCmd::ReadReq); 1353 // Temporarily lock and migrate to the event queue of the 1354 // VM. This queue is assumed to "own" all devices we need to 1355 // access if running in multi-core mode. 1356 EventQueue::ScopedMigration migrate(vm.eventQueue()); 1357 for (int i = 0; i < count; ++i) { 1358 Packet pkt(&io_req, cmd); 1359 1360 pkt.dataStatic(guestData); 1361 delay += dataPort.sendAtomic(&pkt); 1362 1363 guestData += kvm_run.io.size; 1364 } 1365 1366 return delay; 1367} 1368 1369Tick 1370X86KvmCPU::handleKvmExitIRQWindowOpen() 1371{ 1372 // We don't need to do anything here since this is caught the next 1373 // time we execute kvmRun(). We still overload the exit event to 1374 // silence the warning about an unhandled exit event. 1375 return 0; 1376} 1377 1378bool 1379X86KvmCPU::archIsDrained() const 1380{ 1381 struct kvm_vcpu_events events; 1382 1383 getVCpuEvents(events); 1384 1385 // We could probably handle this in a by re-inserting interrupts 1386 // that are pending into gem5 on a drain. However, that would 1387 // probably be tricky to do reliably, so we'll just prevent a 1388 // drain if there is anything pending in the 1389 // guest. X86KvmCPU::kvmRunDrain() minimizes the amount of code 1390 // executed in the guest by requesting an interrupt window if 1391 // there are pending interrupts. 1392 const bool pending_events(events.exception.injected || 1393 events.interrupt.injected || 1394 events.nmi.injected || events.nmi.pending); 1395 1396 if (pending_events) { 1397 DPRINTF(Drain, "archIsDrained: Pending events: %s %s %s %s\n", 1398 events.exception.injected ? "exception" : "", 1399 events.interrupt.injected ? "interrupt" : "", 1400 events.nmi.injected ? "nmi[i]" : "", 1401 events.nmi.pending ? "nmi[p]" : ""); 1402 } 1403 1404 return !pending_events; 1405} 1406 1407static struct kvm_cpuid_entry2 1408makeKvmCpuid(uint32_t function, uint32_t index, 1409 CpuidResult &result) 1410{ 1411 struct kvm_cpuid_entry2 e; 1412 e.function = function; 1413 e.index = index; 1414 e.flags = 0; 1415 e.eax = (uint32_t)result.rax; 1416 e.ebx = (uint32_t)result.rbx; 1417 e.ecx = (uint32_t)result.rcx; 1418 e.edx = (uint32_t)result.rdx; 1419 1420 return e; 1421} 1422 1423void 1424X86KvmCPU::updateCPUID() 1425{ 1426 Kvm::CPUIDVector m5_supported; 1427 1428 /* TODO: We currently don't support any of the functions that 1429 * iterate through data structures in the CPU using an index. It's 1430 * currently not a problem since M5 doesn't expose any of them at 1431 * the moment. 1432 */ 1433 1434 /* Basic features */ 1435 CpuidResult func0; 1436 X86ISA::doCpuid(tc, 0x0, 0, func0); 1437 for (uint32_t function = 0; function <= func0.rax; ++function) { 1438 CpuidResult cpuid; 1439 uint32_t idx(0); 1440 1441 X86ISA::doCpuid(tc, function, idx, cpuid); 1442 m5_supported.push_back(makeKvmCpuid(function, idx, cpuid)); 1443 } 1444 1445 /* Extended features */ 1446 CpuidResult efunc0; 1447 X86ISA::doCpuid(tc, 0x80000000, 0, efunc0); 1448 for (uint32_t function = 0x80000000; function <= efunc0.rax; ++function) { 1449 CpuidResult cpuid; 1450 uint32_t idx(0); 1451 1452 X86ISA::doCpuid(tc, function, idx, cpuid); 1453 m5_supported.push_back(makeKvmCpuid(function, idx, cpuid)); 1454 } 1455 1456 setCPUID(m5_supported); 1457} 1458 1459void 1460X86KvmCPU::setCPUID(const struct kvm_cpuid2 &cpuid) 1461{ 1462 if (ioctl(KVM_SET_CPUID2, (void *)&cpuid) == -1) 1463 panic("KVM: Failed to set guest CPUID2 (errno: %i)\n", 1464 errno); 1465} 1466 1467void 1468X86KvmCPU::setCPUID(const Kvm::CPUIDVector &cpuid) 1469{ 1470 std::unique_ptr<struct kvm_cpuid2> kvm_cpuid( 1471 newVarStruct<struct kvm_cpuid2, struct kvm_cpuid_entry2>(cpuid.size())); 1472 1473 kvm_cpuid->nent = cpuid.size(); 1474 std::copy(cpuid.begin(), cpuid.end(), kvm_cpuid->entries); 1475 1476 setCPUID(*kvm_cpuid); 1477} 1478 1479void 1480X86KvmCPU::setMSRs(const struct kvm_msrs &msrs) 1481{ 1482 if (ioctl(KVM_SET_MSRS, (void *)&msrs) == -1) 1483 panic("KVM: Failed to set guest MSRs (errno: %i)\n", 1484 errno); 1485} 1486 1487void 1488X86KvmCPU::setMSRs(const KvmMSRVector &msrs) 1489{ 1490 std::unique_ptr<struct kvm_msrs> kvm_msrs( 1491 newVarStruct<struct kvm_msrs, struct kvm_msr_entry>(msrs.size())); 1492 1493 kvm_msrs->nmsrs = msrs.size(); 1494 std::copy(msrs.begin(), msrs.end(), kvm_msrs->entries); 1495 1496 setMSRs(*kvm_msrs); 1497} 1498 1499void 1500X86KvmCPU::getMSRs(struct kvm_msrs &msrs) const 1501{ 1502 if (ioctl(KVM_GET_MSRS, (void *)&msrs) == -1) 1503 panic("KVM: Failed to get guest MSRs (errno: %i)\n", 1504 errno); 1505} 1506 1507 1508void 1509X86KvmCPU::setMSR(uint32_t index, uint64_t value) 1510{ 1511 std::unique_ptr<struct kvm_msrs> kvm_msrs( 1512 newVarStruct<struct kvm_msrs, struct kvm_msr_entry>(1)); 1513 struct kvm_msr_entry &entry(kvm_msrs->entries[0]); 1514 1515 kvm_msrs->nmsrs = 1; 1516 entry.index = index; 1517 entry.reserved = 0; 1518 entry.data = value; 1519 1520 setMSRs(*kvm_msrs.get()); 1521} 1522 1523uint64_t 1524X86KvmCPU::getMSR(uint32_t index) const 1525{ 1526 std::unique_ptr<struct kvm_msrs> kvm_msrs( 1527 newVarStruct<struct kvm_msrs, struct kvm_msr_entry>(1)); 1528 struct kvm_msr_entry &entry(kvm_msrs->entries[0]); 1529 1530 kvm_msrs->nmsrs = 1; 1531 entry.index = index; 1532 entry.reserved = 0; 1533 entry.data = 0; 1534 1535 getMSRs(*kvm_msrs.get()); 1536 return entry.data; 1537} 1538 1539const Kvm::MSRIndexVector & 1540X86KvmCPU::getMsrIntersection() const 1541{ 1542 if (cachedMsrIntersection.empty()) { 1543 const Kvm::MSRIndexVector &kvm_msrs(vm.kvm.getSupportedMSRs()); 1544 1545 DPRINTF(Kvm, "kvm-x86: Updating MSR intersection\n"); 1546 for (auto it = kvm_msrs.cbegin(); it != kvm_msrs.cend(); ++it) { 1547 if (X86ISA::msrMap.find(*it) != X86ISA::msrMap.end()) { 1548 cachedMsrIntersection.push_back(*it); 1549 DPRINTF(Kvm, "kvm-x86: Adding MSR 0x%x\n", *it); 1550 } else { 1551 warn("kvm-x86: MSR (0x%x) unsupported by gem5. Skipping.\n", 1552 *it); 1553 } 1554 } 1555 } 1556 1557 return cachedMsrIntersection; 1558} 1559 1560void 1561X86KvmCPU::getDebugRegisters(struct kvm_debugregs ®s) const 1562{ 1563#ifdef KVM_GET_DEBUGREGS 1564 if (ioctl(KVM_GET_DEBUGREGS, ®s) == -1) 1565 panic("KVM: Failed to get guest debug registers\n"); 1566#else 1567 panic("KVM: Unsupported getDebugRegisters call.\n"); 1568#endif 1569} 1570 1571void 1572X86KvmCPU::setDebugRegisters(const struct kvm_debugregs ®s) 1573{ 1574#ifdef KVM_SET_DEBUGREGS 1575 if (ioctl(KVM_SET_DEBUGREGS, (void *)®s) == -1) 1576 panic("KVM: Failed to set guest debug registers\n"); 1577#else 1578 panic("KVM: Unsupported setDebugRegisters call.\n"); 1579#endif 1580} 1581 1582void 1583X86KvmCPU::getXCRs(struct kvm_xcrs ®s) const 1584{ 1585 if (ioctl(KVM_GET_XCRS, ®s) == -1) 1586 panic("KVM: Failed to get guest debug registers\n"); 1587} 1588 1589void 1590X86KvmCPU::setXCRs(const struct kvm_xcrs ®s) 1591{ 1592 if (ioctl(KVM_SET_XCRS, (void *)®s) == -1) 1593 panic("KVM: Failed to set guest debug registers\n"); 1594} 1595 1596void 1597X86KvmCPU::getXSave(struct kvm_xsave &xsave) const 1598{ 1599 if (ioctl(KVM_GET_XSAVE, &xsave) == -1) 1600 panic("KVM: Failed to get guest debug registers\n"); 1601} 1602 1603void 1604X86KvmCPU::setXSave(const struct kvm_xsave &xsave) 1605{ 1606 if (ioctl(KVM_SET_XSAVE, (void *)&xsave) == -1) 1607 panic("KVM: Failed to set guest debug registers\n"); 1608} 1609 1610 1611void 1612X86KvmCPU::getVCpuEvents(struct kvm_vcpu_events &events) const 1613{ 1614 if (ioctl(KVM_GET_VCPU_EVENTS, &events) == -1) 1615 panic("KVM: Failed to get guest debug registers\n"); 1616} 1617 1618void 1619X86KvmCPU::setVCpuEvents(const struct kvm_vcpu_events &events) 1620{ 1621 if (ioctl(KVM_SET_VCPU_EVENTS, (void *)&events) == -1) 1622 panic("KVM: Failed to set guest debug registers\n"); 1623} 1624 1625X86KvmCPU * 1626X86KvmCPUParams::create() 1627{ 1628 return new X86KvmCPU(this); 1629} 1630