intr_control_noisa.cc revision 1762
11689SN/A/* 22325SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292756Sksewell@umich.edu#include <string> 301689SN/A#include <vector> 311689SN/A 321858SN/A#include "cpu/base.hh" 336658Snate@binkert.org#include "cpu/intr_control.hh" 342733Sktlim@umich.edu#include "sim/builder.hh" 354762Snate@binkert.org#include "sim/sim_object.hh" 364762Snate@binkert.org 374762Snate@binkert.orgusing namespace std; 384762Snate@binkert.org 394762Snate@binkert.orgIntrControl::IntrControl(const string &name, BaseCPU *c) 405595Sgblack@eecs.umich.edu : SimObject(name), cpu(c) 414762Snate@binkert.org{} 424762Snate@binkert.org 434762Snate@binkert.org/* @todo 444762Snate@binkert.org *Fix the cpu sim object parameter to be a system pointer 451858SN/A *instead, to avoid some extra dereferencing 462356SN/A */ 471060SN/Avoid 481060SN/AIntrControl::post(int int_num, int index) 491060SN/A{ 501060SN/A std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 511060SN/A BaseCPU *temp = xcvec[0]->cpu; 522794Sktlim@umich.edu temp->post_interrupt(int_num, index); 532794Sktlim@umich.edu} 542794Sktlim@umich.edu 552794Sktlim@umich.eduvoid 565702Ssaidi@eecs.umich.eduIntrControl::post(int cpu_id, int int_num, int index) 575702Ssaidi@eecs.umich.edu{ 585702Ssaidi@eecs.umich.edu std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 595702Ssaidi@eecs.umich.edu BaseCPU *temp = xcvec[cpu_id]->cpu; 605529Snate@binkert.org temp->post_interrupt(int_num, index); 615529Snate@binkert.org} 622669Sktlim@umich.edu 636221Snate@binkert.orgvoid 641060SN/AIntrControl::clear(int int_num, int index) 655529Snate@binkert.org{ 665712Shsul@eecs.umich.edu std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 671060SN/A BaseCPU *temp = xcvec[0]->cpu; 681060SN/A temp->clear_interrupt(int_num, index); 691060SN/A} 702292SN/A 712733Sktlim@umich.eduvoid 722292SN/AIntrControl::clear(int cpu_id, int int_num, int index) 732292SN/A{ 742292SN/A std::vector<ExecContext *> &xcvec = cpu->system->execContexts; 752292SN/A BaseCPU *temp = xcvec[cpu_id]->cpu; 761060SN/A temp->clear_interrupt(int_num, index); 771755SN/A} 785606Snate@binkert.org 791060SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 801060SN/A 811060SN/A SimObjectParam<BaseCPU *> cpu; 821060SN/A 831060SN/AEND_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 841755SN/A 851060SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl) 861060SN/A 871060SN/A INIT_PARAM(cpu, "the cpu") 881060SN/A 891060SN/AEND_INIT_SIM_OBJECT_PARAMS(IntrControl) 901060SN/A 915336Shines@cs.fsu.eduCREATE_SIM_OBJECT(IntrControl) 921060SN/A{ 934873Sstever@eecs.umich.edu return new IntrControl(getInstanceName(), cpu); 941060SN/A} 951060SN/A 961060SN/AREGISTER_SIM_OBJECT("IntrControl", IntrControl) 972829Sksewell@umich.edu