intr_control.cc revision 8793:5f25086326ac
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Ron Dreslinski 30 */ 31 32#include <string> 33#include <vector> 34 35#include "base/trace.hh" 36#include "cpu/base.hh" 37#include "cpu/intr_control.hh" 38#include "cpu/thread_context.hh" 39#include "debug/IntrControl.hh" 40#include "sim/sim_object.hh" 41 42using namespace std; 43 44IntrControl::IntrControl(const Params *p) 45 : SimObject(p), sys(p->sys) 46{} 47 48void 49IntrControl::post(int cpu_id, int int_num, int index) 50{ 51 DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id); 52 std::vector<ThreadContext *> &tcvec = sys->threadContexts; 53 BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); 54 cpu->postInterrupt(int_num, index); 55} 56 57void 58IntrControl::clear(int cpu_id, int int_num, int index) 59{ 60 DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id); 61 std::vector<ThreadContext *> &tcvec = sys->threadContexts; 62 BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); 63 cpu->clearInterrupt(int_num, index); 64} 65 66IntrControl * 67IntrControlParams::create() 68{ 69 return new IntrControl(this); 70} 71