intr_control.cc revision 5218:9b99318ca70d
12SN/A/* 21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Ron Dreslinski 302SN/A */ 312SN/A 322SN/A#include <string> 332SN/A#include <vector> 342SN/A 352SN/A#include "base/trace.hh" 362SN/A#include "cpu/base.hh" 372SN/A#include "cpu/thread_context.hh" 382SN/A#include "cpu/intr_control.hh" 392SN/A#include "sim/sim_object.hh" 402SN/A 412SN/Ausing namespace std; 422SN/A 432SN/AIntrControl::IntrControl(const Params *p) 444762Snate@binkert.org : SimObject(p), sys(p->sys) 4556SN/A{} 461127SN/A 472SN/Avoid 482797Sktlim@umich.eduIntrControl::post(int cpu_id, int int_num, int index) 492797Sktlim@umich.edu{ 502609SN/A DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id); 512SN/A std::vector<ThreadContext *> &tcvec = sys->threadContexts; 522SN/A BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); 532SN/A cpu->post_interrupt(int_num, index); 542SN/A} 552SN/A 561127SN/Avoid 572SN/AIntrControl::clear(int cpu_id, int int_num, int index) 581553SN/A{ 592797Sktlim@umich.edu DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id); 602901Ssaidi@eecs.umich.edu std::vector<ThreadContext *> &tcvec = sys->threadContexts; 612839Sktlim@umich.edu BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); 622901Ssaidi@eecs.umich.edu cpu->clear_interrupt(int_num, index); 632797Sktlim@umich.edu} 643202Shsul@eecs.umich.edu 652901Ssaidi@eecs.umich.eduIntrControl * 662901Ssaidi@eecs.umich.eduIntrControlParams::create() 672797Sktlim@umich.edu{ 68265SN/A return new IntrControl(this); 692797Sktlim@umich.edu} 701553SN/A