inteltrace.hh revision 5034:6186ef720dd4
11689SN/A/* 22326SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 291689SN/A * Nathan Binkert 301689SN/A */ 312292SN/A 322292SN/A#ifndef __INTELTRACE_HH__ 331060SN/A#define __INTELTRACE_HH__ 341060SN/A 351060SN/A#include "base/trace.hh" 361461SN/A#include "cpu/static_inst.hh" 371060SN/A#include "params/IntelTrace.hh" 382292SN/A#include "sim/host.hh" 391717SN/A#include "sim/insttracer.hh" 402292SN/A 412292SN/Aclass ThreadContext; 421060SN/A 432292SN/A 442292SN/Anamespace Trace { 452292SN/A 462326SN/Aclass IntelTraceRecord : public InstRecord 472326SN/A{ 482326SN/A public: 492326SN/A IntelTraceRecord(Tick _when, ThreadContext *_thread, 502326SN/A const StaticInstPtr &_staticInst, Addr _pc, bool spec) 512292SN/A : InstRecord(_when, _thread, _staticInst, _pc, spec) 522326SN/A { 532326SN/A } 542326SN/A 552326SN/A void dump(); 562326SN/A}; 572326SN/A 582326SN/Aclass IntelTrace : public InstTracer 592326SN/A{ 602326SN/A public: 612326SN/A 622326SN/A IntelTrace(const IntelTraceParams *p) : InstTracer(p) 632292SN/A {} 641681SN/A 652292SN/A IntelTraceRecord * 661060SN/A getInstRecord(Tick when, ThreadContext *tc, 671060SN/A const StaticInstPtr staticInst, Addr pc) 681060SN/A { 691061SN/A if (!IsOn(ExecEnable)) 701061SN/A return NULL; 711060SN/A 721060SN/A if (!Trace::enabled) 731060SN/A return NULL; 741681SN/A 751061SN/A if (!IsOn(ExecSpeculative) && tc->misspeculating()) 762292SN/A return NULL; 771060SN/A 781061SN/A return new IntelTraceRecord(when, tc, 791061SN/A staticInst, pc, tc->misspeculating()); 801061SN/A } 811061SN/A}; 821060SN/A 831681SN/A/* namespace Trace */ } 842292SN/A 852292SN/A#endif // __EXETRACE_HH__ 861060SN/A