inteltrace.hh revision 4776
12SN/A/*
21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292665Ssaidi@eecs.umich.edu *          Nathan Binkert
302SN/A */
312SN/A
322SN/A#ifndef __INTELTRACE_HH__
332SN/A#define __INTELTRACE_HH__
342SN/A
352SN/A#include "base/trace.hh"
365882Snate@binkert.org#include "cpu/static_inst.hh"
371492SN/A#include "sim/host.hh"
381717SN/A#include "sim/insttracer.hh"
398229Snate@binkert.org
402680Sktlim@umich.educlass ThreadContext;
418232Snate@binkert.org
424167Sbinkertn@umich.edu
432190SN/Anamespace Trace {
442SN/A
452SN/Aclass IntelTraceRecord : public InstRecord
462SN/A{
472SN/A  public:
482SN/A    IntelTraceRecord(Tick _when, ThreadContext *_thread,
492SN/A               const StaticInstPtr &_staticInst, Addr _pc, bool spec)
502SN/A        : InstRecord(_when, _thread, _staticInst, _pc, spec)
512SN/A    {
522SN/A    }
532SN/A
542SN/A    void dump();
552SN/A};
562SN/A
572SN/Aclass IntelTrace : public InstTracer
588991SAli.Saidi@ARM.com{
598991SAli.Saidi@ARM.com  public:
608991SAli.Saidi@ARM.com
612SN/A    IntelTrace(const std::string & name) : InstTracer(name)
622SN/A    {}
632SN/A
648991SAli.Saidi@ARM.com    IntelTraceRecord *
652SN/A    getInstRecord(Tick when, ThreadContext *tc,
668991SAli.Saidi@ARM.com            const StaticInstPtr staticInst, Addr pc)
678991SAli.Saidi@ARM.com    {
682SN/A        if (!IsOn(ExecEnable))
698991SAli.Saidi@ARM.com            return NULL;
702SN/A
712SN/A        if (!Trace::enabled)
722SN/A            return NULL;
732SN/A
742SN/A        if (!IsOn(ExecSpeculative) && tc->misspeculating())
752SN/A            return NULL;
762SN/A
772SN/A        return new IntelTraceRecord(when, tc,
782SN/A                staticInst, pc, tc->misspeculating());
792SN/A    }
802SN/A};
812SN/A
822SN/A/* namespace Trace */ }
832SN/A
842SN/A#endif // __EXETRACE_HH__
852SN/A