inst_pb_trace.hh revision 10761
110695SAli.Saidi@ARM.com/* 210695SAli.Saidi@ARM.com * Copyright (c) 2014 ARM Limited 310695SAli.Saidi@ARM.com * All rights reserved 410695SAli.Saidi@ARM.com * 510695SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 610695SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 710695SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 810695SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 910695SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 1010695SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 1110695SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 1210695SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 1310695SAli.Saidi@ARM.com * 1410695SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 1510695SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 1610695SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 1710695SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 1810695SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 1910695SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 2010695SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 2110695SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 2210695SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 2310695SAli.Saidi@ARM.com * this software without specific prior written permission. 2410695SAli.Saidi@ARM.com * 2510695SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610695SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710695SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810695SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910695SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010695SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110695SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210695SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310695SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410695SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510695SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610695SAli.Saidi@ARM.com * 3710695SAli.Saidi@ARM.com * Authors: Ali Saidi 3810695SAli.Saidi@ARM.com */ 3910695SAli.Saidi@ARM.com 4010695SAli.Saidi@ARM.com#ifndef __CPU_INST_PB_TRACE_HH__ 4110695SAli.Saidi@ARM.com#define __CPU_INST_PB_TRACE_HH__ 4210695SAli.Saidi@ARM.com 4310695SAli.Saidi@ARM.com#include "arch/types.hh" 4410695SAli.Saidi@ARM.com#include "base/trace.hh" 4510695SAli.Saidi@ARM.com#include "base/types.hh" 4610695SAli.Saidi@ARM.com#include "cpu/static_inst_fwd.hh" 4710695SAli.Saidi@ARM.com#include "params/InstPBTrace.hh" 4810695SAli.Saidi@ARM.com#include "proto/protoio.hh" 4910695SAli.Saidi@ARM.com#include "sim/insttracer.hh" 5010695SAli.Saidi@ARM.com 5110695SAli.Saidi@ARM.comclass ThreadContext; 5210695SAli.Saidi@ARM.com 5310695SAli.Saidi@ARM.comnamespace ProtoMessage { 5410695SAli.Saidi@ARM.comclass Inst; 5510695SAli.Saidi@ARM.com} 5610695SAli.Saidi@ARM.com 5710695SAli.Saidi@ARM.comnamespace Trace { 5810695SAli.Saidi@ARM.com 5910695SAli.Saidi@ARM.com/** 6010695SAli.Saidi@ARM.com * This in an instruction tracer that records the flow of instructions through 6110695SAli.Saidi@ARM.com * multiple cpus and systems to a protobuf file specified by proto/inst.proto 6210695SAli.Saidi@ARM.com * for further analysis. 6310695SAli.Saidi@ARM.com */ 6410695SAli.Saidi@ARM.com 6510695SAli.Saidi@ARM.comclass InstPBTraceRecord : public InstRecord 6610695SAli.Saidi@ARM.com{ 6710695SAli.Saidi@ARM.com public: 6810695SAli.Saidi@ARM.com InstPBTraceRecord(InstPBTrace& _tracer, Tick when, ThreadContext *tc, 6910695SAli.Saidi@ARM.com const StaticInstPtr si, TheISA::PCState pc, 7010695SAli.Saidi@ARM.com const StaticInstPtr mi = NULL) 7110695SAli.Saidi@ARM.com : InstRecord(when, tc, si, pc, mi), tracer(_tracer) 7210695SAli.Saidi@ARM.com {} 7310695SAli.Saidi@ARM.com 7410695SAli.Saidi@ARM.com /** called by the cpu when the instruction commits. 7510695SAli.Saidi@ARM.com * This implementation of dump calls InstPBTrace to output the contents to a 7610695SAli.Saidi@ARM.com * protobuf file 7710695SAli.Saidi@ARM.com */ 7810695SAli.Saidi@ARM.com void dump() M5_ATTR_OVERRIDE; 7910695SAli.Saidi@ARM.com 8010695SAli.Saidi@ARM.com protected: 8110695SAli.Saidi@ARM.com InstPBTrace& tracer; 8210695SAli.Saidi@ARM.com 8310695SAli.Saidi@ARM.com}; 8410695SAli.Saidi@ARM.com 8510761Sandreas.hansson@arm.comclass InstPBTrace : public InstTracer 8610695SAli.Saidi@ARM.com{ 8710695SAli.Saidi@ARM.com public: 8810695SAli.Saidi@ARM.com InstPBTrace(const InstPBTraceParams *p); 8910695SAli.Saidi@ARM.com virtual ~InstPBTrace(); 9010695SAli.Saidi@ARM.com 9110695SAli.Saidi@ARM.com InstPBTraceRecord* getInstRecord(Tick when, ThreadContext *tc, const 9210695SAli.Saidi@ARM.com StaticInstPtr si, TheISA::PCState pc, const 9310695SAli.Saidi@ARM.com StaticInstPtr mi = NULL) M5_ATTR_OVERRIDE; 9410695SAli.Saidi@ARM.com 9510695SAli.Saidi@ARM.com protected: 9610695SAli.Saidi@ARM.com /** One output stream for the entire simulation. 9710695SAli.Saidi@ARM.com * We encode the CPU & system ID so all we need is a single file 9810695SAli.Saidi@ARM.com */ 9910695SAli.Saidi@ARM.com static ProtoOutputStream *traceStream; 10010695SAli.Saidi@ARM.com 10110695SAli.Saidi@ARM.com 10210695SAli.Saidi@ARM.com /** This is the message were working on writing. The majority of the message 10310695SAli.Saidi@ARM.com * exists however the memory accesses will be delayed. 10410695SAli.Saidi@ARM.com */ 10510695SAli.Saidi@ARM.com ProtoMessage::Inst *curMsg; 10610695SAli.Saidi@ARM.com 10710695SAli.Saidi@ARM.com /** Create the output file and write the header into it 10810695SAli.Saidi@ARM.com * @param filename the file to create (if ends with .gz it will be 10910695SAli.Saidi@ARM.com * compressed) 11010695SAli.Saidi@ARM.com */ 11110695SAli.Saidi@ARM.com void createTraceFile(std::string filename); 11210695SAli.Saidi@ARM.com 11310695SAli.Saidi@ARM.com /** If there is a pending message still write it out and then close the file 11410695SAli.Saidi@ARM.com */ 11510695SAli.Saidi@ARM.com void closeStreams(); 11610695SAli.Saidi@ARM.com 11710695SAli.Saidi@ARM.com /** Write an instruction to the trace file 11810695SAli.Saidi@ARM.com * @param tc thread context for the cpu ID 11910695SAli.Saidi@ARM.com * @param si for the machInst and opClass 12010695SAli.Saidi@ARM.com * @param pc for the PC Addr 12110695SAli.Saidi@ARM.com */ 12210695SAli.Saidi@ARM.com void traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc); 12310695SAli.Saidi@ARM.com 12410695SAli.Saidi@ARM.com /** Write a memory request to the trace file as part of the cur instruction 12510695SAli.Saidi@ARM.com * @param si for the machInst and opClass 12610695SAli.Saidi@ARM.com * @param a address of the request 12710695SAli.Saidi@ARM.com * @param s size of the request 12810695SAli.Saidi@ARM.com * @param f flags for the request 12910695SAli.Saidi@ARM.com */ 13010695SAli.Saidi@ARM.com void traceMem(StaticInstPtr si, Addr a, Addr s, unsigned f); 13110695SAli.Saidi@ARM.com 13210695SAli.Saidi@ARM.com friend class InstPBTraceRecord; 13310695SAli.Saidi@ARM.com}; 13410695SAli.Saidi@ARM.com} // namespace Trace 13510695SAli.Saidi@ARM.com#endif // __CPU_INST_PB_TRACE_HH__ 136