exetrace.hh revision 4074:f2c4afa8cd46
12651Ssaidi@eecs.umich.edu/* 22651Ssaidi@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 32651Ssaidi@eecs.umich.edu * All rights reserved. 42651Ssaidi@eecs.umich.edu * 52651Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62651Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72651Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82651Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92651Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102651Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112651Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122651Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132651Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142651Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152651Ssaidi@eecs.umich.edu * 162651Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172651Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182651Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192651Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202651Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212651Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222651Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232651Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242651Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252651Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262651Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272651Ssaidi@eecs.umich.edu * 282651Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292651Ssaidi@eecs.umich.edu * Nathan Binkert 302651Ssaidi@eecs.umich.edu */ 312651Ssaidi@eecs.umich.edu 322651Ssaidi@eecs.umich.edu#ifndef __EXETRACE_HH__ 332680Sktlim@umich.edu#define __EXETRACE_HH__ 342651Ssaidi@eecs.umich.edu 352651Ssaidi@eecs.umich.edu#include <cstring> 362651Ssaidi@eecs.umich.edu#include <fstream> 372651Ssaidi@eecs.umich.edu#include <vector> 382651Ssaidi@eecs.umich.edu 392651Ssaidi@eecs.umich.edu#include "base/trace.hh" 402651Ssaidi@eecs.umich.edu#include "cpu/inst_seq.hh" // for InstSeqNum 412651Ssaidi@eecs.umich.edu#include "cpu/static_inst.hh" 422651Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 432651Ssaidi@eecs.umich.edu#include "sim/host.hh" 442651Ssaidi@eecs.umich.edu 452651Ssaidi@eecs.umich.educlass ThreadContext; 462651Ssaidi@eecs.umich.edu 472651Ssaidi@eecs.umich.edu 482651Ssaidi@eecs.umich.edunamespace Trace { 492651Ssaidi@eecs.umich.edu 502651Ssaidi@eecs.umich.educlass InstRecord 512680Sktlim@umich.edu{ 522651Ssaidi@eecs.umich.edu protected: 532651Ssaidi@eecs.umich.edu typedef TheISA::IntRegFile IntRegFile; 542651Ssaidi@eecs.umich.edu 552680Sktlim@umich.edu Tick when; 562651Ssaidi@eecs.umich.edu 572651Ssaidi@eecs.umich.edu // The following fields are initialized by the constructor and 582680Sktlim@umich.edu // thus guaranteed to be valid. 592680Sktlim@umich.edu ThreadContext *thread; 602651Ssaidi@eecs.umich.edu // need to make this ref-counted so it doesn't go away before we 612651Ssaidi@eecs.umich.edu // dump the record 62 StaticInstPtr staticInst; 63 Addr PC; 64 bool misspeculating; 65 66 // The remaining fields are only valid for particular instruction 67 // types (e.g, addresses for memory ops) or when particular 68 // options are enabled (e.g., tracing full register contents). 69 // Each data field has an associated valid flag to indicate 70 // whether the data field is valid. 71 Addr addr; 72 bool addr_valid; 73 74 union { 75 uint64_t as_int; 76 double as_double; 77 } data; 78 enum { 79 DataInvalid = 0, 80 DataInt8 = 1, // set to equal number of bytes 81 DataInt16 = 2, 82 DataInt32 = 4, 83 DataInt64 = 8, 84 DataDouble = 3 85 } data_status; 86 87 InstSeqNum fetch_seq; 88 bool fetch_seq_valid; 89 90 InstSeqNum cp_seq; 91 bool cp_seq_valid; 92 93 struct iRegFile { 94 IntRegFile regs; 95 }; 96 iRegFile *iregs; 97 bool regs_valid; 98 99 public: 100 InstRecord(Tick _when, ThreadContext *_thread, 101 const StaticInstPtr &_staticInst, 102 Addr _pc, bool spec) 103 : when(_when), thread(_thread), 104 staticInst(_staticInst), PC(_pc), 105 misspeculating(spec) 106 { 107 data_status = DataInvalid; 108 addr_valid = false; 109 regs_valid = false; 110 111 fetch_seq_valid = false; 112 cp_seq_valid = false; 113 } 114 115 ~InstRecord() { } 116 117 void setAddr(Addr a) { addr = a; addr_valid = true; } 118 119 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 120 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 121 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 122 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 123 124 void setData(int64_t d) { setData((uint64_t)d); } 125 void setData(int32_t d) { setData((uint32_t)d); } 126 void setData(int16_t d) { setData((uint16_t)d); } 127 void setData(int8_t d) { setData((uint8_t)d); } 128 129 void setData(double d) { data.as_double = d; data_status = DataDouble; } 130 131 void setFetchSeq(InstSeqNum seq) 132 { fetch_seq = seq; fetch_seq_valid = true; } 133 134 void setCPSeq(InstSeqNum seq) 135 { cp_seq = seq; cp_seq_valid = true; } 136 137 void setRegs(const IntRegFile ®s); 138 139 void dump(); 140}; 141 142 143inline void 144InstRecord::setRegs(const IntRegFile ®s) 145{ 146 if (!iregs) 147 iregs = new iRegFile; 148 149 std::memcpy(&iregs->regs, ®s, sizeof(IntRegFile)); 150 regs_valid = true; 151} 152 153inline InstRecord * 154getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, 155 Addr pc) 156{ 157 if (!IsOn(ExecEnable)) 158 return NULL; 159 160 if (!Trace::enabled) 161 return NULL; 162 163 if (!IsOn(ExecSpeculative) && tc->misspeculating()) 164 return NULL; 165 166 return new InstRecord(when, tc, staticInst, pc, tc->misspeculating()); 167} 168 169/* namespace Trace */ } 170 171#endif // __EXETRACE_HH__ 172