exetrace.hh revision 3506:99f86646ba5c
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 611308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are 711308Santhony.gutierrez@amd.com * met: redistributions of source code must retain the above copyright 811308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer; 911308Santhony.gutierrez@amd.com * redistributions in binary form must reproduce the above copyright 1011308Santhony.gutierrez@amd.com * notice, this list of conditions and the following disclaimer in the 1111308Santhony.gutierrez@amd.com * documentation and/or other materials provided with the distribution; 1211308Santhony.gutierrez@amd.com * neither the name of the copyright holders nor the names of its 1311308Santhony.gutierrez@amd.com * contributors may be used to endorse or promote products derived from 1411308Santhony.gutierrez@amd.com * this software without specific prior written permission. 1511308Santhony.gutierrez@amd.com * 1611308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711308Santhony.gutierrez@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811308Santhony.gutierrez@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911308Santhony.gutierrez@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011308Santhony.gutierrez@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111308Santhony.gutierrez@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211308Santhony.gutierrez@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311308Santhony.gutierrez@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411308Santhony.gutierrez@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511308Santhony.gutierrez@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611308Santhony.gutierrez@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711308Santhony.gutierrez@amd.com * 2811308Santhony.gutierrez@amd.com * Authors: Steve Reinhardt 2911308Santhony.gutierrez@amd.com * Nathan Binkert 3011308Santhony.gutierrez@amd.com */ 3111308Santhony.gutierrez@amd.com 3211308Santhony.gutierrez@amd.com#ifndef __EXETRACE_HH__ 3311308Santhony.gutierrez@amd.com#define __EXETRACE_HH__ 3411308Santhony.gutierrez@amd.com 3511308Santhony.gutierrez@amd.com#include <fstream> 3611308Santhony.gutierrez@amd.com#include <vector> 3711308Santhony.gutierrez@amd.com 3811308Santhony.gutierrez@amd.com#include "sim/host.hh" 3911308Santhony.gutierrez@amd.com#include "cpu/inst_seq.hh" // for InstSeqNum 4011308Santhony.gutierrez@amd.com#include "base/trace.hh" 4111308Santhony.gutierrez@amd.com#include "cpu/thread_context.hh" 4211308Santhony.gutierrez@amd.com#include "cpu/static_inst.hh" 4311308Santhony.gutierrez@amd.com 4411308Santhony.gutierrez@amd.comclass ThreadContext; 4511308Santhony.gutierrez@amd.com 4611308Santhony.gutierrez@amd.com 4711308Santhony.gutierrez@amd.comnamespace Trace { 4811308Santhony.gutierrez@amd.com 4911308Santhony.gutierrez@amd.comclass InstRecord : public Record 5011308Santhony.gutierrez@amd.com{ 5111308Santhony.gutierrez@amd.com protected: 5211308Santhony.gutierrez@amd.com typedef TheISA::IntRegFile IntRegFile; 5311308Santhony.gutierrez@amd.com 5411308Santhony.gutierrez@amd.com // The following fields are initialized by the constructor and 5511308Santhony.gutierrez@amd.com // thus guaranteed to be valid. 5611308Santhony.gutierrez@amd.com ThreadContext *thread; 5711308Santhony.gutierrez@amd.com // need to make this ref-counted so it doesn't go away before we 5811308Santhony.gutierrez@amd.com // dump the record 5911308Santhony.gutierrez@amd.com StaticInstPtr staticInst; 6011308Santhony.gutierrez@amd.com Addr PC; 6111308Santhony.gutierrez@amd.com bool misspeculating; 6211534Sjohn.kalamatianos@amd.com 6311308Santhony.gutierrez@amd.com // The remaining fields are only valid for particular instruction 6411308Santhony.gutierrez@amd.com // types (e.g, addresses for memory ops) or when particular 6511308Santhony.gutierrez@amd.com // options are enabled (e.g., tracing full register contents). 6611308Santhony.gutierrez@amd.com // Each data field has an associated valid flag to indicate 6711308Santhony.gutierrez@amd.com // whether the data field is valid. 6811308Santhony.gutierrez@amd.com Addr addr; 6911308Santhony.gutierrez@amd.com bool addr_valid; 7011308Santhony.gutierrez@amd.com 7111308Santhony.gutierrez@amd.com union { 7211534Sjohn.kalamatianos@amd.com uint64_t as_int; 7311308Santhony.gutierrez@amd.com double as_double; 7411308Santhony.gutierrez@amd.com } data; 7511308Santhony.gutierrez@amd.com enum { 7611308Santhony.gutierrez@amd.com DataInvalid = 0, 7711308Santhony.gutierrez@amd.com DataInt8 = 1, // set to equal number of bytes 7811308Santhony.gutierrez@amd.com DataInt16 = 2, 7911308Santhony.gutierrez@amd.com DataInt32 = 4, 8011308Santhony.gutierrez@amd.com DataInt64 = 8, 8111308Santhony.gutierrez@amd.com DataDouble = 3 8211308Santhony.gutierrez@amd.com } data_status; 8311308Santhony.gutierrez@amd.com 8411308Santhony.gutierrez@amd.com InstSeqNum fetch_seq; 8511308Santhony.gutierrez@amd.com bool fetch_seq_valid; 8611308Santhony.gutierrez@amd.com 8711308Santhony.gutierrez@amd.com InstSeqNum cp_seq; 8811308Santhony.gutierrez@amd.com bool cp_seq_valid; 8911308Santhony.gutierrez@amd.com 9011308Santhony.gutierrez@amd.com struct iRegFile { 9111308Santhony.gutierrez@amd.com IntRegFile regs; 9211308Santhony.gutierrez@amd.com }; 9311308Santhony.gutierrez@amd.com iRegFile *iregs; 9411308Santhony.gutierrez@amd.com bool regs_valid; 9511308Santhony.gutierrez@amd.com 9611308Santhony.gutierrez@amd.com public: 9711308Santhony.gutierrez@amd.com InstRecord(Tick _cycle, ThreadContext *_thread, 9811308Santhony.gutierrez@amd.com const StaticInstPtr &_staticInst, 9911308Santhony.gutierrez@amd.com Addr _pc, bool spec) 10011308Santhony.gutierrez@amd.com : Record(_cycle), thread(_thread), 10111308Santhony.gutierrez@amd.com staticInst(_staticInst), PC(_pc), 10211308Santhony.gutierrez@amd.com misspeculating(spec) 10311308Santhony.gutierrez@amd.com { 10411308Santhony.gutierrez@amd.com data_status = DataInvalid; 10511308Santhony.gutierrez@amd.com addr_valid = false; 10611308Santhony.gutierrez@amd.com regs_valid = false; 10711308Santhony.gutierrez@amd.com 10811308Santhony.gutierrez@amd.com fetch_seq_valid = false; 10911308Santhony.gutierrez@amd.com cp_seq_valid = false; 11011308Santhony.gutierrez@amd.com } 11111308Santhony.gutierrez@amd.com 11211308Santhony.gutierrez@amd.com virtual ~InstRecord() { } 11311308Santhony.gutierrez@amd.com 11411308Santhony.gutierrez@amd.com virtual void dump(std::ostream &outs); 11511308Santhony.gutierrez@amd.com 11611308Santhony.gutierrez@amd.com void setAddr(Addr a) { addr = a; addr_valid = true; } 11711308Santhony.gutierrez@amd.com 11811308Santhony.gutierrez@amd.com void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 11911308Santhony.gutierrez@amd.com void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 12011308Santhony.gutierrez@amd.com void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 12111308Santhony.gutierrez@amd.com void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 12211308Santhony.gutierrez@amd.com 12311308Santhony.gutierrez@amd.com void setData(int64_t d) { setData((uint64_t)d); } 12411308Santhony.gutierrez@amd.com void setData(int32_t d) { setData((uint32_t)d); } 12511308Santhony.gutierrez@amd.com void setData(int16_t d) { setData((uint16_t)d); } 12611308Santhony.gutierrez@amd.com void setData(int8_t d) { setData((uint8_t)d); } 12711308Santhony.gutierrez@amd.com 12811308Santhony.gutierrez@amd.com void setData(double d) { data.as_double = d; data_status = DataDouble; } 12911308Santhony.gutierrez@amd.com 13011308Santhony.gutierrez@amd.com void setFetchSeq(InstSeqNum seq) 13111308Santhony.gutierrez@amd.com { fetch_seq = seq; fetch_seq_valid = true; } 13211308Santhony.gutierrez@amd.com 13311308Santhony.gutierrez@amd.com void setCPSeq(InstSeqNum seq) 13411308Santhony.gutierrez@amd.com { cp_seq = seq; cp_seq_valid = true; } 13511308Santhony.gutierrez@amd.com 13611308Santhony.gutierrez@amd.com void setRegs(const IntRegFile ®s); 13711308Santhony.gutierrez@amd.com 13811700Santhony.gutierrez@amd.com void finalize() { theLog.append(this); } 13911700Santhony.gutierrez@amd.com 14011308Santhony.gutierrez@amd.com enum InstExecFlagBits { 14111308Santhony.gutierrez@amd.com TRACE_MISSPEC = 0, 14211308Santhony.gutierrez@amd.com PRINT_CYCLE, 14311308Santhony.gutierrez@amd.com PRINT_OP_CLASS, 14411308Santhony.gutierrez@amd.com PRINT_THREAD_NUM, 14511308Santhony.gutierrez@amd.com PRINT_RESULT_DATA, 14611308Santhony.gutierrez@amd.com PRINT_EFF_ADDR, 14711308Santhony.gutierrez@amd.com PRINT_INT_REGS, 14811308Santhony.gutierrez@amd.com PRINT_FETCH_SEQ, 14911308Santhony.gutierrez@amd.com PRINT_CP_SEQ, 15011308Santhony.gutierrez@amd.com PRINT_REG_DELTA, 15111308Santhony.gutierrez@amd.com PC_SYMBOL, 15211308Santhony.gutierrez@amd.com INTEL_FORMAT, 15311308Santhony.gutierrez@amd.com LEGION_LOCKSTEP, 15411308Santhony.gutierrez@amd.com NUM_BITS 15511308Santhony.gutierrez@amd.com }; 15611308Santhony.gutierrez@amd.com 15711308Santhony.gutierrez@amd.com static std::vector<bool> flags; 15811308Santhony.gutierrez@amd.com static std::string trace_system; 15911308Santhony.gutierrez@amd.com 16011308Santhony.gutierrez@amd.com static void setParams(); 16111308Santhony.gutierrez@amd.com 16211308Santhony.gutierrez@amd.com static bool traceMisspec() { return flags[TRACE_MISSPEC]; } 16311308Santhony.gutierrez@amd.com}; 16411308Santhony.gutierrez@amd.com 16511308Santhony.gutierrez@amd.com 16611308Santhony.gutierrez@amd.cominline void 16711308Santhony.gutierrez@amd.comInstRecord::setRegs(const IntRegFile ®s) 16811308Santhony.gutierrez@amd.com{ 16911308Santhony.gutierrez@amd.com if (!iregs) 17011308Santhony.gutierrez@amd.com iregs = new iRegFile; 17111308Santhony.gutierrez@amd.com 17211308Santhony.gutierrez@amd.com memcpy(&iregs->regs, ®s, sizeof(IntRegFile)); 17311308Santhony.gutierrez@amd.com regs_valid = true; 17411308Santhony.gutierrez@amd.com} 17511308Santhony.gutierrez@amd.com 17611308Santhony.gutierrez@amd.cominline 17711308Santhony.gutierrez@amd.comInstRecord * 17811308Santhony.gutierrez@amd.comgetInstRecord(Tick cycle, ThreadContext *tc, 17911308Santhony.gutierrez@amd.com const StaticInstPtr staticInst, 18011308Santhony.gutierrez@amd.com Addr pc) 18111308Santhony.gutierrez@amd.com{ 18211308Santhony.gutierrez@amd.com if (DTRACE(InstExec) && 18311308Santhony.gutierrez@amd.com (InstRecord::traceMisspec() || !tc->misspeculating())) { 18411308Santhony.gutierrez@amd.com return new InstRecord(cycle, tc, staticInst, pc, 18511308Santhony.gutierrez@amd.com tc->misspeculating()); 18611308Santhony.gutierrez@amd.com } 18711308Santhony.gutierrez@amd.com 18811308Santhony.gutierrez@amd.com return NULL; 18911308Santhony.gutierrez@amd.com} 19011308Santhony.gutierrez@amd.com 19111308Santhony.gutierrez@amd.com 19211308Santhony.gutierrez@amd.com} 19311308Santhony.gutierrez@amd.com 19411308Santhony.gutierrez@amd.com#endif // __EXETRACE_HH__ 19511308Santhony.gutierrez@amd.com