exetrace.hh revision 2107 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __EXETRACE_HH__
30#define __EXETRACE_HH__
31
32#include <fstream>
33#include <vector>
34
35#include "sim/host.hh"
36#include "cpu/inst_seq.hh"	// for InstSeqNum
37#include "base/trace.hh"
38#include "cpu/exec_context.hh"
39#include "cpu/static_inst.hh"
40
41class BaseCPU;
42
43
44namespace Trace {
45
46class InstRecord : public Record
47{
48  protected:
49    typedef TheISA::Addr Addr;
50    typedef TheISA::IntRegFile IntRegFile;
51
52    // The following fields are initialized by the constructor and
53    // thus guaranteed to be valid.
54    BaseCPU *cpu;
55    // need to make this ref-counted so it doesn't go away before we
56    // dump the record
57    StaticInstPtr staticInst;
58    Addr PC;
59    bool misspeculating;
60    unsigned thread;
61
62    // The remaining fields are only valid for particular instruction
63    // types (e.g, addresses for memory ops) or when particular
64    // options are enabled (e.g., tracing full register contents).
65    // Each data field has an associated valid flag to indicate
66    // whether the data field is valid.
67    Addr addr;
68    bool addr_valid;
69
70    union {
71        uint64_t as_int;
72        double as_double;
73    } data;
74    enum {
75        DataInvalid = 0,
76        DataInt8 = 1,	// set to equal number of bytes
77        DataInt16 = 2,
78        DataInt32 = 4,
79        DataInt64 = 8,
80        DataDouble = 3
81    } data_status;
82
83    InstSeqNum fetch_seq;
84    bool fetch_seq_valid;
85
86    InstSeqNum cp_seq;
87    bool cp_seq_valid;
88
89    struct iRegFile {
90        IntRegFile regs;
91    };
92    iRegFile *iregs;
93    bool regs_valid;
94
95  public:
96    InstRecord(Tick _cycle, BaseCPU *_cpu,
97               const StaticInstPtr &_staticInst,
98               Addr _pc, bool spec, int _thread)
99        : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
100          misspeculating(spec), thread(_thread)
101    {
102        data_status = DataInvalid;
103        addr_valid = false;
104        regs_valid = false;
105
106        fetch_seq_valid = false;
107        cp_seq_valid = false;
108    }
109
110    virtual ~InstRecord() { }
111
112    virtual void dump(std::ostream &outs);
113
114    void setAddr(Addr a) { addr = a; addr_valid = true; }
115
116    void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
117    void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
118    void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
119    void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
120
121    void setData(int64_t d) { setData((uint64_t)d); }
122    void setData(int32_t d) { setData((uint32_t)d); }
123    void setData(int16_t d) { setData((uint16_t)d); }
124    void setData(int8_t d)  { setData((uint8_t)d); }
125
126    void setData(double d) { data.as_double = d; data_status = DataDouble; }
127
128    void setFetchSeq(InstSeqNum seq)
129    { fetch_seq = seq; fetch_seq_valid = true; }
130
131    void setCPSeq(InstSeqNum seq)
132    { cp_seq = seq; cp_seq_valid = true; }
133
134    void setRegs(const IntRegFile &regs);
135
136    void finalize() { theLog.append(this); }
137
138    enum InstExecFlagBits {
139        TRACE_MISSPEC = 0,
140        PRINT_CYCLE,
141        PRINT_OP_CLASS,
142        PRINT_THREAD_NUM,
143        PRINT_RESULT_DATA,
144        PRINT_EFF_ADDR,
145        PRINT_INT_REGS,
146        PRINT_FETCH_SEQ,
147        PRINT_CP_SEQ,
148        INTEL_FORMAT,
149        NUM_BITS
150    };
151
152    static std::vector<bool> flags;
153    static std::string trace_system;
154
155    static void setParams();
156
157    static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
158};
159
160
161inline void
162InstRecord::setRegs(const IntRegFile &regs)
163{
164    if (!iregs)
165      iregs = new iRegFile;
166
167    memcpy(&iregs->regs, regs, sizeof(IntRegFile));
168    regs_valid = true;
169}
170
171inline
172InstRecord *
173getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
174              const StaticInstPtr staticInst,
175              TheISA::Addr pc, int thread = 0)
176{
177    if (DTRACE(InstExec) &&
178        (InstRecord::traceMisspec() || !xc->misspeculating())) {
179        return new InstRecord(cycle, cpu, staticInst, pc,
180                              xc->misspeculating(), thread);
181    }
182
183    return NULL;
184}
185
186
187}
188
189#endif // __EXETRACE_HH__
190