exetrace.hh revision 2
113356Sciro.santilli@arm.com/* 28840Sandreas.hansson@arm.com * Copyright (c) 2003 The Regents of The University of Michigan 38840Sandreas.hansson@arm.com * All rights reserved. 48840Sandreas.hansson@arm.com * 58840Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68840Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78840Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88840Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98840Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108840Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118840Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128840Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 132740SN/A * contributors may be used to endorse or promote products derived from 149983Sstever@gmail.com * this software without specific prior written permission. 159983Sstever@gmail.com * 161046SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171046SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181046SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191046SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201046SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211046SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221046SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231046SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241046SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251046SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261046SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271046SN/A */ 281046SN/A 291046SN/A#ifndef __EXETRACE_HH__ 301046SN/A#define __EXETRACE_HH__ 311046SN/A 321046SN/A#include <fstream> 331046SN/A#include <vector> 341046SN/A 351046SN/A#include "host.hh" 361046SN/A#include "std_types.hh" // for InstSeqNum 371046SN/A#include "trace.hh" 381046SN/A#include "exec_context.hh" 391046SN/A#include "static_inst.hh" 402665SN/A 412665SN/Aclass BaseCPU; 422665SN/A 438840Sandreas.hansson@arm.com 4411988Sandreas.sandberg@arm.comnamespace Trace { 451046SN/A 4612563Sgabeblack@google.com#if 0 4713714Sandreas.sandberg@arm.com static const FlagVec ALL = ULL(0x1); 4813719Sandreas.sandberg@arm.com static const FlagVec FULL = ULL(0x2); 4913719Sandreas.sandberg@arm.com static const FlagVec SYMBOLS = ULL(0x4); 5013719Sandreas.sandberg@arm.com static const FlagVec EXTENDED = ULL(0x8); 5112563Sgabeblack@google.com static const FlagVec BRANCH_TAKEN = ULL(0x10); 525766Snate@binkert.org static const FlagVec BRANCH_NOTTAKEN = ULL(0x20); 538331Ssteve.reinhardt@amd.com static const FlagVec CALLPAL = ULL(0x40); 5411988Sandreas.sandberg@arm.com static const FlagVec SPECULATIVE = ULL(0x100); 5511988Sandreas.sandberg@arm.com static const FlagVec OMIT_COUNT = ULL(0x200); 561438SN/A static const FlagVec INCLUDE_THREAD_NUM = ULL(0x400); 574762Snate@binkert.org#endif 586654Snate@binkert.org 5911988Sandreas.sandberg@arm.comclass InstRecord : public Record 6012469Sglenn.bergmans@arm.com{ 6112469Sglenn.bergmans@arm.com protected: 6212469Sglenn.bergmans@arm.com 633102Sstever@eecs.umich.edu // The following fields are initialized by the constructor and 643102Sstever@eecs.umich.edu // thus guaranteed to be valid. 653102Sstever@eecs.umich.edu BaseCPU *cpu; 663102Sstever@eecs.umich.edu // need to make this ref-counted so it doesn't go away before we 676654Snate@binkert.org // dump the record 683102Sstever@eecs.umich.edu StaticInstPtr<TheISA> staticInst; 693102Sstever@eecs.umich.edu Addr PC; 707528Ssteve.reinhardt@amd.com bool misspeculating; 718839Sandreas.hansson@arm.com unsigned thread; 723102Sstever@eecs.umich.edu 736654Snate@binkert.org // The remaining fields are only valid for particular instruction 746654Snate@binkert.org // types (e.g, addresses for memory ops) or when particular 75679SN/A // options are enabled (e.g., tracing full register contents). 76679SN/A // Each data field has an associated valid flag to indicate 77679SN/A // whether the data field is valid. 78679SN/A Addr addr; 79679SN/A bool addr_valid; 80679SN/A 811692SN/A union { 82679SN/A uint64_t as_int; 83679SN/A double as_double; 84679SN/A } data; 85679SN/A enum { 86679SN/A DataInvalid = 0, 87679SN/A DataInt8 = 1, // set to equal number of bytes 88679SN/A DataInt16 = 2, 89679SN/A DataInt32 = 4, 90679SN/A DataInt64 = 8, 91679SN/A DataDouble = 3 92679SN/A } data_status; 93679SN/A 94679SN/A InstSeqNum fetch_seq; 95679SN/A bool fetch_seq_valid; 961692SN/A 97679SN/A InstSeqNum cp_seq; 98679SN/A bool cp_seq_valid; 99679SN/A 100679SN/A struct iRegFile { 101679SN/A IntRegFile regs; 102679SN/A }; 103679SN/A iRegFile *iregs; 104679SN/A bool regs_valid; 105679SN/A 106679SN/A public: 107679SN/A InstRecord(Tick _cycle, BaseCPU *_cpu, StaticInstPtr<TheISA> _staticInst, 108679SN/A Addr _pc, bool spec, unsigned _thread) 109679SN/A : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc), 110679SN/A misspeculating(spec), thread(_thread) 111679SN/A { 1122740SN/A data_status = DataInvalid; 113679SN/A addr_valid = false; 114679SN/A regs_valid = false; 115679SN/A 1164762Snate@binkert.org fetch_seq_valid = false; 1174762Snate@binkert.org cp_seq_valid = false; 1184762Snate@binkert.org } 1192738SN/A 1202738SN/A virtual ~InstRecord() { } 1212738SN/A 1229338SAndreas.Sandberg@arm.com virtual void dump(std::ostream &outs); 1239338SAndreas.Sandberg@arm.com 1249338SAndreas.Sandberg@arm.com void setAddr(Addr a) { addr = a; addr_valid = true; } 1257673Snate@binkert.org 1267673Snate@binkert.org void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 1278331Ssteve.reinhardt@amd.com void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 1288331Ssteve.reinhardt@amd.com void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 1297673Snate@binkert.org void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 13010458Sandreas.hansson@arm.com 13110458Sandreas.hansson@arm.com void setData(int64_t d) { setData((uint64_t)d); } 13210458Sandreas.hansson@arm.com void setData(int32_t d) { setData((uint32_t)d); } 13310458Sandreas.hansson@arm.com void setData(int16_t d) { setData((uint16_t)d); } 13410458Sandreas.hansson@arm.com void setData(int8_t d) { setData((uint8_t)d); } 13510458Sandreas.hansson@arm.com 13610458Sandreas.hansson@arm.com void setData(double d) { data.as_double = d; data_status = DataDouble; } 13710458Sandreas.hansson@arm.com 13810458Sandreas.hansson@arm.com void setFetchSeq(InstSeqNum seq) 13910458Sandreas.hansson@arm.com { fetch_seq = seq; fetch_seq_valid = true; } 14010458Sandreas.hansson@arm.com 14110458Sandreas.hansson@arm.com void setCPSeq(InstSeqNum seq) 14210458Sandreas.hansson@arm.com { cp_seq = seq; cp_seq_valid = true; } 14310458Sandreas.hansson@arm.com 14410458Sandreas.hansson@arm.com void setRegs(const IntRegFile ®s); 14510458Sandreas.hansson@arm.com 14610458Sandreas.hansson@arm.com void finalize() { theLog.append(this); } 14710458Sandreas.hansson@arm.com 14810458Sandreas.hansson@arm.com enum InstExecFlagBits { 14910458Sandreas.hansson@arm.com TRACE_MISSPEC = 0, 15010458Sandreas.hansson@arm.com PRINT_CYCLE, 15110458Sandreas.hansson@arm.com PRINT_OP_CLASS, 15210458Sandreas.hansson@arm.com PRINT_THREAD_NUM, 15310458Sandreas.hansson@arm.com PRINT_RESULT_DATA, 15410458Sandreas.hansson@arm.com PRINT_EFF_ADDR, 15510458Sandreas.hansson@arm.com PRINT_INT_REGS, 15610458Sandreas.hansson@arm.com PRINT_FETCH_SEQ, 15710458Sandreas.hansson@arm.com PRINT_CP_SEQ, 15810458Sandreas.hansson@arm.com NUM_BITS 15910458Sandreas.hansson@arm.com }; 16010458Sandreas.hansson@arm.com 16110458Sandreas.hansson@arm.com static std::vector<bool> flags; 16210458Sandreas.hansson@arm.com 16310458Sandreas.hansson@arm.com static void setParams(); 16410458Sandreas.hansson@arm.com 16510458Sandreas.hansson@arm.com static bool traceMisspec() { return flags[TRACE_MISSPEC]; } 16610458Sandreas.hansson@arm.com}; 16710458Sandreas.hansson@arm.com 16810458Sandreas.hansson@arm.com 16910458Sandreas.hansson@arm.cominline void 17010458Sandreas.hansson@arm.comInstRecord::setRegs(const IntRegFile ®s) 17110458Sandreas.hansson@arm.com{ 17210458Sandreas.hansson@arm.com if (!iregs) 17310458Sandreas.hansson@arm.com iregs = new iRegFile; 17410458Sandreas.hansson@arm.com 17513709Sandreas.sandberg@arm.com memcpy(&iregs->regs, regs, sizeof(IntRegFile)); 17610458Sandreas.hansson@arm.com regs_valid = true; 17710458Sandreas.hansson@arm.com} 17810458Sandreas.hansson@arm.com 17910458Sandreas.hansson@arm.cominline 18010458Sandreas.hansson@arm.comInstRecord * 18110458Sandreas.hansson@arm.comgetInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu, 18210458Sandreas.hansson@arm.com const StaticInstPtr<TheISA> staticInst, 18310458Sandreas.hansson@arm.com Addr pc, int thread = 0) 18410458Sandreas.hansson@arm.com{ 18510458Sandreas.hansson@arm.com if (DTRACE(InstExec) && 18610458Sandreas.hansson@arm.com (InstRecord::traceMisspec() || !xc->misspeculating())) { 18710458Sandreas.hansson@arm.com return new InstRecord(cycle, cpu, staticInst, pc, 18810458Sandreas.hansson@arm.com xc->misspeculating(), thread); 18910458Sandreas.hansson@arm.com } 19010458Sandreas.hansson@arm.com 19110458Sandreas.hansson@arm.com return NULL; 19210458Sandreas.hansson@arm.com} 19310458Sandreas.hansson@arm.com 19410458Sandreas.hansson@arm.com 19510458Sandreas.hansson@arm.com} 19610458Sandreas.hansson@arm.com 19710458Sandreas.hansson@arm.com#endif // __EXETRACE_HH__ 19810458Sandreas.hansson@arm.com