exetrace.cc revision 8902:75b524b64c28 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Lisa Hsu
30 *          Nathan Binkert
31 *          Steve Raasch
32 */
33
34#include <iomanip>
35
36#include "arch/isa_traits.hh"
37#include "arch/utility.hh"
38#include "base/loader/symtab.hh"
39#include "config/the_isa.hh"
40#include "cpu/base.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/static_inst.hh"
43#include "cpu/thread_context.hh"
44#include "debug/ExecAll.hh"
45#include "enums/OpClass.hh"
46
47using namespace std;
48using namespace TheISA;
49
50namespace Trace {
51
52void
53ExeTracerRecord::dumpTicks(ostream &outs)
54{
55    ccprintf(outs, "%7d: ", when);
56}
57
58void
59Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
60{
61    ostream &outs = Trace::output();
62
63    if (!Debug::ExecUser || !Debug::ExecKernel) {
64        bool in_user_mode = TheISA::inUserMode(thread);
65        if (in_user_mode && !Debug::ExecUser) return;
66        if (!in_user_mode && !Debug::ExecKernel) return;
67    }
68
69    if (Debug::ExecTicks)
70        dumpTicks(outs);
71
72    outs << thread->getCpuPtr()->name() << " ";
73
74    if (Debug::ExecSpeculative)
75        outs << (misspeculating ? "-" : "+") << " ";
76
77    if (Debug::ExecAsid)
78        outs << "A" << dec << TheISA::getExecutingAsid(thread) << " ";
79
80    if (Debug::ExecThread)
81        outs << "T" << thread->threadId() << " : ";
82
83    std::string sym_str;
84    Addr sym_addr;
85    Addr cur_pc = pc.instAddr();
86    if (debugSymbolTable && Debug::ExecSymbol && !inUserMode(thread)
87        && debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) {
88        if (cur_pc != sym_addr)
89            sym_str += csprintf("+%d",cur_pc - sym_addr);
90        outs << "@" << sym_str;
91    } else {
92        outs << "0x" << hex << cur_pc;
93    }
94
95    if (inst->isMicroop()) {
96        outs << "." << setw(2) << dec << pc.microPC();
97    } else {
98        outs << "   ";
99    }
100
101    outs << " : ";
102
103    //
104    //  Print decoded instruction
105    //
106
107    outs << setw(26) << left;
108    outs << inst->disassemble(cur_pc, debugSymbolTable);
109
110    if (ran) {
111        outs << " : ";
112
113        if (Debug::ExecOpClass) {
114            outs << Enums::OpClassStrings[inst->opClass()] << " : ";
115        }
116
117        if (Debug::ExecResult && predicate == false) {
118            outs << "Predicated False";
119        }
120
121        if (Debug::ExecResult && data_status != DataInvalid) {
122            ccprintf(outs, " D=%#018x", data.as_int);
123        }
124
125        if (Debug::ExecEffAddr && addr_valid)
126            outs << " A=0x" << hex << addr;
127
128        if (Debug::ExecFetchSeq && fetch_seq_valid)
129            outs << "  FetchSeq=" << dec << fetch_seq;
130
131        if (Debug::ExecCPSeq && cp_seq_valid)
132            outs << "  CPSeq=" << dec << cp_seq;
133    }
134
135    //
136    //  End of line...
137    //
138    outs << endl;
139}
140
141void
142Trace::ExeTracerRecord::dump()
143{
144    /*
145     * The behavior this check tries to achieve is that if ExecMacro is on,
146     * the macroop will be printed. If it's on and microops are also on, it's
147     * printed before the microops start printing to give context. If the
148     * microops aren't printed, then it's printed only when the final microop
149     * finishes. Macroops then behave like regular instructions and don't
150     * complete/print when they fault.
151     */
152    if (Debug::ExecMacro && staticInst->isMicroop() &&
153        ((Debug::ExecMicro &&
154            macroStaticInst && staticInst->isFirstMicroop()) ||
155            (!Debug::ExecMicro &&
156             macroStaticInst && staticInst->isLastMicroop()))) {
157        traceInst(macroStaticInst, false);
158    }
159    if (Debug::ExecMicro || !staticInst->isMicroop()) {
160        traceInst(staticInst, true);
161    }
162}
163
164} // namespace Trace
165
166////////////////////////////////////////////////////////////////////////
167//
168//  ExeTracer Simulation Object
169//
170Trace::ExeTracer *
171ExeTracerParams::create()
172{
173    return new Trace::ExeTracer(this);
174}
175