exetrace.cc revision 3614:70e12b0fe41e
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Lisa Hsu 30 * Nathan Binkert 31 * Steve Raasch 32 */ 33 34#include <fstream> 35#include <iomanip> 36#include <sys/ipc.h> 37#include <sys/shm.h> 38 39#include "arch/regfile.hh" 40#include "arch/utility.hh" 41#include "base/loader/symtab.hh" 42#include "config/full_system.hh" 43#include "cpu/base.hh" 44#include "cpu/exetrace.hh" 45#include "cpu/static_inst.hh" 46#include "sim/param.hh" 47#include "sim/system.hh" 48 49#if FULL_SYSTEM 50#include "arch/tlb.hh" 51#endif 52 53//XXX This is temporary 54#include "arch/isa_specific.hh" 55#include "cpu/m5legion_interface.h" 56 57using namespace std; 58using namespace TheISA; 59 60namespace Trace { 61SharedData *shared_data = NULL; 62} 63 64//////////////////////////////////////////////////////////////////////// 65// 66// Methods for the InstRecord object 67// 68 69 70void 71Trace::InstRecord::dump(ostream &outs) 72{ 73 if (flags[PRINT_REG_DELTA]) 74 { 75#if THE_ISA == SPARC_ISA 76 //Don't print what happens for each micro-op, just print out 77 //once at the last op, and for regular instructions. 78 if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 79 { 80 static uint64_t regs[32] = { 81 0, 0, 0, 0, 0, 0, 0, 0, 82 0, 0, 0, 0, 0, 0, 0, 0, 83 0, 0, 0, 0, 0, 0, 0, 0, 84 0, 0, 0, 0, 0, 0, 0, 0}; 85 static uint64_t ccr = 0; 86 static uint64_t y = 0; 87 static uint64_t floats[32]; 88 uint64_t newVal; 89 static const char * prefixes[4] = {"G", "O", "L", "I"}; 90 91 outs << hex; 92 outs << "PC = " << thread->readNextPC(); 93 outs << " NPC = " << thread->readNextNPC(); 94 newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); 95 if(newVal != ccr) 96 { 97 outs << " CCR = " << newVal; 98 ccr = newVal; 99 } 100 newVal = thread->readMiscReg(SparcISA::MISCREG_Y); 101 if(newVal != y) 102 { 103 outs << " Y = " << newVal; 104 y = newVal; 105 } 106 for(int y = 0; y < 4; y++) 107 { 108 for(int x = 0; x < 8; x++) 109 { 110 int index = x + 8 * y; 111 newVal = thread->readIntReg(index); 112 if(regs[index] != newVal) 113 { 114 outs << " " << prefixes[y] << dec << x << " = " << hex << newVal; 115 regs[index] = newVal; 116 } 117 } 118 } 119 for(int y = 0; y < 32; y++) 120 { 121 newVal = thread->readFloatRegBits(2 * y, 64); 122 if(floats[y] != newVal) 123 { 124 outs << " F" << dec << (2 * y) << " = " << hex << newVal; 125 floats[y] = newVal; 126 } 127 } 128 outs << dec << endl; 129 } 130#endif 131 } 132 else if (flags[INTEL_FORMAT]) { 133#if FULL_SYSTEM 134 bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system); 135#else 136 bool is_trace_system = true; 137#endif 138 if (is_trace_system) { 139 ccprintf(outs, "%7d ) ", cycle); 140 outs << "0x" << hex << PC << ":\t"; 141 if (staticInst->isLoad()) { 142 outs << "<RD 0x" << hex << addr; 143 outs << ">"; 144 } else if (staticInst->isStore()) { 145 outs << "<WR 0x" << hex << addr; 146 outs << ">"; 147 } 148 outs << endl; 149 } 150 } else { 151 if (flags[PRINT_CYCLE]) 152 ccprintf(outs, "%7d: ", cycle); 153 154 outs << thread->getCpuPtr()->name() << " "; 155 156 if (flags[TRACE_MISSPEC]) 157 outs << (misspeculating ? "-" : "+") << " "; 158 159 if (flags[PRINT_THREAD_NUM]) 160 outs << "T" << thread->getThreadNum() << " : "; 161 162 163 std::string sym_str; 164 Addr sym_addr; 165 if (debugSymbolTable 166 && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 167 && flags[PC_SYMBOL]) { 168 if (PC != sym_addr) 169 sym_str += csprintf("+%d", PC - sym_addr); 170 outs << "@" << sym_str << " : "; 171 } 172 else { 173 outs << "0x" << hex << PC << " : "; 174 } 175 176 // 177 // Print decoded instruction 178 // 179 180#if defined(__GNUC__) && (__GNUC__ < 3) 181 // There's a bug in gcc 2.x library that prevents setw() 182 // from working properly on strings 183 string mc(staticInst->disassemble(PC, debugSymbolTable)); 184 while (mc.length() < 26) 185 mc += " "; 186 outs << mc; 187#else 188 outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 189#endif 190 191 outs << " : "; 192 193 if (flags[PRINT_OP_CLASS]) { 194 outs << opClassStrings[staticInst->opClass()] << " : "; 195 } 196 197 if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 198 outs << " D="; 199#if 0 200 if (data_status == DataDouble) 201 ccprintf(outs, "%f", data.as_double); 202 else 203 ccprintf(outs, "%#018x", data.as_int); 204#else 205 ccprintf(outs, "%#018x", data.as_int); 206#endif 207 } 208 209 if (flags[PRINT_EFF_ADDR] && addr_valid) 210 outs << " A=0x" << hex << addr; 211 212 if (flags[PRINT_INT_REGS] && regs_valid) { 213 for (int i = 0; i < TheISA::NumIntRegs;) 214 for (int j = i + 1; i <= j; i++) 215 ccprintf(outs, "r%02d = %#018x%s", i, 216 iregs->regs.readReg(i), 217 ((i == j) ? "\n" : " ")); 218 outs << "\n"; 219 } 220 221 if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 222 outs << " FetchSeq=" << dec << fetch_seq; 223 224 if (flags[PRINT_CP_SEQ] && cp_seq_valid) 225 outs << " CPSeq=" << dec << cp_seq; 226 227 // 228 // End of line... 229 // 230 outs << endl; 231 } 232#if THE_ISA == SPARC_ISA 233 // Compare 234 if (flags[LEGION_LOCKSTEP]) 235 { 236 bool compared = false; 237 bool diffPC = false; 238 bool diffInst = false; 239 bool diffRegs = false; 240 Addr m5Pc, lgnPc; 241 242 243 if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { 244 while (!compared) { 245 m5Pc = PC & TheISA::PAddrImplMask; 246 lgnPc = shared_data->pc & TheISA::PAddrImplMask; 247 if (shared_data->flags == OWN_M5) { 248 if (lgnPc != m5Pc) 249 diffPC = true; 250 if (shared_data->instruction != staticInst->machInst) 251 diffInst = true; 252 for (int i = 0; i < TheISA::NumRegularIntRegs; i++) { 253 if (thread->readIntReg(i) != shared_data->intregs[i]) { 254 diffRegs = true; 255 } 256 } 257 258 if (diffPC || diffInst || diffRegs ) { 259 outs << "Differences found between M5 and Legion:"; 260 if (diffPC) 261 outs << " [PC]"; 262 if (diffInst) 263 outs << " [Instruction]"; 264 if (diffRegs) 265 outs << " [IntRegs]"; 266 outs << endl << endl; 267 268 outs << right << setfill(' ') << setw(15) 269 << "M5 PC: " << "0x"<< setw(16) << setfill('0') 270 << hex << m5Pc << endl; 271 outs << setfill(' ') << setw(15) 272 << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex 273 << lgnPc << endl << endl; 274 275 outs << setfill(' ') << setw(15) 276 << "M5 Inst: " << "0x"<< setw(8) 277 << setfill('0') << hex << staticInst->machInst 278 << staticInst->disassemble(m5Pc, debugSymbolTable) 279 << endl; 280 281 StaticInstPtr legionInst = StaticInst::decode(makeExtMI(shared_data->instruction, thread)); 282 outs << setfill(' ') << setw(15) 283 << " Legion Inst: " 284 << "0x" << setw(8) << setfill('0') << hex 285 << shared_data->instruction 286 << legionInst->disassemble(lgnPc, debugSymbolTable) 287 << endl; 288 289 outs << endl; 290 291 static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; 292 for(int y = 0; y < 4; y++) 293 { 294 for(int x = 0; x < 8; x++) 295 { 296 outs << regtypes[y] << x << " " ; 297 outs << "0x" << hex << setw(16) << thread->readIntReg(y*8+x); 298 if (thread->readIntReg(y*8 + x) != shared_data->intregs[y*8+x]) 299 outs << " X "; 300 else 301 outs << " | "; 302 outs << "0x" << setw(16) << hex << shared_data->intregs[y*8+x] 303 << endl; 304 } 305 } 306 fatal("Differences found between Legion and M5\n"); 307 } 308 309 compared = true; 310 shared_data->flags = OWN_LEGION; 311 } 312 } // while 313 } // if not microop 314 } 315#endif 316} 317 318 319vector<bool> Trace::InstRecord::flags(NUM_BITS); 320string Trace::InstRecord::trace_system; 321 322//////////////////////////////////////////////////////////////////////// 323// 324// Parameter space for per-cycle execution address tracing options. 325// Derive from ParamContext so we can override checkParams() function. 326// 327class ExecutionTraceParamContext : public ParamContext 328{ 329 public: 330 ExecutionTraceParamContext(const string &_iniSection) 331 : ParamContext(_iniSection) 332 { 333 } 334 335 void checkParams(); // defined at bottom of file 336}; 337 338ExecutionTraceParamContext exeTraceParams("exetrace"); 339 340Param<bool> exe_trace_spec(&exeTraceParams, "speculative", 341 "capture speculative instructions", true); 342 343Param<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 344 "print cycle number", true); 345Param<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 346 "print op class", true); 347Param<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 348 "print thread number", true); 349Param<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 350 "print effective address", true); 351Param<bool> exe_trace_print_data(&exeTraceParams, "print_data", 352 "print result data", true); 353Param<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 354 "print all integer regs", false); 355Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 356 "print fetch sequence number", false); 357Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 358 "print correct-path sequence number", false); 359Param<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 360 "print which registers changed to what", false); 361Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 362 "Use symbols for the PC if available", true); 363Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 364 "print trace in intel compatible format", false); 365Param<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep", 366 "Compare sim state to legion state every cycle", 367 false); 368Param<string> exe_trace_system(&exeTraceParams, "trace_system", 369 "print trace of which system (client or server)", 370 "client"); 371 372 373// 374// Helper function for ExecutionTraceParamContext::checkParams() just 375// to get us into the InstRecord namespace 376// 377void 378Trace::InstRecord::setParams() 379{ 380 flags[TRACE_MISSPEC] = exe_trace_spec; 381 382 flags[PRINT_CYCLE] = exe_trace_print_cycle; 383 flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 384 flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 385 flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 386 flags[PRINT_EFF_ADDR] = exe_trace_print_data; 387 flags[PRINT_INT_REGS] = exe_trace_print_iregs; 388 flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 389 flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 390 flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 391 flags[PC_SYMBOL] = exe_trace_pc_symbol; 392 flags[INTEL_FORMAT] = exe_trace_intel_format; 393 flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep; 394 trace_system = exe_trace_system; 395 396 // If were going to be in lockstep with Legion 397 // Setup shared memory, and get otherwise ready 398 if (flags[LEGION_LOCKSTEP]) { 399 int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777); 400 if (shmfd < 0) 401 fatal("Couldn't get shared memory fd. Is Legion running?"); 402 403 shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 404 if (shared_data == (SharedData*)-1) 405 fatal("Couldn't allocate shared memory"); 406 407 if (shared_data->flags != OWN_M5) 408 fatal("Shared memory has invalid owner"); 409 410 if (shared_data->version != VERSION) 411 fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 412 shared_data->version); 413 414 // step legion forward one cycle so we can get register values 415 shared_data->flags = OWN_LEGION; 416 } 417} 418 419void 420ExecutionTraceParamContext::checkParams() 421{ 422 Trace::InstRecord::setParams(); 423} 424 425