exetrace.cc revision 3584:8c3cdb2c001c 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Lisa Hsu
30 *          Nathan Binkert
31 *          Steve Raasch
32 */
33
34#include <fstream>
35#include <iomanip>
36#include <sys/ipc.h>
37#include <sys/shm.h>
38
39#include "arch/regfile.hh"
40#include "arch/utility.hh"
41#include "base/loader/symtab.hh"
42#include "cpu/base.hh"
43#include "cpu/exetrace.hh"
44#include "cpu/static_inst.hh"
45#include "sim/param.hh"
46#include "sim/system.hh"
47
48//XXX This is temporary
49#include "arch/isa_specific.hh"
50#include "cpu/m5legion_interface.h"
51
52using namespace std;
53using namespace TheISA;
54
55namespace Trace {
56SharedData *shared_data = NULL;
57}
58
59////////////////////////////////////////////////////////////////////////
60//
61//  Methods for the InstRecord object
62//
63
64
65void
66Trace::InstRecord::dump(ostream &outs)
67{
68    if (flags[PRINT_REG_DELTA])
69    {
70#if THE_ISA == SPARC_ISA
71#if 0
72        //Don't print what happens for each micro-op, just print out
73        //once at the last op, and for regular instructions.
74        if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
75        {
76            static uint64_t regs[32] = {
77                0, 0, 0, 0, 0, 0, 0, 0,
78                0, 0, 0, 0, 0, 0, 0, 0,
79                0, 0, 0, 0, 0, 0, 0, 0,
80                0, 0, 0, 0, 0, 0, 0, 0};
81            static uint64_t ccr = 0;
82            static uint64_t y = 0;
83            static uint64_t floats[32];
84            uint64_t newVal;
85            static const char * prefixes[4] = {"G", "O", "L", "I"};
86
87            char buf[256];
88            sprintf(buf, "PC = 0x%016llx", thread->readNextPC());
89            outs << buf;
90            sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC());
91            outs << buf;
92            newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
93            if(newVal != ccr)
94            {
95                sprintf(buf, " CCR = 0x%016llx", newVal);
96                outs << buf;
97                ccr = newVal;
98            }
99            newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
100            if(newVal != y)
101            {
102                sprintf(buf, " Y = 0x%016llx", newVal);
103                outs << buf;
104                y = newVal;
105            }
106            for(int y = 0; y < 4; y++)
107            {
108                for(int x = 0; x < 8; x++)
109                {
110                    int index = x + 8 * y;
111                    newVal = thread->readIntReg(index);
112                    if(regs[index] != newVal)
113                    {
114                        sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal);
115                        outs << buf;
116                        regs[index] = newVal;
117                    }
118                }
119            }
120            for(int y = 0; y < 32; y++)
121            {
122                newVal = thread->readFloatRegBits(2 * y, 64);
123                if(floats[y] != newVal)
124                {
125                    sprintf(buf, " F%d = 0x%016llx", 2 * y, newVal);
126                    outs << buf;
127                    floats[y] = newVal;
128                }
129            }
130            outs << endl;
131        }
132#endif
133#endif
134    }
135    else if (flags[INTEL_FORMAT]) {
136#if FULL_SYSTEM
137        bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system);
138#else
139        bool is_trace_system = true;
140#endif
141        if (is_trace_system) {
142            ccprintf(outs, "%7d ) ", cycle);
143            outs << "0x" << hex << PC << ":\t";
144            if (staticInst->isLoad()) {
145                outs << "<RD 0x" << hex << addr;
146                outs << ">";
147            } else if (staticInst->isStore()) {
148                outs << "<WR 0x" << hex << addr;
149                outs << ">";
150            }
151            outs << endl;
152        }
153    } else {
154        if (flags[PRINT_CYCLE])
155            ccprintf(outs, "%7d: ", cycle);
156
157        outs << thread->getCpuPtr()->name() << " ";
158
159        if (flags[TRACE_MISSPEC])
160            outs << (misspeculating ? "-" : "+") << " ";
161
162        if (flags[PRINT_THREAD_NUM])
163            outs << "T" << thread->getThreadNum() << " : ";
164
165
166        std::string sym_str;
167        Addr sym_addr;
168        if (debugSymbolTable
169            && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)
170            && flags[PC_SYMBOL]) {
171            if (PC != sym_addr)
172                sym_str += csprintf("+%d", PC - sym_addr);
173            outs << "@" << sym_str << " : ";
174        }
175        else {
176            outs << "0x" << hex << PC << " : ";
177        }
178
179        //
180        //  Print decoded instruction
181        //
182
183#if defined(__GNUC__) && (__GNUC__ < 3)
184        // There's a bug in gcc 2.x library that prevents setw()
185        // from working properly on strings
186        string mc(staticInst->disassemble(PC, debugSymbolTable));
187        while (mc.length() < 26)
188            mc += " ";
189        outs << mc;
190#else
191        outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable);
192#endif
193
194        outs << " : ";
195
196        if (flags[PRINT_OP_CLASS]) {
197            outs << opClassStrings[staticInst->opClass()] << " : ";
198        }
199
200        if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) {
201            outs << " D=";
202#if 0
203            if (data_status == DataDouble)
204                ccprintf(outs, "%f", data.as_double);
205            else
206                ccprintf(outs, "%#018x", data.as_int);
207#else
208            ccprintf(outs, "%#018x", data.as_int);
209#endif
210        }
211
212        if (flags[PRINT_EFF_ADDR] && addr_valid)
213            outs << " A=0x" << hex << addr;
214
215        if (flags[PRINT_INT_REGS] && regs_valid) {
216            for (int i = 0; i < TheISA::NumIntRegs;)
217                for (int j = i + 1; i <= j; i++)
218                    ccprintf(outs, "r%02d = %#018x%s", i,
219                            iregs->regs.readReg(i),
220                            ((i == j) ? "\n" : "    "));
221            outs << "\n";
222        }
223
224        if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid)
225            outs << "  FetchSeq=" << dec << fetch_seq;
226
227        if (flags[PRINT_CP_SEQ] && cp_seq_valid)
228            outs << "  CPSeq=" << dec << cp_seq;
229
230        //
231        //  End of line...
232        //
233        outs << endl;
234    }
235#if THE_ISA == SPARC_ISA
236    // Compare
237    if (flags[LEGION_LOCKSTEP])
238    {
239        bool compared = false;
240        bool diffPC   = false;
241        bool diffInst = false;
242        bool diffRegs = false;
243
244        if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
245            while (!compared) {
246                if (shared_data->flags == OWN_M5) {
247                    if (shared_data->pc != PC)
248                       diffPC = true;
249                    if (shared_data->instruction != staticInst->machInst)
250                        diffInst = true;
251                    for (int i = 0; i < TheISA::NumIntRegs; i++) {
252                        if (thread->readIntReg(i) != shared_data->intregs[i])
253                            diffRegs = true;
254                    }
255
256                    if (diffPC || diffInst || diffRegs ) {
257                        outs << "Differences found between M5 and Legion:";
258                        if (diffPC)
259                            outs << " [PC]";
260                        if (diffInst)
261                            outs << " [Instruction]";
262                        if (diffRegs)
263                            outs << " [IntRegs]";
264                        outs << endl << endl;;
265
266                        outs << setfill(' ') << setw(15)
267                             << "M5 PC: " << "0x"<< setw(16) << setfill('0')
268                             << hex << PC << endl;
269                        outs << setfill(' ') << setw(15)
270                             << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex
271                             << shared_data->pc << endl << endl;
272
273                        outs << setfill(' ') << setw(15)
274                             << "M5 Inst: "  << "0x"<< setw(8)
275                             << setfill('0') << hex << staticInst->machInst
276                             << staticInst->disassemble(PC, debugSymbolTable)
277                             << endl;
278
279                        StaticInstPtr legionInst = StaticInst::decode(makeExtMI(shared_data->instruction, thread));
280                        outs << setfill(' ') << setw(15)
281                             << " Legion Inst: "
282                             << "0x" << setw(8) << setfill('0') << hex
283                             << shared_data->instruction
284                             << legionInst->disassemble(shared_data->pc, debugSymbolTable)
285                             << endl;
286
287                        outs << endl;
288
289                        static const char * regtypes[4] = {"%g", "%o", "%l", "%i"};
290                        for(int y = 0; y < 4; y++)
291                        {
292                            for(int x = 0; x < 8; x++)
293                            {
294                                outs << regtypes[y] << x << "         " ;
295                                outs <<  "0x" << hex << setw(16) << thread->readIntReg(y*8+x);
296                                if (thread->readIntReg(y*8 + x) != shared_data->intregs[y*8+x])
297                                    outs << "     X     ";
298                                else
299                                    outs << "     |     ";
300                                outs << "0x" << setw(16) << hex << shared_data->intregs[y*8+x]
301                                     << endl;
302                            }
303                        }
304                        fatal("Differences found between Legion and M5\n");
305                    }
306
307                    compared = true;
308                    shared_data->flags = OWN_LEGION;
309                }
310            } // while
311        } // if not microop
312    }
313#endif
314}
315
316
317vector<bool> Trace::InstRecord::flags(NUM_BITS);
318string Trace::InstRecord::trace_system;
319
320////////////////////////////////////////////////////////////////////////
321//
322// Parameter space for per-cycle execution address tracing options.
323// Derive from ParamContext so we can override checkParams() function.
324//
325class ExecutionTraceParamContext : public ParamContext
326{
327  public:
328    ExecutionTraceParamContext(const string &_iniSection)
329        : ParamContext(_iniSection)
330        {
331        }
332
333    void checkParams();	// defined at bottom of file
334};
335
336ExecutionTraceParamContext exeTraceParams("exetrace");
337
338Param<bool> exe_trace_spec(&exeTraceParams, "speculative",
339                           "capture speculative instructions", true);
340
341Param<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle",
342                                  "print cycle number", true);
343Param<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass",
344                                  "print op class", true);
345Param<bool> exe_trace_print_thread(&exeTraceParams, "print_thread",
346                                  "print thread number", true);
347Param<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr",
348                                  "print effective address", true);
349Param<bool> exe_trace_print_data(&exeTraceParams, "print_data",
350                                  "print result data", true);
351Param<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs",
352                                  "print all integer regs", false);
353Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
354                                  "print fetch sequence number", false);
355Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
356                                  "print correct-path sequence number", false);
357Param<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta",
358                                  "print which registers changed to what", false);
359Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
360                                  "Use symbols for the PC if available", true);
361Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
362                                   "print trace in intel compatible format", false);
363Param<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep",
364                                   "Compare sim state to legion state every cycle",
365                                   false);
366Param<string> exe_trace_system(&exeTraceParams, "trace_system",
367                                   "print trace of which system (client or server)",
368                                   "client");
369
370
371//
372// Helper function for ExecutionTraceParamContext::checkParams() just
373// to get us into the InstRecord namespace
374//
375void
376Trace::InstRecord::setParams()
377{
378    flags[TRACE_MISSPEC]     = exe_trace_spec;
379
380    flags[PRINT_CYCLE]       = exe_trace_print_cycle;
381    flags[PRINT_OP_CLASS]    = exe_trace_print_opclass;
382    flags[PRINT_THREAD_NUM]  = exe_trace_print_thread;
383    flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr;
384    flags[PRINT_EFF_ADDR]    = exe_trace_print_data;
385    flags[PRINT_INT_REGS]    = exe_trace_print_iregs;
386    flags[PRINT_FETCH_SEQ]   = exe_trace_print_fetchseq;
387    flags[PRINT_CP_SEQ]      = exe_trace_print_cp_seq;
388    flags[PRINT_REG_DELTA]   = exe_trace_print_reg_delta;
389    flags[PC_SYMBOL]         = exe_trace_pc_symbol;
390    flags[INTEL_FORMAT]      = exe_trace_intel_format;
391    flags[LEGION_LOCKSTEP]   = exe_trace_legion_lockstep;
392    trace_system	     = exe_trace_system;
393
394    // If were going to be in lockstep with Legion
395    // Setup shared memory, and get otherwise ready
396    if (flags[LEGION_LOCKSTEP]) {
397        int shmfd = shmget(getuid(), sizeof(SharedData), 0777);
398        if (shmfd < 0)
399            fatal("Couldn't get shared memory fd. Is Legion running?");
400
401        shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND);
402        if (shared_data == (SharedData*)-1)
403            fatal("Couldn't allocate shared memory");
404
405        if (shared_data->flags != OWN_M5)
406            fatal("Shared memory has invalid owner");
407
408        if (shared_data->version != VERSION)
409            fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION,
410                    shared_data->version);
411
412    }
413}
414
415void
416ExecutionTraceParamContext::checkParams()
417{
418    Trace::InstRecord::setParams();
419}
420
421