exetrace.cc revision 5784
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <iomanip> 352SN/A 3656SN/A#include "base/loader/symtab.hh" 371717SN/A#include "cpu/base.hh" 382518SN/A#include "cpu/exetrace.hh" 3956SN/A#include "cpu/static_inst.hh" 404776Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 414762Snate@binkert.org#include "enums/OpClass.hh" 423065Sgblack@eecs.umich.edu 432SN/Ausing namespace std; 442973Sgblack@eecs.umich.eduusing namespace TheISA; 452SN/A 463506Ssaidi@eecs.umich.edunamespace Trace { 474054Sbinkertn@umich.edu 484054Sbinkertn@umich.eduvoid 495784Sgblack@eecs.umich.eduTrace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran) 504054Sbinkertn@umich.edu{ 514776Sgblack@eecs.umich.edu ostream &outs = Trace::output(); 524054Sbinkertn@umich.edu 534776Sgblack@eecs.umich.edu if (IsOn(ExecTicks)) 544776Sgblack@eecs.umich.edu ccprintf(outs, "%7d: ", when); 554054Sbinkertn@umich.edu 564776Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 574054Sbinkertn@umich.edu 584776Sgblack@eecs.umich.edu if (IsOn(ExecSpeculative)) 594776Sgblack@eecs.umich.edu outs << (misspeculating ? "-" : "+") << " "; 604054Sbinkertn@umich.edu 614776Sgblack@eecs.umich.edu if (IsOn(ExecThread)) 625715Shsul@eecs.umich.edu outs << "T" << thread->threadId() << " : "; 634776Sgblack@eecs.umich.edu 644776Sgblack@eecs.umich.edu std::string sym_str; 654776Sgblack@eecs.umich.edu Addr sym_addr; 664776Sgblack@eecs.umich.edu if (debugSymbolTable 674776Sgblack@eecs.umich.edu && IsOn(ExecSymbol) 684776Sgblack@eecs.umich.edu && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) { 694776Sgblack@eecs.umich.edu if (PC != sym_addr) 704776Sgblack@eecs.umich.edu sym_str += csprintf("+%d", PC - sym_addr); 715784Sgblack@eecs.umich.edu outs << "@" << sym_str; 724776Sgblack@eecs.umich.edu } 734776Sgblack@eecs.umich.edu else { 745784Sgblack@eecs.umich.edu outs << "0x" << hex << PC; 754776Sgblack@eecs.umich.edu } 764776Sgblack@eecs.umich.edu 775784Sgblack@eecs.umich.edu if (inst->isMicroop()) { 785784Sgblack@eecs.umich.edu outs << "." << setw(2) << dec << upc; 795784Sgblack@eecs.umich.edu } else { 805784Sgblack@eecs.umich.edu outs << " "; 815784Sgblack@eecs.umich.edu } 825784Sgblack@eecs.umich.edu 835784Sgblack@eecs.umich.edu outs << " : "; 845784Sgblack@eecs.umich.edu 854776Sgblack@eecs.umich.edu // 864776Sgblack@eecs.umich.edu // Print decoded instruction 874776Sgblack@eecs.umich.edu // 884776Sgblack@eecs.umich.edu 894776Sgblack@eecs.umich.edu outs << setw(26) << left; 905784Sgblack@eecs.umich.edu outs << inst->disassemble(PC, debugSymbolTable); 914776Sgblack@eecs.umich.edu 925784Sgblack@eecs.umich.edu if (ran) { 935784Sgblack@eecs.umich.edu outs << " : "; 945784Sgblack@eecs.umich.edu 955784Sgblack@eecs.umich.edu if (IsOn(ExecOpClass)) { 965784Sgblack@eecs.umich.edu outs << Enums::OpClassStrings[inst->opClass()] << " : "; 975784Sgblack@eecs.umich.edu } 985784Sgblack@eecs.umich.edu 995784Sgblack@eecs.umich.edu if (IsOn(ExecResult) && data_status != DataInvalid) { 1005784Sgblack@eecs.umich.edu ccprintf(outs, " D=%#018x", data.as_int); 1015784Sgblack@eecs.umich.edu } 1025784Sgblack@eecs.umich.edu 1035784Sgblack@eecs.umich.edu if (IsOn(ExecEffAddr) && addr_valid) 1045784Sgblack@eecs.umich.edu outs << " A=0x" << hex << addr; 1055784Sgblack@eecs.umich.edu 1065784Sgblack@eecs.umich.edu if (IsOn(ExecFetchSeq) && fetch_seq_valid) 1075784Sgblack@eecs.umich.edu outs << " FetchSeq=" << dec << fetch_seq; 1085784Sgblack@eecs.umich.edu 1095784Sgblack@eecs.umich.edu if (IsOn(ExecCPSeq) && cp_seq_valid) 1105784Sgblack@eecs.umich.edu outs << " CPSeq=" << dec << cp_seq; 1114776Sgblack@eecs.umich.edu } 1124776Sgblack@eecs.umich.edu 1134776Sgblack@eecs.umich.edu // 1144776Sgblack@eecs.umich.edu // End of line... 1154776Sgblack@eecs.umich.edu // 1164776Sgblack@eecs.umich.edu outs << endl; 1173506Ssaidi@eecs.umich.edu} 1183506Ssaidi@eecs.umich.edu 1195784Sgblack@eecs.umich.eduvoid 1205784Sgblack@eecs.umich.eduTrace::ExeTracerRecord::dump() 1215784Sgblack@eecs.umich.edu{ 1225784Sgblack@eecs.umich.edu /* 1235784Sgblack@eecs.umich.edu * The behavior this check tries to achieve is that if ExecMacro is on, 1245784Sgblack@eecs.umich.edu * the macroop will be printed. If it's on and microops are also on, it's 1255784Sgblack@eecs.umich.edu * printed before the microops start printing to give context. If the 1265784Sgblack@eecs.umich.edu * microops aren't printed, then it's printed only when the final microop 1275784Sgblack@eecs.umich.edu * finishes. Macroops then behave like regular instructions and don't 1285784Sgblack@eecs.umich.edu * complete/print when they fault. 1295784Sgblack@eecs.umich.edu */ 1305784Sgblack@eecs.umich.edu if (IsOn(ExecMacro) && staticInst->isMicroop() && 1315784Sgblack@eecs.umich.edu (IsOn(ExecMicro) && 1325784Sgblack@eecs.umich.edu macroStaticInst && staticInst->isFirstMicroop()) || 1335784Sgblack@eecs.umich.edu (!IsOn(ExecMicro) && 1345784Sgblack@eecs.umich.edu macroStaticInst && staticInst->isLastMicroop())) { 1355784Sgblack@eecs.umich.edu traceInst(macroStaticInst, false); 1365784Sgblack@eecs.umich.edu } 1375784Sgblack@eecs.umich.edu if (IsOn(ExecMicro) || !staticInst->isMicroop()) { 1385784Sgblack@eecs.umich.edu traceInst(staticInst, true); 1395784Sgblack@eecs.umich.edu } 1405784Sgblack@eecs.umich.edu} 1415784Sgblack@eecs.umich.edu 1424776Sgblack@eecs.umich.edu/* namespace Trace */ } 1434776Sgblack@eecs.umich.edu 1442SN/A//////////////////////////////////////////////////////////////////////// 1452SN/A// 1464776Sgblack@eecs.umich.edu// ExeTracer Simulation Object 1472SN/A// 1484776Sgblack@eecs.umich.eduTrace::ExeTracer * 1494776Sgblack@eecs.umich.eduExeTracerParams::create() 1503748Sgblack@eecs.umich.edu{ 1515034Smilesck@eecs.umich.edu return new Trace::ExeTracer(this); 1524776Sgblack@eecs.umich.edu}; 153