exetrace.cc revision 4265
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 344265Sgblack@eecs.umich.edu#include <errno.h> 352SN/A#include <fstream> 362SN/A#include <iomanip> 373506Ssaidi@eecs.umich.edu#include <sys/ipc.h> 383506Ssaidi@eecs.umich.edu#include <sys/shm.h> 392SN/A 402973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 413584Ssaidi@eecs.umich.edu#include "arch/utility.hh" 4256SN/A#include "base/loader/symtab.hh" 434265Sgblack@eecs.umich.edu#include "base/socket.hh" 443614Sgblack@eecs.umich.edu#include "config/full_system.hh" 451717SN/A#include "cpu/base.hh" 462518SN/A#include "cpu/exetrace.hh" 4756SN/A#include "cpu/static_inst.hh" 482518SN/A#include "sim/param.hh" 492518SN/A#include "sim/system.hh" 502SN/A 513614Sgblack@eecs.umich.edu#if FULL_SYSTEM 523614Sgblack@eecs.umich.edu#include "arch/tlb.hh" 533614Sgblack@eecs.umich.edu#endif 543614Sgblack@eecs.umich.edu 553065Sgblack@eecs.umich.edu//XXX This is temporary 563065Sgblack@eecs.umich.edu#include "arch/isa_specific.hh" 573506Ssaidi@eecs.umich.edu#include "cpu/m5legion_interface.h" 583065Sgblack@eecs.umich.edu 592SN/Ausing namespace std; 602973Sgblack@eecs.umich.eduusing namespace TheISA; 612SN/A 623840Shsul@eecs.umich.edu#if THE_ISA == SPARC_ISA && FULL_SYSTEM 633825Ssaidi@eecs.umich.edustatic int diffcount = 0; 643903Ssaidi@eecs.umich.edustatic bool wasMicro = false; 653840Shsul@eecs.umich.edu#endif 663825Ssaidi@eecs.umich.edu 673506Ssaidi@eecs.umich.edunamespace Trace { 683506Ssaidi@eecs.umich.eduSharedData *shared_data = NULL; 694265Sgblack@eecs.umich.eduListenSocket *cosim_listener = NULL; 704054Sbinkertn@umich.edu 714054Sbinkertn@umich.eduvoid 724054Sbinkertn@umich.edusetupSharedData() 734054Sbinkertn@umich.edu{ 744054Sbinkertn@umich.edu int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777); 754054Sbinkertn@umich.edu if (shmfd < 0) 764054Sbinkertn@umich.edu fatal("Couldn't get shared memory fd. Is Legion running?"); 774054Sbinkertn@umich.edu 784054Sbinkertn@umich.edu shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 794054Sbinkertn@umich.edu if (shared_data == (SharedData*)-1) 804054Sbinkertn@umich.edu fatal("Couldn't allocate shared memory"); 814054Sbinkertn@umich.edu 824054Sbinkertn@umich.edu if (shared_data->flags != OWN_M5) 834054Sbinkertn@umich.edu fatal("Shared memory has invalid owner"); 844054Sbinkertn@umich.edu 854054Sbinkertn@umich.edu if (shared_data->version != VERSION) 864054Sbinkertn@umich.edu fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 874054Sbinkertn@umich.edu shared_data->version); 884054Sbinkertn@umich.edu 894054Sbinkertn@umich.edu // step legion forward one cycle so we can get register values 904054Sbinkertn@umich.edu shared_data->flags = OWN_LEGION; 913506Ssaidi@eecs.umich.edu} 923506Ssaidi@eecs.umich.edu 932SN/A//////////////////////////////////////////////////////////////////////// 942SN/A// 952SN/A// Methods for the InstRecord object 962SN/A// 972SN/A 983748Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 993748Sgblack@eecs.umich.edu 1003748Sgblack@eecs.umich.eduinline char * genCenteredLabel(int length, char * buffer, char * label) 1013748Sgblack@eecs.umich.edu{ 1023748Sgblack@eecs.umich.edu int labelLength = strlen(label); 1033748Sgblack@eecs.umich.edu assert(labelLength <= length); 1043748Sgblack@eecs.umich.edu int leftPad = (length - labelLength) / 2; 1053748Sgblack@eecs.umich.edu int rightPad = length - leftPad - labelLength; 1063748Sgblack@eecs.umich.edu char format[64]; 1073748Sgblack@eecs.umich.edu sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad); 1083748Sgblack@eecs.umich.edu sprintf(buffer, format, "", label, ""); 1093748Sgblack@eecs.umich.edu return buffer; 1103748Sgblack@eecs.umich.edu} 1113748Sgblack@eecs.umich.edu 1123748Sgblack@eecs.umich.eduinline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b) 1133748Sgblack@eecs.umich.edu{ 1143748Sgblack@eecs.umich.edu ccprintf(os, " %16s | %#018x %s %#-018x \n", 1153748Sgblack@eecs.umich.edu title, a, (a == b) ? "|" : "X", b); 1163748Sgblack@eecs.umich.edu} 1173748Sgblack@eecs.umich.edu 1183748Sgblack@eecs.umich.eduinline void printColumnLabels(ostream & os) 1193748Sgblack@eecs.umich.edu{ 1203748Sgblack@eecs.umich.edu static char * regLabel = genCenteredLabel(16, new char[17], "Register"); 1213748Sgblack@eecs.umich.edu static char * m5Label = genCenteredLabel(18, new char[18], "M5"); 1223748Sgblack@eecs.umich.edu static char * legionLabel = genCenteredLabel(18, new char[18], "Legion"); 1233748Sgblack@eecs.umich.edu ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel); 1243748Sgblack@eecs.umich.edu ccprintf(os, "--------------------+-----------------------+-----------------------\n"); 1253748Sgblack@eecs.umich.edu} 1263748Sgblack@eecs.umich.edu 1273748Sgblack@eecs.umich.eduinline void printSectionHeader(ostream & os, char * name) 1283748Sgblack@eecs.umich.edu{ 1293748Sgblack@eecs.umich.edu char sectionString[70]; 1303748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, name); 1313748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1323748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1333748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1343748Sgblack@eecs.umich.edu} 1353748Sgblack@eecs.umich.edu 1363748Sgblack@eecs.umich.eduinline void printLevelHeader(ostream & os, int level) 1373748Sgblack@eecs.umich.edu{ 1383748Sgblack@eecs.umich.edu char sectionString[70]; 1393748Sgblack@eecs.umich.edu char levelName[70]; 1403748Sgblack@eecs.umich.edu sprintf(levelName, "Trap stack level %d", level); 1413748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, levelName); 1423748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1433748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1443748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1453748Sgblack@eecs.umich.edu} 1463748Sgblack@eecs.umich.edu 1473748Sgblack@eecs.umich.edu#endif 1482SN/A 1492SN/Avoid 1504046Sbinkertn@umich.eduTrace::InstRecord::dump() 1512SN/A{ 1524046Sbinkertn@umich.edu ostream &outs = Trace::output(); 1534046Sbinkertn@umich.edu 1543903Ssaidi@eecs.umich.edu DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst); 1554265Sgblack@eecs.umich.edu bool diff = true; 1564054Sbinkertn@umich.edu if (IsOn(ExecRegDelta)) 1572973Sgblack@eecs.umich.edu { 1584265Sgblack@eecs.umich.edu diff = false; 1594265Sgblack@eecs.umich.edu#ifndef NDEBUG 1603065Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 1614265Sgblack@eecs.umich.edu static int fd = 0; 1624265Sgblack@eecs.umich.edu //Don't print what happens for each micro-op, just print out 1634265Sgblack@eecs.umich.edu //once at the last op, and for regular instructions. 1644265Sgblack@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 1654265Sgblack@eecs.umich.edu { 1664265Sgblack@eecs.umich.edu if(!cosim_listener) 1674265Sgblack@eecs.umich.edu { 1684265Sgblack@eecs.umich.edu int port = 8000; 1694265Sgblack@eecs.umich.edu cosim_listener = new ListenSocket(); 1704265Sgblack@eecs.umich.edu while(!cosim_listener->listen(port, true)) 1714265Sgblack@eecs.umich.edu { 1724265Sgblack@eecs.umich.edu DPRINTF(GDBMisc, "Can't bind port %d\n", port); 1734265Sgblack@eecs.umich.edu port++; 1744265Sgblack@eecs.umich.edu } 1754265Sgblack@eecs.umich.edu ccprintf(cerr, "Listening for cosimulator on port %d\n", port); 1764265Sgblack@eecs.umich.edu fd = cosim_listener->accept(); 1774265Sgblack@eecs.umich.edu } 1784265Sgblack@eecs.umich.edu char prefix[] = "goli"; 1794265Sgblack@eecs.umich.edu for(int p = 0; p < 4; p++) 1804265Sgblack@eecs.umich.edu { 1814265Sgblack@eecs.umich.edu for(int i = 0; i < 8; i++) 1824265Sgblack@eecs.umich.edu { 1834265Sgblack@eecs.umich.edu uint64_t regVal; 1844265Sgblack@eecs.umich.edu int res = read(fd, ®Val, sizeof(regVal)); 1854265Sgblack@eecs.umich.edu if(res < 0) 1864265Sgblack@eecs.umich.edu panic("First read call failed! %s\n", strerror(errno)); 1874265Sgblack@eecs.umich.edu regVal = TheISA::gtoh(regVal); 1884265Sgblack@eecs.umich.edu uint64_t realRegVal = thread->readIntReg(p * 8 + i); 1894265Sgblack@eecs.umich.edu if((regVal & 0xffffffffULL) != (realRegVal & 0xffffffffULL)) 1904265Sgblack@eecs.umich.edu { 1914265Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "Register %s%d should be %#x but is %#x.\n", prefix[p], i, regVal, realRegVal); 1924265Sgblack@eecs.umich.edu diff = true; 1934265Sgblack@eecs.umich.edu } 1944265Sgblack@eecs.umich.edu //ccprintf(outs, "%s%d m5 = %#x statetrace = %#x\n", prefix[p], i, realRegVal, regVal); 1954265Sgblack@eecs.umich.edu } 1964265Sgblack@eecs.umich.edu } 1974265Sgblack@eecs.umich.edu /*for(int f = 0; f <= 62; f+=2) 1984265Sgblack@eecs.umich.edu { 1994265Sgblack@eecs.umich.edu uint64_t regVal; 2004265Sgblack@eecs.umich.edu int res = read(fd, ®Val, sizeof(regVal)); 2014265Sgblack@eecs.umich.edu if(res < 0) 2024265Sgblack@eecs.umich.edu panic("First read call failed! %s\n", strerror(errno)); 2034265Sgblack@eecs.umich.edu regVal = TheISA::gtoh(regVal); 2044265Sgblack@eecs.umich.edu uint64_t realRegVal = thread->readFloatRegBits(f, 64); 2054265Sgblack@eecs.umich.edu if(regVal != realRegVal) 2064265Sgblack@eecs.umich.edu { 2074265Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "Register f%d should be %#x but is %#x.\n", f, regVal, realRegVal); 2084265Sgblack@eecs.umich.edu } 2094265Sgblack@eecs.umich.edu }*/ 2104265Sgblack@eecs.umich.edu uint64_t regVal; 2114265Sgblack@eecs.umich.edu int res = read(fd, ®Val, sizeof(regVal)); 2124265Sgblack@eecs.umich.edu if(res < 0) 2134265Sgblack@eecs.umich.edu panic("First read call failed! %s\n", strerror(errno)); 2144265Sgblack@eecs.umich.edu regVal = TheISA::gtoh(regVal); 2154265Sgblack@eecs.umich.edu uint64_t realRegVal = thread->readNextPC(); 2164265Sgblack@eecs.umich.edu if(regVal != realRegVal) 2174265Sgblack@eecs.umich.edu { 2184265Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "Register pc should be %#x but is %#x.\n", regVal, realRegVal); 2194265Sgblack@eecs.umich.edu diff = true; 2204265Sgblack@eecs.umich.edu } 2214265Sgblack@eecs.umich.edu res = read(fd, ®Val, sizeof(regVal)); 2224265Sgblack@eecs.umich.edu if(res < 0) 2234265Sgblack@eecs.umich.edu panic("First read call failed! %s\n", strerror(errno)); 2244265Sgblack@eecs.umich.edu regVal = TheISA::gtoh(regVal); 2254265Sgblack@eecs.umich.edu realRegVal = thread->readNextNPC(); 2264265Sgblack@eecs.umich.edu if(regVal != realRegVal) 2274265Sgblack@eecs.umich.edu { 2284265Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "Register npc should be %#x but is %#x.\n", regVal, realRegVal); 2294265Sgblack@eecs.umich.edu diff = true; 2304265Sgblack@eecs.umich.edu } 2314265Sgblack@eecs.umich.edu res = read(fd, ®Val, sizeof(regVal)); 2324265Sgblack@eecs.umich.edu if(res < 0) 2334265Sgblack@eecs.umich.edu panic("First read call failed! %s\n", strerror(errno)); 2344265Sgblack@eecs.umich.edu regVal = TheISA::gtoh(regVal); 2354265Sgblack@eecs.umich.edu realRegVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2); 2364265Sgblack@eecs.umich.edu if((regVal & 0xF) != (realRegVal & 0xF)) 2374265Sgblack@eecs.umich.edu { 2384265Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "Register ccr should be %#x but is %#x.\n", regVal, realRegVal); 2394265Sgblack@eecs.umich.edu diff = true; 2404265Sgblack@eecs.umich.edu } 2414265Sgblack@eecs.umich.edu } 2424265Sgblack@eecs.umich.edu#endif 2434265Sgblack@eecs.umich.edu#endif 2444265Sgblack@eecs.umich.edu#if 0 //THE_ISA == SPARC_ISA 2453380Sgblack@eecs.umich.edu //Don't print what happens for each micro-op, just print out 2463380Sgblack@eecs.umich.edu //once at the last op, and for regular instructions. 2473380Sgblack@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 2483380Sgblack@eecs.umich.edu { 2493380Sgblack@eecs.umich.edu static uint64_t regs[32] = { 2503380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 2513380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 2523380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 2533380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 2543380Sgblack@eecs.umich.edu static uint64_t ccr = 0; 2553380Sgblack@eecs.umich.edu static uint64_t y = 0; 2563380Sgblack@eecs.umich.edu static uint64_t floats[32]; 2573380Sgblack@eecs.umich.edu uint64_t newVal; 2583380Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 2593065Sgblack@eecs.umich.edu 2603588Sgblack@eecs.umich.edu outs << hex; 2613588Sgblack@eecs.umich.edu outs << "PC = " << thread->readNextPC(); 2623588Sgblack@eecs.umich.edu outs << " NPC = " << thread->readNextNPC(); 2633790Sgblack@eecs.umich.edu newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2); 2644172Ssaidi@eecs.umich.edu //newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_CCR); 2653380Sgblack@eecs.umich.edu if(newVal != ccr) 2663059Sgblack@eecs.umich.edu { 2673588Sgblack@eecs.umich.edu outs << " CCR = " << newVal; 2683380Sgblack@eecs.umich.edu ccr = newVal; 2693380Sgblack@eecs.umich.edu } 2703790Sgblack@eecs.umich.edu newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 1); 2714172Ssaidi@eecs.umich.edu //newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_Y); 2723380Sgblack@eecs.umich.edu if(newVal != y) 2733380Sgblack@eecs.umich.edu { 2743588Sgblack@eecs.umich.edu outs << " Y = " << newVal; 2753380Sgblack@eecs.umich.edu y = newVal; 2763380Sgblack@eecs.umich.edu } 2773380Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 2783380Sgblack@eecs.umich.edu { 2793380Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 2803059Sgblack@eecs.umich.edu { 2813380Sgblack@eecs.umich.edu int index = x + 8 * y; 2823380Sgblack@eecs.umich.edu newVal = thread->readIntReg(index); 2833380Sgblack@eecs.umich.edu if(regs[index] != newVal) 2843380Sgblack@eecs.umich.edu { 2853588Sgblack@eecs.umich.edu outs << " " << prefixes[y] << dec << x << " = " << hex << newVal; 2863380Sgblack@eecs.umich.edu regs[index] = newVal; 2873380Sgblack@eecs.umich.edu } 2883059Sgblack@eecs.umich.edu } 2893059Sgblack@eecs.umich.edu } 2903380Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 2913380Sgblack@eecs.umich.edu { 2923380Sgblack@eecs.umich.edu newVal = thread->readFloatRegBits(2 * y, 64); 2933380Sgblack@eecs.umich.edu if(floats[y] != newVal) 2943380Sgblack@eecs.umich.edu { 2953588Sgblack@eecs.umich.edu outs << " F" << dec << (2 * y) << " = " << hex << newVal; 2963380Sgblack@eecs.umich.edu floats[y] = newVal; 2973380Sgblack@eecs.umich.edu } 2983380Sgblack@eecs.umich.edu } 2993588Sgblack@eecs.umich.edu outs << dec << endl; 3003059Sgblack@eecs.umich.edu } 3013065Sgblack@eecs.umich.edu#endif 3022973Sgblack@eecs.umich.edu } 3034265Sgblack@eecs.umich.edu if(!diff) { 3044265Sgblack@eecs.umich.edu } else if (IsOn(ExecIntel)) { 3054054Sbinkertn@umich.edu ccprintf(outs, "%7d ) ", when); 3064054Sbinkertn@umich.edu outs << "0x" << hex << PC << ":\t"; 3074054Sbinkertn@umich.edu if (staticInst->isLoad()) { 3084054Sbinkertn@umich.edu ccprintf(outs, "<RD %#x>", addr); 3094054Sbinkertn@umich.edu } else if (staticInst->isStore()) { 3104054Sbinkertn@umich.edu ccprintf(outs, "<WR %#x>", addr); 3111904SN/A } 3124054Sbinkertn@umich.edu outs << endl; 3131904SN/A } else { 3144054Sbinkertn@umich.edu if (IsOn(ExecTicks)) 3154046Sbinkertn@umich.edu ccprintf(outs, "%7d: ", when); 316452SN/A 3173064Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 3182SN/A 3194054Sbinkertn@umich.edu if (IsOn(ExecSpeculative)) 3201904SN/A outs << (misspeculating ? "-" : "+") << " "; 3212SN/A 3224054Sbinkertn@umich.edu if (IsOn(ExecThread)) 3233064Sgblack@eecs.umich.edu outs << "T" << thread->getThreadNum() << " : "; 3242SN/A 3252SN/A 3261904SN/A std::string sym_str; 3271904SN/A Addr sym_addr; 3281904SN/A if (debugSymbolTable 3292299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 3304054Sbinkertn@umich.edu && IsOn(ExecSymbol)) { 3311904SN/A if (PC != sym_addr) 3321904SN/A sym_str += csprintf("+%d", PC - sym_addr); 3331904SN/A outs << "@" << sym_str << " : "; 3341904SN/A } 3351904SN/A else { 3361904SN/A outs << "0x" << hex << PC << " : "; 3371904SN/A } 338452SN/A 3391904SN/A // 3401904SN/A // Print decoded instruction 3411904SN/A // 3422SN/A 3432SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 3441904SN/A // There's a bug in gcc 2.x library that prevents setw() 3451904SN/A // from working properly on strings 3461904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 3471904SN/A while (mc.length() < 26) 3481904SN/A mc += " "; 3491904SN/A outs << mc; 3502SN/A#else 3511904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 3522SN/A#endif 3532SN/A 3541904SN/A outs << " : "; 3552SN/A 3564054Sbinkertn@umich.edu if (IsOn(ExecOpClass)) { 3571904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 3581904SN/A } 3591904SN/A 3604054Sbinkertn@umich.edu if (IsOn(ExecResult) && data_status != DataInvalid) { 3611904SN/A outs << " D="; 3621904SN/A#if 0 3631904SN/A if (data_status == DataDouble) 3641904SN/A ccprintf(outs, "%f", data.as_double); 3651904SN/A else 3661904SN/A ccprintf(outs, "%#018x", data.as_int); 3671904SN/A#else 3681904SN/A ccprintf(outs, "%#018x", data.as_int); 3691904SN/A#endif 3701904SN/A } 3711904SN/A 3724054Sbinkertn@umich.edu if (IsOn(ExecEffAddr) && addr_valid) 3731904SN/A outs << " A=0x" << hex << addr; 3741904SN/A 3754054Sbinkertn@umich.edu if (IsOn(ExecIntRegs) && regs_valid) { 3762525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 3771904SN/A for (int j = i + 1; i <= j; i++) 3782525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 3792525SN/A iregs->regs.readReg(i), 3802525SN/A ((i == j) ? "\n" : " ")); 3811904SN/A outs << "\n"; 3821904SN/A } 3831904SN/A 3844054Sbinkertn@umich.edu if (IsOn(ExecFetchSeq) && fetch_seq_valid) 3851904SN/A outs << " FetchSeq=" << dec << fetch_seq; 3861904SN/A 3874054Sbinkertn@umich.edu if (IsOn(ExecCPSeq) && cp_seq_valid) 3881904SN/A outs << " CPSeq=" << dec << cp_seq; 3891967SN/A 3901967SN/A // 3911967SN/A // End of line... 3921967SN/A // 3931967SN/A outs << endl; 3942SN/A } 3953817Ssaidi@eecs.umich.edu#if THE_ISA == SPARC_ISA && FULL_SYSTEM 3963506Ssaidi@eecs.umich.edu // Compare 3974054Sbinkertn@umich.edu if (IsOn(ExecLegion)) 3983506Ssaidi@eecs.umich.edu { 3993506Ssaidi@eecs.umich.edu bool compared = false; 4003506Ssaidi@eecs.umich.edu bool diffPC = false; 4013814Ssaidi@eecs.umich.edu bool diffCC = false; 4023506Ssaidi@eecs.umich.edu bool diffInst = false; 4033931Ssaidi@eecs.umich.edu bool diffIntRegs = false; 4043931Ssaidi@eecs.umich.edu bool diffFpRegs = false; 4053748Sgblack@eecs.umich.edu bool diffTpc = false; 4063748Sgblack@eecs.umich.edu bool diffTnpc = false; 4073748Sgblack@eecs.umich.edu bool diffTstate = false; 4083748Sgblack@eecs.umich.edu bool diffTt = false; 4093748Sgblack@eecs.umich.edu bool diffTba = false; 4103748Sgblack@eecs.umich.edu bool diffHpstate = false; 4113748Sgblack@eecs.umich.edu bool diffHtstate = false; 4123748Sgblack@eecs.umich.edu bool diffHtba = false; 4133748Sgblack@eecs.umich.edu bool diffPstate = false; 4143748Sgblack@eecs.umich.edu bool diffY = false; 4154001Ssaidi@eecs.umich.edu bool diffFsr = false; 4163748Sgblack@eecs.umich.edu bool diffCcr = false; 4173748Sgblack@eecs.umich.edu bool diffTl = false; 4183748Sgblack@eecs.umich.edu bool diffGl = false; 4193748Sgblack@eecs.umich.edu bool diffAsi = false; 4203748Sgblack@eecs.umich.edu bool diffPil = false; 4213748Sgblack@eecs.umich.edu bool diffCwp = false; 4223748Sgblack@eecs.umich.edu bool diffCansave = false; 4233748Sgblack@eecs.umich.edu bool diffCanrestore = false; 4243748Sgblack@eecs.umich.edu bool diffOtherwin = false; 4253748Sgblack@eecs.umich.edu bool diffCleanwin = false; 4263880Ssaidi@eecs.umich.edu bool diffTlb = false; 4273603Ssaidi@eecs.umich.edu Addr m5Pc, lgnPc; 4283603Ssaidi@eecs.umich.edu 4294054Sbinkertn@umich.edu if (!shared_data) 4304054Sbinkertn@umich.edu setupSharedData(); 4314054Sbinkertn@umich.edu 4323903Ssaidi@eecs.umich.edu // We took a trap on a micro-op... 4333903Ssaidi@eecs.umich.edu if (wasMicro && !staticInst->isMicroOp()) 4343903Ssaidi@eecs.umich.edu { 4354046Sbinkertn@umich.edu // let's skip comparing this tick 4363903Ssaidi@eecs.umich.edu while (!compared) 4373903Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 4383903Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 4393903Ssaidi@eecs.umich.edu compared = true; 4403903Ssaidi@eecs.umich.edu } 4413903Ssaidi@eecs.umich.edu compared = false; 4423903Ssaidi@eecs.umich.edu wasMicro = false; 4433903Ssaidi@eecs.umich.edu } 4443903Ssaidi@eecs.umich.edu 4453903Ssaidi@eecs.umich.edu if (staticInst->isLastMicroOp()) 4463903Ssaidi@eecs.umich.edu wasMicro = false; 4473903Ssaidi@eecs.umich.edu else if (staticInst->isMicroOp()) 4483903Ssaidi@eecs.umich.edu wasMicro = true; 4493903Ssaidi@eecs.umich.edu 4503506Ssaidi@eecs.umich.edu 4513584Ssaidi@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { 4523584Ssaidi@eecs.umich.edu while (!compared) { 4533584Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 4543748Sgblack@eecs.umich.edu m5Pc = PC & TheISA::PAddrImplMask; 4553928Ssaidi@eecs.umich.edu if (bits(shared_data->pstate,3,3)) { 4563928Ssaidi@eecs.umich.edu m5Pc &= mask(32); 4573928Ssaidi@eecs.umich.edu } 4583748Sgblack@eecs.umich.edu lgnPc = shared_data->pc & TheISA::PAddrImplMask; 4593603Ssaidi@eecs.umich.edu if (lgnPc != m5Pc) 4603584Ssaidi@eecs.umich.edu diffPC = true; 4613814Ssaidi@eecs.umich.edu 4623814Ssaidi@eecs.umich.edu if (shared_data->cycle_count != 4633814Ssaidi@eecs.umich.edu thread->getCpuPtr()->instCount()) 4643814Ssaidi@eecs.umich.edu diffCC = true; 4653814Ssaidi@eecs.umich.edu 4663743Sgblack@eecs.umich.edu if (shared_data->instruction != 4673743Sgblack@eecs.umich.edu (SparcISA::MachInst)staticInst->machInst) { 4683584Ssaidi@eecs.umich.edu diffInst = true; 4693743Sgblack@eecs.umich.edu } 4703989Ssaidi@eecs.umich.edu // assume we have %g0 working correctly 4713989Ssaidi@eecs.umich.edu for (int i = 1; i < TheISA::NumIntArchRegs; i++) { 4723603Ssaidi@eecs.umich.edu if (thread->readIntReg(i) != shared_data->intregs[i]) { 4733931Ssaidi@eecs.umich.edu diffIntRegs = true; 4743603Ssaidi@eecs.umich.edu } 4753584Ssaidi@eecs.umich.edu } 4763931Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumFloatRegs/2; i++) { 4773945Ssaidi@eecs.umich.edu if (thread->readFloatRegBits(i*2,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) { 4783931Ssaidi@eecs.umich.edu diffFpRegs = true; 4793931Ssaidi@eecs.umich.edu } 4803931Ssaidi@eecs.umich.edu } 4814172Ssaidi@eecs.umich.edu uint64_t oldTl = thread->readMiscRegNoEffect(MISCREG_TL); 4823748Sgblack@eecs.umich.edu if (oldTl != shared_data->tl) 4833748Sgblack@eecs.umich.edu diffTl = true; 4843748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 4854172Ssaidi@eecs.umich.edu thread->setMiscRegNoEffect(MISCREG_TL, i); 4864172Ssaidi@eecs.umich.edu if (thread->readMiscRegNoEffect(MISCREG_TPC) != 4873815Ssaidi@eecs.umich.edu shared_data->tpc[i-1]) 4883748Sgblack@eecs.umich.edu diffTpc = true; 4894172Ssaidi@eecs.umich.edu if (thread->readMiscRegNoEffect(MISCREG_TNPC) != 4903815Ssaidi@eecs.umich.edu shared_data->tnpc[i-1]) 4913748Sgblack@eecs.umich.edu diffTnpc = true; 4924172Ssaidi@eecs.umich.edu if (thread->readMiscRegNoEffect(MISCREG_TSTATE) != 4933815Ssaidi@eecs.umich.edu shared_data->tstate[i-1]) 4943748Sgblack@eecs.umich.edu diffTstate = true; 4954172Ssaidi@eecs.umich.edu if (thread->readMiscRegNoEffect(MISCREG_TT) != 4963815Ssaidi@eecs.umich.edu shared_data->tt[i-1]) 4973748Sgblack@eecs.umich.edu diffTt = true; 4984172Ssaidi@eecs.umich.edu if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) != 4993815Ssaidi@eecs.umich.edu shared_data->htstate[i-1]) 5003748Sgblack@eecs.umich.edu diffHtstate = true; 5013748Sgblack@eecs.umich.edu } 5024172Ssaidi@eecs.umich.edu thread->setMiscRegNoEffect(MISCREG_TL, oldTl); 5033584Ssaidi@eecs.umich.edu 5044172Ssaidi@eecs.umich.edu if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA)) 5053748Sgblack@eecs.umich.edu diffTba = true; 5063748Sgblack@eecs.umich.edu //When the hpstate register is read by an instruction, 5073748Sgblack@eecs.umich.edu //legion has bit 11 set. When it's in storage, it doesn't. 5083748Sgblack@eecs.umich.edu //Since we don't directly support seperate interpretations 5093748Sgblack@eecs.umich.edu //of the registers like that, the bit is always set to 1 and 5103748Sgblack@eecs.umich.edu //we just don't compare it. It's not supposed to matter 5113748Sgblack@eecs.umich.edu //anyway. 5124172Ssaidi@eecs.umich.edu if((shared_data->hpstate | (1 << 11)) != thread->readMiscRegNoEffect(MISCREG_HPSTATE)) 5133748Sgblack@eecs.umich.edu diffHpstate = true; 5144172Ssaidi@eecs.umich.edu if(shared_data->htba != thread->readMiscRegNoEffect(MISCREG_HTBA)) 5153748Sgblack@eecs.umich.edu diffHtba = true; 5164172Ssaidi@eecs.umich.edu if(shared_data->pstate != thread->readMiscRegNoEffect(MISCREG_PSTATE)) 5173748Sgblack@eecs.umich.edu diffPstate = true; 5184172Ssaidi@eecs.umich.edu //if(shared_data->y != thread->readMiscRegNoEffect(MISCREG_Y)) 5193790Sgblack@eecs.umich.edu if(shared_data->y != 5203790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 1)) 5213748Sgblack@eecs.umich.edu diffY = true; 5224172Ssaidi@eecs.umich.edu if(shared_data->fsr != thread->readMiscRegNoEffect(MISCREG_FSR)) { 5234001Ssaidi@eecs.umich.edu diffFsr = true; 5244011Ssaidi@eecs.umich.edu if (mbits(shared_data->fsr, 63,10) == 5254172Ssaidi@eecs.umich.edu mbits(thread->readMiscRegNoEffect(MISCREG_FSR), 63,10)) { 5264172Ssaidi@eecs.umich.edu thread->setMiscRegNoEffect(MISCREG_FSR, shared_data->fsr); 5274011Ssaidi@eecs.umich.edu diffFsr = false; 5284011Ssaidi@eecs.umich.edu } 5294011Ssaidi@eecs.umich.edu } 5304172Ssaidi@eecs.umich.edu //if(shared_data->ccr != thread->readMiscRegNoEffect(MISCREG_CCR)) 5313790Sgblack@eecs.umich.edu if(shared_data->ccr != 5323790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 2)) 5333748Sgblack@eecs.umich.edu diffCcr = true; 5344172Ssaidi@eecs.umich.edu if(shared_data->gl != thread->readMiscRegNoEffect(MISCREG_GL)) 5353748Sgblack@eecs.umich.edu diffGl = true; 5364172Ssaidi@eecs.umich.edu if(shared_data->asi != thread->readMiscRegNoEffect(MISCREG_ASI)) 5373748Sgblack@eecs.umich.edu diffAsi = true; 5384172Ssaidi@eecs.umich.edu if(shared_data->pil != thread->readMiscRegNoEffect(MISCREG_PIL)) 5393748Sgblack@eecs.umich.edu diffPil = true; 5404172Ssaidi@eecs.umich.edu if(shared_data->cwp != thread->readMiscRegNoEffect(MISCREG_CWP)) 5413748Sgblack@eecs.umich.edu diffCwp = true; 5424172Ssaidi@eecs.umich.edu //if(shared_data->cansave != thread->readMiscRegNoEffect(MISCREG_CANSAVE)) 5433790Sgblack@eecs.umich.edu if(shared_data->cansave != 5443790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 3)) 5453748Sgblack@eecs.umich.edu diffCansave = true; 5463790Sgblack@eecs.umich.edu //if(shared_data->canrestore != 5474172Ssaidi@eecs.umich.edu // thread->readMiscRegNoEffect(MISCREG_CANRESTORE)) 5483748Sgblack@eecs.umich.edu if(shared_data->canrestore != 5493989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 4)) 5503748Sgblack@eecs.umich.edu diffCanrestore = true; 5514172Ssaidi@eecs.umich.edu //if(shared_data->otherwin != thread->readMiscRegNoEffect(MISCREG_OTHERWIN)) 5523790Sgblack@eecs.umich.edu if(shared_data->otherwin != 5533989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 6)) 5543748Sgblack@eecs.umich.edu diffOtherwin = true; 5554172Ssaidi@eecs.umich.edu //if(shared_data->cleanwin != thread->readMiscRegNoEffect(MISCREG_CLEANWIN)) 5563790Sgblack@eecs.umich.edu if(shared_data->cleanwin != 5573989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 5)) 5583748Sgblack@eecs.umich.edu diffCleanwin = true; 5593748Sgblack@eecs.umich.edu 5603880Ssaidi@eecs.umich.edu for (int i = 0; i < 64; i++) { 5613880Ssaidi@eecs.umich.edu if (shared_data->itb[i] != thread->getITBPtr()->TteRead(i)) 5623880Ssaidi@eecs.umich.edu diffTlb = true; 5633880Ssaidi@eecs.umich.edu if (shared_data->dtb[i] != thread->getDTBPtr()->TteRead(i)) 5643880Ssaidi@eecs.umich.edu diffTlb = true; 5653880Ssaidi@eecs.umich.edu } 5663880Ssaidi@eecs.umich.edu 5674008Ssaidi@eecs.umich.edu if (diffPC || diffCC || diffInst || diffIntRegs || 5683931Ssaidi@eecs.umich.edu diffFpRegs || diffTpc || diffTnpc || diffTstate || 5693931Ssaidi@eecs.umich.edu diffTt || diffHpstate || diffHtstate || diffHtba || 5704001Ssaidi@eecs.umich.edu diffPstate || diffY || diffCcr || diffTl || diffFsr || 5714001Ssaidi@eecs.umich.edu diffGl || diffAsi || diffPil || diffCwp || diffCansave || 5723931Ssaidi@eecs.umich.edu diffCanrestore || diffOtherwin || diffCleanwin || diffTlb) 5734008Ssaidi@eecs.umich.edu { 5743863Ssaidi@eecs.umich.edu 5753584Ssaidi@eecs.umich.edu outs << "Differences found between M5 and Legion:"; 5763584Ssaidi@eecs.umich.edu if (diffPC) 5773584Ssaidi@eecs.umich.edu outs << " [PC]"; 5783814Ssaidi@eecs.umich.edu if (diffCC) 5793814Ssaidi@eecs.umich.edu outs << " [CC]"; 5803584Ssaidi@eecs.umich.edu if (diffInst) 5813584Ssaidi@eecs.umich.edu outs << " [Instruction]"; 5823931Ssaidi@eecs.umich.edu if (diffIntRegs) 5833584Ssaidi@eecs.umich.edu outs << " [IntRegs]"; 5843931Ssaidi@eecs.umich.edu if (diffFpRegs) 5853931Ssaidi@eecs.umich.edu outs << " [FpRegs]"; 5863748Sgblack@eecs.umich.edu if (diffTpc) 5873748Sgblack@eecs.umich.edu outs << " [Tpc]"; 5883748Sgblack@eecs.umich.edu if (diffTnpc) 5893748Sgblack@eecs.umich.edu outs << " [Tnpc]"; 5903748Sgblack@eecs.umich.edu if (diffTstate) 5913748Sgblack@eecs.umich.edu outs << " [Tstate]"; 5923748Sgblack@eecs.umich.edu if (diffTt) 5933748Sgblack@eecs.umich.edu outs << " [Tt]"; 5943748Sgblack@eecs.umich.edu if (diffHpstate) 5953748Sgblack@eecs.umich.edu outs << " [Hpstate]"; 5963748Sgblack@eecs.umich.edu if (diffHtstate) 5973748Sgblack@eecs.umich.edu outs << " [Htstate]"; 5983748Sgblack@eecs.umich.edu if (diffHtba) 5993748Sgblack@eecs.umich.edu outs << " [Htba]"; 6003748Sgblack@eecs.umich.edu if (diffPstate) 6013748Sgblack@eecs.umich.edu outs << " [Pstate]"; 6023748Sgblack@eecs.umich.edu if (diffY) 6033748Sgblack@eecs.umich.edu outs << " [Y]"; 6044001Ssaidi@eecs.umich.edu if (diffFsr) 6054001Ssaidi@eecs.umich.edu outs << " [FSR]"; 6063748Sgblack@eecs.umich.edu if (diffCcr) 6073748Sgblack@eecs.umich.edu outs << " [Ccr]"; 6083748Sgblack@eecs.umich.edu if (diffTl) 6093748Sgblack@eecs.umich.edu outs << " [Tl]"; 6103748Sgblack@eecs.umich.edu if (diffGl) 6113748Sgblack@eecs.umich.edu outs << " [Gl]"; 6123748Sgblack@eecs.umich.edu if (diffAsi) 6133748Sgblack@eecs.umich.edu outs << " [Asi]"; 6143748Sgblack@eecs.umich.edu if (diffPil) 6153748Sgblack@eecs.umich.edu outs << " [Pil]"; 6163748Sgblack@eecs.umich.edu if (diffCwp) 6173748Sgblack@eecs.umich.edu outs << " [Cwp]"; 6183748Sgblack@eecs.umich.edu if (diffCansave) 6193748Sgblack@eecs.umich.edu outs << " [Cansave]"; 6203748Sgblack@eecs.umich.edu if (diffCanrestore) 6213748Sgblack@eecs.umich.edu outs << " [Canrestore]"; 6223748Sgblack@eecs.umich.edu if (diffOtherwin) 6233748Sgblack@eecs.umich.edu outs << " [Otherwin]"; 6243748Sgblack@eecs.umich.edu if (diffCleanwin) 6253748Sgblack@eecs.umich.edu outs << " [Cleanwin]"; 6263880Ssaidi@eecs.umich.edu if (diffTlb) 6273880Ssaidi@eecs.umich.edu outs << " [Tlb]"; 6283603Ssaidi@eecs.umich.edu outs << endl << endl; 6293584Ssaidi@eecs.umich.edu 6303603Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 6313584Ssaidi@eecs.umich.edu << "M5 PC: " << "0x"<< setw(16) << setfill('0') 6323603Ssaidi@eecs.umich.edu << hex << m5Pc << endl; 6333584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 6343584Ssaidi@eecs.umich.edu << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex 6353603Ssaidi@eecs.umich.edu << lgnPc << endl << endl; 6363584Ssaidi@eecs.umich.edu 6373814Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 6383814Ssaidi@eecs.umich.edu << "M5 CC: " << "0x"<< setw(16) << setfill('0') 6393814Ssaidi@eecs.umich.edu << hex << thread->getCpuPtr()->instCount() << endl; 6403814Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 6413814Ssaidi@eecs.umich.edu << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex 6423814Ssaidi@eecs.umich.edu << shared_data->cycle_count << endl << endl; 6433814Ssaidi@eecs.umich.edu 6443584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 6453584Ssaidi@eecs.umich.edu << "M5 Inst: " << "0x"<< setw(8) 6463584Ssaidi@eecs.umich.edu << setfill('0') << hex << staticInst->machInst 6473603Ssaidi@eecs.umich.edu << staticInst->disassemble(m5Pc, debugSymbolTable) 6483584Ssaidi@eecs.umich.edu << endl; 6493584Ssaidi@eecs.umich.edu 6503748Sgblack@eecs.umich.edu StaticInstPtr legionInst = 6513748Sgblack@eecs.umich.edu StaticInst::decode(makeExtMI(shared_data->instruction, 6523748Sgblack@eecs.umich.edu thread)); 6533584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 6543584Ssaidi@eecs.umich.edu << " Legion Inst: " 6553584Ssaidi@eecs.umich.edu << "0x" << setw(8) << setfill('0') << hex 6563584Ssaidi@eecs.umich.edu << shared_data->instruction 6573603Ssaidi@eecs.umich.edu << legionInst->disassemble(lgnPc, debugSymbolTable) 6583748Sgblack@eecs.umich.edu << endl << endl; 6593584Ssaidi@eecs.umich.edu 6603748Sgblack@eecs.umich.edu printSectionHeader(outs, "General State"); 6613748Sgblack@eecs.umich.edu printColumnLabels(outs); 6623748Sgblack@eecs.umich.edu printRegPair(outs, "HPstate", 6634172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_HPSTATE), 6643748Sgblack@eecs.umich.edu shared_data->hpstate | (1 << 11)); 6653748Sgblack@eecs.umich.edu printRegPair(outs, "Htba", 6664172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_HTBA), 6673748Sgblack@eecs.umich.edu shared_data->htba); 6683748Sgblack@eecs.umich.edu printRegPair(outs, "Pstate", 6694172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_PSTATE), 6703748Sgblack@eecs.umich.edu shared_data->pstate); 6713748Sgblack@eecs.umich.edu printRegPair(outs, "Y", 6724172Ssaidi@eecs.umich.edu //thread->readMiscRegNoEffect(MISCREG_Y), 6733989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 1), 6743748Sgblack@eecs.umich.edu shared_data->y); 6754001Ssaidi@eecs.umich.edu printRegPair(outs, "FSR", 6764172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_FSR), 6774001Ssaidi@eecs.umich.edu shared_data->fsr); 6783748Sgblack@eecs.umich.edu printRegPair(outs, "Ccr", 6794172Ssaidi@eecs.umich.edu //thread->readMiscRegNoEffect(MISCREG_CCR), 6803989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 2), 6813748Sgblack@eecs.umich.edu shared_data->ccr); 6823748Sgblack@eecs.umich.edu printRegPair(outs, "Tl", 6834172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_TL), 6843748Sgblack@eecs.umich.edu shared_data->tl); 6853748Sgblack@eecs.umich.edu printRegPair(outs, "Gl", 6864172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_GL), 6873748Sgblack@eecs.umich.edu shared_data->gl); 6883748Sgblack@eecs.umich.edu printRegPair(outs, "Asi", 6894172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_ASI), 6903748Sgblack@eecs.umich.edu shared_data->asi); 6913748Sgblack@eecs.umich.edu printRegPair(outs, "Pil", 6924172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_PIL), 6933748Sgblack@eecs.umich.edu shared_data->pil); 6943748Sgblack@eecs.umich.edu printRegPair(outs, "Cwp", 6954172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_CWP), 6963748Sgblack@eecs.umich.edu shared_data->cwp); 6973748Sgblack@eecs.umich.edu printRegPair(outs, "Cansave", 6984172Ssaidi@eecs.umich.edu //thread->readMiscRegNoEffect(MISCREG_CANSAVE), 6993790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 3), 7003748Sgblack@eecs.umich.edu shared_data->cansave); 7013748Sgblack@eecs.umich.edu printRegPair(outs, "Canrestore", 7024172Ssaidi@eecs.umich.edu //thread->readMiscRegNoEffect(MISCREG_CANRESTORE), 7033790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 4), 7043748Sgblack@eecs.umich.edu shared_data->canrestore); 7053748Sgblack@eecs.umich.edu printRegPair(outs, "Otherwin", 7064172Ssaidi@eecs.umich.edu //thread->readMiscRegNoEffect(MISCREG_OTHERWIN), 7073989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 6), 7083748Sgblack@eecs.umich.edu shared_data->otherwin); 7093748Sgblack@eecs.umich.edu printRegPair(outs, "Cleanwin", 7104172Ssaidi@eecs.umich.edu //thread->readMiscRegNoEffect(MISCREG_CLEANWIN), 7113989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 5), 7123748Sgblack@eecs.umich.edu shared_data->cleanwin); 7133748Sgblack@eecs.umich.edu outs << endl; 7143748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 7153748Sgblack@eecs.umich.edu printLevelHeader(outs, i); 7163748Sgblack@eecs.umich.edu printColumnLabels(outs); 7174172Ssaidi@eecs.umich.edu thread->setMiscRegNoEffect(MISCREG_TL, i); 7183748Sgblack@eecs.umich.edu printRegPair(outs, "Tpc", 7194172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_TPC), 7203815Ssaidi@eecs.umich.edu shared_data->tpc[i-1]); 7213748Sgblack@eecs.umich.edu printRegPair(outs, "Tnpc", 7224172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_TNPC), 7233815Ssaidi@eecs.umich.edu shared_data->tnpc[i-1]); 7243748Sgblack@eecs.umich.edu printRegPair(outs, "Tstate", 7254172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_TSTATE), 7263815Ssaidi@eecs.umich.edu shared_data->tstate[i-1]); 7273748Sgblack@eecs.umich.edu printRegPair(outs, "Tt", 7284172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_TT), 7293815Ssaidi@eecs.umich.edu shared_data->tt[i-1]); 7303748Sgblack@eecs.umich.edu printRegPair(outs, "Htstate", 7314172Ssaidi@eecs.umich.edu thread->readMiscRegNoEffect(MISCREG_HTSTATE), 7323815Ssaidi@eecs.umich.edu shared_data->htstate[i-1]); 7333748Sgblack@eecs.umich.edu } 7344172Ssaidi@eecs.umich.edu thread->setMiscRegNoEffect(MISCREG_TL, oldTl); 7353584Ssaidi@eecs.umich.edu outs << endl; 7363584Ssaidi@eecs.umich.edu 7373748Sgblack@eecs.umich.edu printSectionHeader(outs, "General Purpose Registers"); 7383584Ssaidi@eecs.umich.edu static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; 7393931Ssaidi@eecs.umich.edu for(int y = 0; y < 4; y++) { 7403931Ssaidi@eecs.umich.edu for(int x = 0; x < 8; x++) { 7413748Sgblack@eecs.umich.edu char label[8]; 7423748Sgblack@eecs.umich.edu sprintf(label, "%s%d", regtypes[y], x); 7433748Sgblack@eecs.umich.edu printRegPair(outs, label, 7443748Sgblack@eecs.umich.edu thread->readIntReg(y*8+x), 7453748Sgblack@eecs.umich.edu shared_data->intregs[y*8+x]); 7463931Ssaidi@eecs.umich.edu } 7473931Ssaidi@eecs.umich.edu } 7483931Ssaidi@eecs.umich.edu if (diffFpRegs) { 7493931Ssaidi@eecs.umich.edu for (int x = 0; x < 32; x++) { 7503931Ssaidi@eecs.umich.edu char label[8]; 7513931Ssaidi@eecs.umich.edu sprintf(label, "%%f%d", x); 7523931Ssaidi@eecs.umich.edu printRegPair(outs, label, 7534008Ssaidi@eecs.umich.edu thread->readFloatRegBits(x*2,FloatRegFile::DoubleWidth), 7543931Ssaidi@eecs.umich.edu shared_data->fpregs[x]); 7553584Ssaidi@eecs.umich.edu } 7563584Ssaidi@eecs.umich.edu } 7573903Ssaidi@eecs.umich.edu if (diffTlb) { 7583903Ssaidi@eecs.umich.edu printColumnLabels(outs); 7593903Ssaidi@eecs.umich.edu char label[8]; 7603903Ssaidi@eecs.umich.edu for (int x = 0; x < 64; x++) { 7613903Ssaidi@eecs.umich.edu if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) || 7623903Ssaidi@eecs.umich.edu thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { 7633903Ssaidi@eecs.umich.edu sprintf(label, "I-TLB:%02d", x); 7643903Ssaidi@eecs.umich.edu printRegPair(outs, label, thread->getITBPtr()->TteRead(x), 7653903Ssaidi@eecs.umich.edu shared_data->itb[x]); 7663903Ssaidi@eecs.umich.edu } 7673880Ssaidi@eecs.umich.edu } 7683903Ssaidi@eecs.umich.edu for (int x = 0; x < 64; x++) { 7693903Ssaidi@eecs.umich.edu if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) || 7703903Ssaidi@eecs.umich.edu thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { 7713903Ssaidi@eecs.umich.edu sprintf(label, "D-TLB:%02d", x); 7723903Ssaidi@eecs.umich.edu printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), 7733903Ssaidi@eecs.umich.edu shared_data->dtb[x]); 7743903Ssaidi@eecs.umich.edu } 7753903Ssaidi@eecs.umich.edu } 7763903Ssaidi@eecs.umich.edu thread->getITBPtr()->dumpAll(); 7773903Ssaidi@eecs.umich.edu thread->getDTBPtr()->dumpAll(); 7783880Ssaidi@eecs.umich.edu } 7793826Ssaidi@eecs.umich.edu 7803825Ssaidi@eecs.umich.edu diffcount++; 7814011Ssaidi@eecs.umich.edu if (diffcount > 3) 7823825Ssaidi@eecs.umich.edu fatal("Differences found between Legion and M5\n"); 7833892Ssaidi@eecs.umich.edu } else 7843892Ssaidi@eecs.umich.edu diffcount = 0; 7853584Ssaidi@eecs.umich.edu 7863584Ssaidi@eecs.umich.edu compared = true; 7873584Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 7883506Ssaidi@eecs.umich.edu } 7893584Ssaidi@eecs.umich.edu } // while 7903584Ssaidi@eecs.umich.edu } // if not microop 7913506Ssaidi@eecs.umich.edu } 7923584Ssaidi@eecs.umich.edu#endif 7932SN/A} 7942SN/A 7954054Sbinkertn@umich.edu/* namespace Trace */ } 796