exetrace.cc revision 4054
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 363506Ssaidi@eecs.umich.edu#include <sys/ipc.h> 373506Ssaidi@eecs.umich.edu#include <sys/shm.h> 382SN/A 392973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 403584Ssaidi@eecs.umich.edu#include "arch/utility.hh" 4156SN/A#include "base/loader/symtab.hh" 423614Sgblack@eecs.umich.edu#include "config/full_system.hh" 431717SN/A#include "cpu/base.hh" 442518SN/A#include "cpu/exetrace.hh" 4556SN/A#include "cpu/static_inst.hh" 462518SN/A#include "sim/param.hh" 472518SN/A#include "sim/system.hh" 482SN/A 493614Sgblack@eecs.umich.edu#if FULL_SYSTEM 503614Sgblack@eecs.umich.edu#include "arch/tlb.hh" 513614Sgblack@eecs.umich.edu#endif 523614Sgblack@eecs.umich.edu 533065Sgblack@eecs.umich.edu//XXX This is temporary 543065Sgblack@eecs.umich.edu#include "arch/isa_specific.hh" 553506Ssaidi@eecs.umich.edu#include "cpu/m5legion_interface.h" 563065Sgblack@eecs.umich.edu 572SN/Ausing namespace std; 582973Sgblack@eecs.umich.eduusing namespace TheISA; 592SN/A 603840Shsul@eecs.umich.edu#if THE_ISA == SPARC_ISA && FULL_SYSTEM 613825Ssaidi@eecs.umich.edustatic int diffcount = 0; 623903Ssaidi@eecs.umich.edustatic bool wasMicro = false; 633840Shsul@eecs.umich.edu#endif 643825Ssaidi@eecs.umich.edu 653506Ssaidi@eecs.umich.edunamespace Trace { 663506Ssaidi@eecs.umich.eduSharedData *shared_data = NULL; 674054Sbinkertn@umich.edu 684054Sbinkertn@umich.eduvoid 694054Sbinkertn@umich.edusetupSharedData() 704054Sbinkertn@umich.edu{ 714054Sbinkertn@umich.edu int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777); 724054Sbinkertn@umich.edu if (shmfd < 0) 734054Sbinkertn@umich.edu fatal("Couldn't get shared memory fd. Is Legion running?"); 744054Sbinkertn@umich.edu 754054Sbinkertn@umich.edu shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 764054Sbinkertn@umich.edu if (shared_data == (SharedData*)-1) 774054Sbinkertn@umich.edu fatal("Couldn't allocate shared memory"); 784054Sbinkertn@umich.edu 794054Sbinkertn@umich.edu if (shared_data->flags != OWN_M5) 804054Sbinkertn@umich.edu fatal("Shared memory has invalid owner"); 814054Sbinkertn@umich.edu 824054Sbinkertn@umich.edu if (shared_data->version != VERSION) 834054Sbinkertn@umich.edu fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 844054Sbinkertn@umich.edu shared_data->version); 854054Sbinkertn@umich.edu 864054Sbinkertn@umich.edu // step legion forward one cycle so we can get register values 874054Sbinkertn@umich.edu shared_data->flags = OWN_LEGION; 883506Ssaidi@eecs.umich.edu} 893506Ssaidi@eecs.umich.edu 902SN/A//////////////////////////////////////////////////////////////////////// 912SN/A// 922SN/A// Methods for the InstRecord object 932SN/A// 942SN/A 953748Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 963748Sgblack@eecs.umich.edu 973748Sgblack@eecs.umich.eduinline char * genCenteredLabel(int length, char * buffer, char * label) 983748Sgblack@eecs.umich.edu{ 993748Sgblack@eecs.umich.edu int labelLength = strlen(label); 1003748Sgblack@eecs.umich.edu assert(labelLength <= length); 1013748Sgblack@eecs.umich.edu int leftPad = (length - labelLength) / 2; 1023748Sgblack@eecs.umich.edu int rightPad = length - leftPad - labelLength; 1033748Sgblack@eecs.umich.edu char format[64]; 1043748Sgblack@eecs.umich.edu sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad); 1053748Sgblack@eecs.umich.edu sprintf(buffer, format, "", label, ""); 1063748Sgblack@eecs.umich.edu return buffer; 1073748Sgblack@eecs.umich.edu} 1083748Sgblack@eecs.umich.edu 1093748Sgblack@eecs.umich.eduinline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b) 1103748Sgblack@eecs.umich.edu{ 1113748Sgblack@eecs.umich.edu ccprintf(os, " %16s | %#018x %s %#-018x \n", 1123748Sgblack@eecs.umich.edu title, a, (a == b) ? "|" : "X", b); 1133748Sgblack@eecs.umich.edu} 1143748Sgblack@eecs.umich.edu 1153748Sgblack@eecs.umich.eduinline void printColumnLabels(ostream & os) 1163748Sgblack@eecs.umich.edu{ 1173748Sgblack@eecs.umich.edu static char * regLabel = genCenteredLabel(16, new char[17], "Register"); 1183748Sgblack@eecs.umich.edu static char * m5Label = genCenteredLabel(18, new char[18], "M5"); 1193748Sgblack@eecs.umich.edu static char * legionLabel = genCenteredLabel(18, new char[18], "Legion"); 1203748Sgblack@eecs.umich.edu ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel); 1213748Sgblack@eecs.umich.edu ccprintf(os, "--------------------+-----------------------+-----------------------\n"); 1223748Sgblack@eecs.umich.edu} 1233748Sgblack@eecs.umich.edu 1243748Sgblack@eecs.umich.eduinline void printSectionHeader(ostream & os, char * name) 1253748Sgblack@eecs.umich.edu{ 1263748Sgblack@eecs.umich.edu char sectionString[70]; 1273748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, name); 1283748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1293748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1303748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1313748Sgblack@eecs.umich.edu} 1323748Sgblack@eecs.umich.edu 1333748Sgblack@eecs.umich.eduinline void printLevelHeader(ostream & os, int level) 1343748Sgblack@eecs.umich.edu{ 1353748Sgblack@eecs.umich.edu char sectionString[70]; 1363748Sgblack@eecs.umich.edu char levelName[70]; 1373748Sgblack@eecs.umich.edu sprintf(levelName, "Trap stack level %d", level); 1383748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, levelName); 1393748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1403748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1413748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1423748Sgblack@eecs.umich.edu} 1433748Sgblack@eecs.umich.edu 1443748Sgblack@eecs.umich.edu#endif 1452SN/A 1462SN/Avoid 1474046Sbinkertn@umich.eduTrace::InstRecord::dump() 1482SN/A{ 1494046Sbinkertn@umich.edu ostream &outs = Trace::output(); 1504046Sbinkertn@umich.edu 1513903Ssaidi@eecs.umich.edu DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst); 1524054Sbinkertn@umich.edu if (IsOn(ExecRegDelta)) 1532973Sgblack@eecs.umich.edu { 1543065Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 1553380Sgblack@eecs.umich.edu //Don't print what happens for each micro-op, just print out 1563380Sgblack@eecs.umich.edu //once at the last op, and for regular instructions. 1573380Sgblack@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 1583380Sgblack@eecs.umich.edu { 1593380Sgblack@eecs.umich.edu static uint64_t regs[32] = { 1603380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1613380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1623380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1633380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 1643380Sgblack@eecs.umich.edu static uint64_t ccr = 0; 1653380Sgblack@eecs.umich.edu static uint64_t y = 0; 1663380Sgblack@eecs.umich.edu static uint64_t floats[32]; 1673380Sgblack@eecs.umich.edu uint64_t newVal; 1683380Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 1693065Sgblack@eecs.umich.edu 1703588Sgblack@eecs.umich.edu outs << hex; 1713588Sgblack@eecs.umich.edu outs << "PC = " << thread->readNextPC(); 1723588Sgblack@eecs.umich.edu outs << " NPC = " << thread->readNextNPC(); 1733790Sgblack@eecs.umich.edu newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2); 1743790Sgblack@eecs.umich.edu //newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); 1753380Sgblack@eecs.umich.edu if(newVal != ccr) 1763059Sgblack@eecs.umich.edu { 1773588Sgblack@eecs.umich.edu outs << " CCR = " << newVal; 1783380Sgblack@eecs.umich.edu ccr = newVal; 1793380Sgblack@eecs.umich.edu } 1803790Sgblack@eecs.umich.edu newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 1); 1813790Sgblack@eecs.umich.edu //newVal = thread->readMiscReg(SparcISA::MISCREG_Y); 1823380Sgblack@eecs.umich.edu if(newVal != y) 1833380Sgblack@eecs.umich.edu { 1843588Sgblack@eecs.umich.edu outs << " Y = " << newVal; 1853380Sgblack@eecs.umich.edu y = newVal; 1863380Sgblack@eecs.umich.edu } 1873380Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 1883380Sgblack@eecs.umich.edu { 1893380Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 1903059Sgblack@eecs.umich.edu { 1913380Sgblack@eecs.umich.edu int index = x + 8 * y; 1923380Sgblack@eecs.umich.edu newVal = thread->readIntReg(index); 1933380Sgblack@eecs.umich.edu if(regs[index] != newVal) 1943380Sgblack@eecs.umich.edu { 1953588Sgblack@eecs.umich.edu outs << " " << prefixes[y] << dec << x << " = " << hex << newVal; 1963380Sgblack@eecs.umich.edu regs[index] = newVal; 1973380Sgblack@eecs.umich.edu } 1983059Sgblack@eecs.umich.edu } 1993059Sgblack@eecs.umich.edu } 2003380Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 2013380Sgblack@eecs.umich.edu { 2023380Sgblack@eecs.umich.edu newVal = thread->readFloatRegBits(2 * y, 64); 2033380Sgblack@eecs.umich.edu if(floats[y] != newVal) 2043380Sgblack@eecs.umich.edu { 2053588Sgblack@eecs.umich.edu outs << " F" << dec << (2 * y) << " = " << hex << newVal; 2063380Sgblack@eecs.umich.edu floats[y] = newVal; 2073380Sgblack@eecs.umich.edu } 2083380Sgblack@eecs.umich.edu } 2093588Sgblack@eecs.umich.edu outs << dec << endl; 2103059Sgblack@eecs.umich.edu } 2113065Sgblack@eecs.umich.edu#endif 2122973Sgblack@eecs.umich.edu } 2134054Sbinkertn@umich.edu else if (IsOn(ExecIntel)) { 2144054Sbinkertn@umich.edu ccprintf(outs, "%7d ) ", when); 2154054Sbinkertn@umich.edu outs << "0x" << hex << PC << ":\t"; 2164054Sbinkertn@umich.edu if (staticInst->isLoad()) { 2174054Sbinkertn@umich.edu ccprintf(outs, "<RD %#x>", addr); 2184054Sbinkertn@umich.edu } else if (staticInst->isStore()) { 2194054Sbinkertn@umich.edu ccprintf(outs, "<WR %#x>", addr); 2201904SN/A } 2214054Sbinkertn@umich.edu outs << endl; 2221904SN/A } else { 2234054Sbinkertn@umich.edu if (IsOn(ExecTicks)) 2244046Sbinkertn@umich.edu ccprintf(outs, "%7d: ", when); 225452SN/A 2263064Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 2272SN/A 2284054Sbinkertn@umich.edu if (IsOn(ExecSpeculative)) 2291904SN/A outs << (misspeculating ? "-" : "+") << " "; 2302SN/A 2314054Sbinkertn@umich.edu if (IsOn(ExecThread)) 2323064Sgblack@eecs.umich.edu outs << "T" << thread->getThreadNum() << " : "; 2332SN/A 2342SN/A 2351904SN/A std::string sym_str; 2361904SN/A Addr sym_addr; 2371904SN/A if (debugSymbolTable 2382299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 2394054Sbinkertn@umich.edu && IsOn(ExecSymbol)) { 2401904SN/A if (PC != sym_addr) 2411904SN/A sym_str += csprintf("+%d", PC - sym_addr); 2421904SN/A outs << "@" << sym_str << " : "; 2431904SN/A } 2441904SN/A else { 2451904SN/A outs << "0x" << hex << PC << " : "; 2461904SN/A } 247452SN/A 2481904SN/A // 2491904SN/A // Print decoded instruction 2501904SN/A // 2512SN/A 2522SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 2531904SN/A // There's a bug in gcc 2.x library that prevents setw() 2541904SN/A // from working properly on strings 2551904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 2561904SN/A while (mc.length() < 26) 2571904SN/A mc += " "; 2581904SN/A outs << mc; 2592SN/A#else 2601904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 2612SN/A#endif 2622SN/A 2631904SN/A outs << " : "; 2642SN/A 2654054Sbinkertn@umich.edu if (IsOn(ExecOpClass)) { 2661904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 2671904SN/A } 2681904SN/A 2694054Sbinkertn@umich.edu if (IsOn(ExecResult) && data_status != DataInvalid) { 2701904SN/A outs << " D="; 2711904SN/A#if 0 2721904SN/A if (data_status == DataDouble) 2731904SN/A ccprintf(outs, "%f", data.as_double); 2741904SN/A else 2751904SN/A ccprintf(outs, "%#018x", data.as_int); 2761904SN/A#else 2771904SN/A ccprintf(outs, "%#018x", data.as_int); 2781904SN/A#endif 2791904SN/A } 2801904SN/A 2814054Sbinkertn@umich.edu if (IsOn(ExecEffAddr) && addr_valid) 2821904SN/A outs << " A=0x" << hex << addr; 2831904SN/A 2844054Sbinkertn@umich.edu if (IsOn(ExecIntRegs) && regs_valid) { 2852525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 2861904SN/A for (int j = i + 1; i <= j; i++) 2872525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 2882525SN/A iregs->regs.readReg(i), 2892525SN/A ((i == j) ? "\n" : " ")); 2901904SN/A outs << "\n"; 2911904SN/A } 2921904SN/A 2934054Sbinkertn@umich.edu if (IsOn(ExecFetchSeq) && fetch_seq_valid) 2941904SN/A outs << " FetchSeq=" << dec << fetch_seq; 2951904SN/A 2964054Sbinkertn@umich.edu if (IsOn(ExecCPSeq) && cp_seq_valid) 2971904SN/A outs << " CPSeq=" << dec << cp_seq; 2981967SN/A 2991967SN/A // 3001967SN/A // End of line... 3011967SN/A // 3021967SN/A outs << endl; 3032SN/A } 3043817Ssaidi@eecs.umich.edu#if THE_ISA == SPARC_ISA && FULL_SYSTEM 3053506Ssaidi@eecs.umich.edu // Compare 3064054Sbinkertn@umich.edu if (IsOn(ExecLegion)) 3073506Ssaidi@eecs.umich.edu { 3083506Ssaidi@eecs.umich.edu bool compared = false; 3093506Ssaidi@eecs.umich.edu bool diffPC = false; 3103814Ssaidi@eecs.umich.edu bool diffCC = false; 3113506Ssaidi@eecs.umich.edu bool diffInst = false; 3123931Ssaidi@eecs.umich.edu bool diffIntRegs = false; 3133931Ssaidi@eecs.umich.edu bool diffFpRegs = false; 3143748Sgblack@eecs.umich.edu bool diffTpc = false; 3153748Sgblack@eecs.umich.edu bool diffTnpc = false; 3163748Sgblack@eecs.umich.edu bool diffTstate = false; 3173748Sgblack@eecs.umich.edu bool diffTt = false; 3183748Sgblack@eecs.umich.edu bool diffTba = false; 3193748Sgblack@eecs.umich.edu bool diffHpstate = false; 3203748Sgblack@eecs.umich.edu bool diffHtstate = false; 3213748Sgblack@eecs.umich.edu bool diffHtba = false; 3223748Sgblack@eecs.umich.edu bool diffPstate = false; 3233748Sgblack@eecs.umich.edu bool diffY = false; 3244001Ssaidi@eecs.umich.edu bool diffFsr = false; 3253748Sgblack@eecs.umich.edu bool diffCcr = false; 3263748Sgblack@eecs.umich.edu bool diffTl = false; 3273748Sgblack@eecs.umich.edu bool diffGl = false; 3283748Sgblack@eecs.umich.edu bool diffAsi = false; 3293748Sgblack@eecs.umich.edu bool diffPil = false; 3303748Sgblack@eecs.umich.edu bool diffCwp = false; 3313748Sgblack@eecs.umich.edu bool diffCansave = false; 3323748Sgblack@eecs.umich.edu bool diffCanrestore = false; 3333748Sgblack@eecs.umich.edu bool diffOtherwin = false; 3343748Sgblack@eecs.umich.edu bool diffCleanwin = false; 3353880Ssaidi@eecs.umich.edu bool diffTlb = false; 3363603Ssaidi@eecs.umich.edu Addr m5Pc, lgnPc; 3373603Ssaidi@eecs.umich.edu 3384054Sbinkertn@umich.edu if (!shared_data) 3394054Sbinkertn@umich.edu setupSharedData(); 3404054Sbinkertn@umich.edu 3413903Ssaidi@eecs.umich.edu // We took a trap on a micro-op... 3423903Ssaidi@eecs.umich.edu if (wasMicro && !staticInst->isMicroOp()) 3433903Ssaidi@eecs.umich.edu { 3444046Sbinkertn@umich.edu // let's skip comparing this tick 3453903Ssaidi@eecs.umich.edu while (!compared) 3463903Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 3473903Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 3483903Ssaidi@eecs.umich.edu compared = true; 3493903Ssaidi@eecs.umich.edu } 3503903Ssaidi@eecs.umich.edu compared = false; 3513903Ssaidi@eecs.umich.edu wasMicro = false; 3523903Ssaidi@eecs.umich.edu } 3533903Ssaidi@eecs.umich.edu 3543903Ssaidi@eecs.umich.edu if (staticInst->isLastMicroOp()) 3553903Ssaidi@eecs.umich.edu wasMicro = false; 3563903Ssaidi@eecs.umich.edu else if (staticInst->isMicroOp()) 3573903Ssaidi@eecs.umich.edu wasMicro = true; 3583903Ssaidi@eecs.umich.edu 3593506Ssaidi@eecs.umich.edu 3603584Ssaidi@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { 3613584Ssaidi@eecs.umich.edu while (!compared) { 3623584Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 3633748Sgblack@eecs.umich.edu m5Pc = PC & TheISA::PAddrImplMask; 3643928Ssaidi@eecs.umich.edu if (bits(shared_data->pstate,3,3)) { 3653928Ssaidi@eecs.umich.edu m5Pc &= mask(32); 3663928Ssaidi@eecs.umich.edu } 3673748Sgblack@eecs.umich.edu lgnPc = shared_data->pc & TheISA::PAddrImplMask; 3683603Ssaidi@eecs.umich.edu if (lgnPc != m5Pc) 3693584Ssaidi@eecs.umich.edu diffPC = true; 3703814Ssaidi@eecs.umich.edu 3713814Ssaidi@eecs.umich.edu if (shared_data->cycle_count != 3723814Ssaidi@eecs.umich.edu thread->getCpuPtr()->instCount()) 3733814Ssaidi@eecs.umich.edu diffCC = true; 3743814Ssaidi@eecs.umich.edu 3753743Sgblack@eecs.umich.edu if (shared_data->instruction != 3763743Sgblack@eecs.umich.edu (SparcISA::MachInst)staticInst->machInst) { 3773584Ssaidi@eecs.umich.edu diffInst = true; 3783743Sgblack@eecs.umich.edu } 3793989Ssaidi@eecs.umich.edu // assume we have %g0 working correctly 3803989Ssaidi@eecs.umich.edu for (int i = 1; i < TheISA::NumIntArchRegs; i++) { 3813603Ssaidi@eecs.umich.edu if (thread->readIntReg(i) != shared_data->intregs[i]) { 3823931Ssaidi@eecs.umich.edu diffIntRegs = true; 3833603Ssaidi@eecs.umich.edu } 3843584Ssaidi@eecs.umich.edu } 3853931Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumFloatRegs/2; i++) { 3863945Ssaidi@eecs.umich.edu if (thread->readFloatRegBits(i*2,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) { 3873931Ssaidi@eecs.umich.edu diffFpRegs = true; 3883931Ssaidi@eecs.umich.edu } 3893931Ssaidi@eecs.umich.edu } 3903931Ssaidi@eecs.umich.edu uint64_t oldTl = thread->readMiscReg(MISCREG_TL); 3913748Sgblack@eecs.umich.edu if (oldTl != shared_data->tl) 3923748Sgblack@eecs.umich.edu diffTl = true; 3933748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 3943748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, i); 3953748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TPC) != 3963815Ssaidi@eecs.umich.edu shared_data->tpc[i-1]) 3973748Sgblack@eecs.umich.edu diffTpc = true; 3983748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TNPC) != 3993815Ssaidi@eecs.umich.edu shared_data->tnpc[i-1]) 4003748Sgblack@eecs.umich.edu diffTnpc = true; 4013748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TSTATE) != 4023815Ssaidi@eecs.umich.edu shared_data->tstate[i-1]) 4033748Sgblack@eecs.umich.edu diffTstate = true; 4043748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TT) != 4053815Ssaidi@eecs.umich.edu shared_data->tt[i-1]) 4063748Sgblack@eecs.umich.edu diffTt = true; 4073748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_HTSTATE) != 4083815Ssaidi@eecs.umich.edu shared_data->htstate[i-1]) 4093748Sgblack@eecs.umich.edu diffHtstate = true; 4103748Sgblack@eecs.umich.edu } 4113748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, oldTl); 4123584Ssaidi@eecs.umich.edu 4133748Sgblack@eecs.umich.edu if(shared_data->tba != thread->readMiscReg(MISCREG_TBA)) 4143748Sgblack@eecs.umich.edu diffTba = true; 4153748Sgblack@eecs.umich.edu //When the hpstate register is read by an instruction, 4163748Sgblack@eecs.umich.edu //legion has bit 11 set. When it's in storage, it doesn't. 4173748Sgblack@eecs.umich.edu //Since we don't directly support seperate interpretations 4183748Sgblack@eecs.umich.edu //of the registers like that, the bit is always set to 1 and 4193748Sgblack@eecs.umich.edu //we just don't compare it. It's not supposed to matter 4203748Sgblack@eecs.umich.edu //anyway. 4213748Sgblack@eecs.umich.edu if((shared_data->hpstate | (1 << 11)) != thread->readMiscReg(MISCREG_HPSTATE)) 4223748Sgblack@eecs.umich.edu diffHpstate = true; 4233748Sgblack@eecs.umich.edu if(shared_data->htba != thread->readMiscReg(MISCREG_HTBA)) 4243748Sgblack@eecs.umich.edu diffHtba = true; 4253748Sgblack@eecs.umich.edu if(shared_data->pstate != thread->readMiscReg(MISCREG_PSTATE)) 4263748Sgblack@eecs.umich.edu diffPstate = true; 4273790Sgblack@eecs.umich.edu //if(shared_data->y != thread->readMiscReg(MISCREG_Y)) 4283790Sgblack@eecs.umich.edu if(shared_data->y != 4293790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 1)) 4303748Sgblack@eecs.umich.edu diffY = true; 4314011Ssaidi@eecs.umich.edu if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR)) { 4324001Ssaidi@eecs.umich.edu diffFsr = true; 4334011Ssaidi@eecs.umich.edu if (mbits(shared_data->fsr, 63,10) == 4344011Ssaidi@eecs.umich.edu mbits(thread->readMiscReg(MISCREG_FSR), 63,10)) { 4354011Ssaidi@eecs.umich.edu thread->setMiscReg(MISCREG_FSR, shared_data->fsr); 4364011Ssaidi@eecs.umich.edu diffFsr = false; 4374011Ssaidi@eecs.umich.edu } 4384011Ssaidi@eecs.umich.edu } 4393790Sgblack@eecs.umich.edu //if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR)) 4403790Sgblack@eecs.umich.edu if(shared_data->ccr != 4413790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 2)) 4423748Sgblack@eecs.umich.edu diffCcr = true; 4433748Sgblack@eecs.umich.edu if(shared_data->gl != thread->readMiscReg(MISCREG_GL)) 4443748Sgblack@eecs.umich.edu diffGl = true; 4453748Sgblack@eecs.umich.edu if(shared_data->asi != thread->readMiscReg(MISCREG_ASI)) 4463748Sgblack@eecs.umich.edu diffAsi = true; 4473748Sgblack@eecs.umich.edu if(shared_data->pil != thread->readMiscReg(MISCREG_PIL)) 4483748Sgblack@eecs.umich.edu diffPil = true; 4493748Sgblack@eecs.umich.edu if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP)) 4503748Sgblack@eecs.umich.edu diffCwp = true; 4513790Sgblack@eecs.umich.edu //if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE)) 4523790Sgblack@eecs.umich.edu if(shared_data->cansave != 4533790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 3)) 4543748Sgblack@eecs.umich.edu diffCansave = true; 4553790Sgblack@eecs.umich.edu //if(shared_data->canrestore != 4563790Sgblack@eecs.umich.edu // thread->readMiscReg(MISCREG_CANRESTORE)) 4573748Sgblack@eecs.umich.edu if(shared_data->canrestore != 4583989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 4)) 4593748Sgblack@eecs.umich.edu diffCanrestore = true; 4603790Sgblack@eecs.umich.edu //if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN)) 4613790Sgblack@eecs.umich.edu if(shared_data->otherwin != 4623989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 6)) 4633748Sgblack@eecs.umich.edu diffOtherwin = true; 4643790Sgblack@eecs.umich.edu //if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN)) 4653790Sgblack@eecs.umich.edu if(shared_data->cleanwin != 4663989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 5)) 4673748Sgblack@eecs.umich.edu diffCleanwin = true; 4683748Sgblack@eecs.umich.edu 4693880Ssaidi@eecs.umich.edu for (int i = 0; i < 64; i++) { 4703880Ssaidi@eecs.umich.edu if (shared_data->itb[i] != thread->getITBPtr()->TteRead(i)) 4713880Ssaidi@eecs.umich.edu diffTlb = true; 4723880Ssaidi@eecs.umich.edu if (shared_data->dtb[i] != thread->getDTBPtr()->TteRead(i)) 4733880Ssaidi@eecs.umich.edu diffTlb = true; 4743880Ssaidi@eecs.umich.edu } 4753880Ssaidi@eecs.umich.edu 4764008Ssaidi@eecs.umich.edu if (diffPC || diffCC || diffInst || diffIntRegs || 4773931Ssaidi@eecs.umich.edu diffFpRegs || diffTpc || diffTnpc || diffTstate || 4783931Ssaidi@eecs.umich.edu diffTt || diffHpstate || diffHtstate || diffHtba || 4794001Ssaidi@eecs.umich.edu diffPstate || diffY || diffCcr || diffTl || diffFsr || 4804001Ssaidi@eecs.umich.edu diffGl || diffAsi || diffPil || diffCwp || diffCansave || 4813931Ssaidi@eecs.umich.edu diffCanrestore || diffOtherwin || diffCleanwin || diffTlb) 4824008Ssaidi@eecs.umich.edu { 4833863Ssaidi@eecs.umich.edu 4843584Ssaidi@eecs.umich.edu outs << "Differences found between M5 and Legion:"; 4853584Ssaidi@eecs.umich.edu if (diffPC) 4863584Ssaidi@eecs.umich.edu outs << " [PC]"; 4873814Ssaidi@eecs.umich.edu if (diffCC) 4883814Ssaidi@eecs.umich.edu outs << " [CC]"; 4893584Ssaidi@eecs.umich.edu if (diffInst) 4903584Ssaidi@eecs.umich.edu outs << " [Instruction]"; 4913931Ssaidi@eecs.umich.edu if (diffIntRegs) 4923584Ssaidi@eecs.umich.edu outs << " [IntRegs]"; 4933931Ssaidi@eecs.umich.edu if (diffFpRegs) 4943931Ssaidi@eecs.umich.edu outs << " [FpRegs]"; 4953748Sgblack@eecs.umich.edu if (diffTpc) 4963748Sgblack@eecs.umich.edu outs << " [Tpc]"; 4973748Sgblack@eecs.umich.edu if (diffTnpc) 4983748Sgblack@eecs.umich.edu outs << " [Tnpc]"; 4993748Sgblack@eecs.umich.edu if (diffTstate) 5003748Sgblack@eecs.umich.edu outs << " [Tstate]"; 5013748Sgblack@eecs.umich.edu if (diffTt) 5023748Sgblack@eecs.umich.edu outs << " [Tt]"; 5033748Sgblack@eecs.umich.edu if (diffHpstate) 5043748Sgblack@eecs.umich.edu outs << " [Hpstate]"; 5053748Sgblack@eecs.umich.edu if (diffHtstate) 5063748Sgblack@eecs.umich.edu outs << " [Htstate]"; 5073748Sgblack@eecs.umich.edu if (diffHtba) 5083748Sgblack@eecs.umich.edu outs << " [Htba]"; 5093748Sgblack@eecs.umich.edu if (diffPstate) 5103748Sgblack@eecs.umich.edu outs << " [Pstate]"; 5113748Sgblack@eecs.umich.edu if (diffY) 5123748Sgblack@eecs.umich.edu outs << " [Y]"; 5134001Ssaidi@eecs.umich.edu if (diffFsr) 5144001Ssaidi@eecs.umich.edu outs << " [FSR]"; 5153748Sgblack@eecs.umich.edu if (diffCcr) 5163748Sgblack@eecs.umich.edu outs << " [Ccr]"; 5173748Sgblack@eecs.umich.edu if (diffTl) 5183748Sgblack@eecs.umich.edu outs << " [Tl]"; 5193748Sgblack@eecs.umich.edu if (diffGl) 5203748Sgblack@eecs.umich.edu outs << " [Gl]"; 5213748Sgblack@eecs.umich.edu if (diffAsi) 5223748Sgblack@eecs.umich.edu outs << " [Asi]"; 5233748Sgblack@eecs.umich.edu if (diffPil) 5243748Sgblack@eecs.umich.edu outs << " [Pil]"; 5253748Sgblack@eecs.umich.edu if (diffCwp) 5263748Sgblack@eecs.umich.edu outs << " [Cwp]"; 5273748Sgblack@eecs.umich.edu if (diffCansave) 5283748Sgblack@eecs.umich.edu outs << " [Cansave]"; 5293748Sgblack@eecs.umich.edu if (diffCanrestore) 5303748Sgblack@eecs.umich.edu outs << " [Canrestore]"; 5313748Sgblack@eecs.umich.edu if (diffOtherwin) 5323748Sgblack@eecs.umich.edu outs << " [Otherwin]"; 5333748Sgblack@eecs.umich.edu if (diffCleanwin) 5343748Sgblack@eecs.umich.edu outs << " [Cleanwin]"; 5353880Ssaidi@eecs.umich.edu if (diffTlb) 5363880Ssaidi@eecs.umich.edu outs << " [Tlb]"; 5373603Ssaidi@eecs.umich.edu outs << endl << endl; 5383584Ssaidi@eecs.umich.edu 5393603Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 5403584Ssaidi@eecs.umich.edu << "M5 PC: " << "0x"<< setw(16) << setfill('0') 5413603Ssaidi@eecs.umich.edu << hex << m5Pc << endl; 5423584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5433584Ssaidi@eecs.umich.edu << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex 5443603Ssaidi@eecs.umich.edu << lgnPc << endl << endl; 5453584Ssaidi@eecs.umich.edu 5463814Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 5473814Ssaidi@eecs.umich.edu << "M5 CC: " << "0x"<< setw(16) << setfill('0') 5483814Ssaidi@eecs.umich.edu << hex << thread->getCpuPtr()->instCount() << endl; 5493814Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5503814Ssaidi@eecs.umich.edu << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex 5513814Ssaidi@eecs.umich.edu << shared_data->cycle_count << endl << endl; 5523814Ssaidi@eecs.umich.edu 5533584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5543584Ssaidi@eecs.umich.edu << "M5 Inst: " << "0x"<< setw(8) 5553584Ssaidi@eecs.umich.edu << setfill('0') << hex << staticInst->machInst 5563603Ssaidi@eecs.umich.edu << staticInst->disassemble(m5Pc, debugSymbolTable) 5573584Ssaidi@eecs.umich.edu << endl; 5583584Ssaidi@eecs.umich.edu 5593748Sgblack@eecs.umich.edu StaticInstPtr legionInst = 5603748Sgblack@eecs.umich.edu StaticInst::decode(makeExtMI(shared_data->instruction, 5613748Sgblack@eecs.umich.edu thread)); 5623584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 5633584Ssaidi@eecs.umich.edu << " Legion Inst: " 5643584Ssaidi@eecs.umich.edu << "0x" << setw(8) << setfill('0') << hex 5653584Ssaidi@eecs.umich.edu << shared_data->instruction 5663603Ssaidi@eecs.umich.edu << legionInst->disassemble(lgnPc, debugSymbolTable) 5673748Sgblack@eecs.umich.edu << endl << endl; 5683584Ssaidi@eecs.umich.edu 5693748Sgblack@eecs.umich.edu printSectionHeader(outs, "General State"); 5703748Sgblack@eecs.umich.edu printColumnLabels(outs); 5713748Sgblack@eecs.umich.edu printRegPair(outs, "HPstate", 5723748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HPSTATE), 5733748Sgblack@eecs.umich.edu shared_data->hpstate | (1 << 11)); 5743748Sgblack@eecs.umich.edu printRegPair(outs, "Htba", 5753748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HTBA), 5763748Sgblack@eecs.umich.edu shared_data->htba); 5773748Sgblack@eecs.umich.edu printRegPair(outs, "Pstate", 5783748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_PSTATE), 5793748Sgblack@eecs.umich.edu shared_data->pstate); 5803748Sgblack@eecs.umich.edu printRegPair(outs, "Y", 5813790Sgblack@eecs.umich.edu //thread->readMiscReg(MISCREG_Y), 5823989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 1), 5833748Sgblack@eecs.umich.edu shared_data->y); 5844001Ssaidi@eecs.umich.edu printRegPair(outs, "FSR", 5854001Ssaidi@eecs.umich.edu thread->readMiscReg(MISCREG_FSR), 5864001Ssaidi@eecs.umich.edu shared_data->fsr); 5873748Sgblack@eecs.umich.edu printRegPair(outs, "Ccr", 5883790Sgblack@eecs.umich.edu //thread->readMiscReg(MISCREG_CCR), 5893989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 2), 5903748Sgblack@eecs.umich.edu shared_data->ccr); 5913748Sgblack@eecs.umich.edu printRegPair(outs, "Tl", 5923748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TL), 5933748Sgblack@eecs.umich.edu shared_data->tl); 5943748Sgblack@eecs.umich.edu printRegPair(outs, "Gl", 5953748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_GL), 5963748Sgblack@eecs.umich.edu shared_data->gl); 5973748Sgblack@eecs.umich.edu printRegPair(outs, "Asi", 5983748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_ASI), 5993748Sgblack@eecs.umich.edu shared_data->asi); 6003748Sgblack@eecs.umich.edu printRegPair(outs, "Pil", 6013748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_PIL), 6023748Sgblack@eecs.umich.edu shared_data->pil); 6033748Sgblack@eecs.umich.edu printRegPair(outs, "Cwp", 6043748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CWP), 6053748Sgblack@eecs.umich.edu shared_data->cwp); 6063748Sgblack@eecs.umich.edu printRegPair(outs, "Cansave", 6073790Sgblack@eecs.umich.edu //thread->readMiscReg(MISCREG_CANSAVE), 6083790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 3), 6093748Sgblack@eecs.umich.edu shared_data->cansave); 6103748Sgblack@eecs.umich.edu printRegPair(outs, "Canrestore", 6113790Sgblack@eecs.umich.edu //thread->readMiscReg(MISCREG_CANRESTORE), 6123790Sgblack@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 4), 6133748Sgblack@eecs.umich.edu shared_data->canrestore); 6143748Sgblack@eecs.umich.edu printRegPair(outs, "Otherwin", 6153790Sgblack@eecs.umich.edu //thread->readMiscReg(MISCREG_OTHERWIN), 6163989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 6), 6173748Sgblack@eecs.umich.edu shared_data->otherwin); 6183748Sgblack@eecs.umich.edu printRegPair(outs, "Cleanwin", 6193790Sgblack@eecs.umich.edu //thread->readMiscReg(MISCREG_CLEANWIN), 6203989Ssaidi@eecs.umich.edu thread->readIntReg(NumIntArchRegs + 5), 6213748Sgblack@eecs.umich.edu shared_data->cleanwin); 6223748Sgblack@eecs.umich.edu outs << endl; 6233748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 6243748Sgblack@eecs.umich.edu printLevelHeader(outs, i); 6253748Sgblack@eecs.umich.edu printColumnLabels(outs); 6263748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, i); 6273748Sgblack@eecs.umich.edu printRegPair(outs, "Tpc", 6283748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TPC), 6293815Ssaidi@eecs.umich.edu shared_data->tpc[i-1]); 6303748Sgblack@eecs.umich.edu printRegPair(outs, "Tnpc", 6313748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TNPC), 6323815Ssaidi@eecs.umich.edu shared_data->tnpc[i-1]); 6333748Sgblack@eecs.umich.edu printRegPair(outs, "Tstate", 6343748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TSTATE), 6353815Ssaidi@eecs.umich.edu shared_data->tstate[i-1]); 6363748Sgblack@eecs.umich.edu printRegPair(outs, "Tt", 6373748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TT), 6383815Ssaidi@eecs.umich.edu shared_data->tt[i-1]); 6393748Sgblack@eecs.umich.edu printRegPair(outs, "Htstate", 6403748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HTSTATE), 6413815Ssaidi@eecs.umich.edu shared_data->htstate[i-1]); 6423748Sgblack@eecs.umich.edu } 6433748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, oldTl); 6443584Ssaidi@eecs.umich.edu outs << endl; 6453584Ssaidi@eecs.umich.edu 6463748Sgblack@eecs.umich.edu printSectionHeader(outs, "General Purpose Registers"); 6473584Ssaidi@eecs.umich.edu static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; 6483931Ssaidi@eecs.umich.edu for(int y = 0; y < 4; y++) { 6493931Ssaidi@eecs.umich.edu for(int x = 0; x < 8; x++) { 6503748Sgblack@eecs.umich.edu char label[8]; 6513748Sgblack@eecs.umich.edu sprintf(label, "%s%d", regtypes[y], x); 6523748Sgblack@eecs.umich.edu printRegPair(outs, label, 6533748Sgblack@eecs.umich.edu thread->readIntReg(y*8+x), 6543748Sgblack@eecs.umich.edu shared_data->intregs[y*8+x]); 6553931Ssaidi@eecs.umich.edu } 6563931Ssaidi@eecs.umich.edu } 6573931Ssaidi@eecs.umich.edu if (diffFpRegs) { 6583931Ssaidi@eecs.umich.edu for (int x = 0; x < 32; x++) { 6593931Ssaidi@eecs.umich.edu char label[8]; 6603931Ssaidi@eecs.umich.edu sprintf(label, "%%f%d", x); 6613931Ssaidi@eecs.umich.edu printRegPair(outs, label, 6624008Ssaidi@eecs.umich.edu thread->readFloatRegBits(x*2,FloatRegFile::DoubleWidth), 6633931Ssaidi@eecs.umich.edu shared_data->fpregs[x]); 6643584Ssaidi@eecs.umich.edu } 6653584Ssaidi@eecs.umich.edu } 6663903Ssaidi@eecs.umich.edu if (diffTlb) { 6673903Ssaidi@eecs.umich.edu printColumnLabels(outs); 6683903Ssaidi@eecs.umich.edu char label[8]; 6693903Ssaidi@eecs.umich.edu for (int x = 0; x < 64; x++) { 6703903Ssaidi@eecs.umich.edu if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) || 6713903Ssaidi@eecs.umich.edu thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { 6723903Ssaidi@eecs.umich.edu sprintf(label, "I-TLB:%02d", x); 6733903Ssaidi@eecs.umich.edu printRegPair(outs, label, thread->getITBPtr()->TteRead(x), 6743903Ssaidi@eecs.umich.edu shared_data->itb[x]); 6753903Ssaidi@eecs.umich.edu } 6763880Ssaidi@eecs.umich.edu } 6773903Ssaidi@eecs.umich.edu for (int x = 0; x < 64; x++) { 6783903Ssaidi@eecs.umich.edu if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) || 6793903Ssaidi@eecs.umich.edu thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { 6803903Ssaidi@eecs.umich.edu sprintf(label, "D-TLB:%02d", x); 6813903Ssaidi@eecs.umich.edu printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), 6823903Ssaidi@eecs.umich.edu shared_data->dtb[x]); 6833903Ssaidi@eecs.umich.edu } 6843903Ssaidi@eecs.umich.edu } 6853903Ssaidi@eecs.umich.edu thread->getITBPtr()->dumpAll(); 6863903Ssaidi@eecs.umich.edu thread->getDTBPtr()->dumpAll(); 6873880Ssaidi@eecs.umich.edu } 6883826Ssaidi@eecs.umich.edu 6893825Ssaidi@eecs.umich.edu diffcount++; 6904011Ssaidi@eecs.umich.edu if (diffcount > 3) 6913825Ssaidi@eecs.umich.edu fatal("Differences found between Legion and M5\n"); 6923892Ssaidi@eecs.umich.edu } else 6933892Ssaidi@eecs.umich.edu diffcount = 0; 6943584Ssaidi@eecs.umich.edu 6953584Ssaidi@eecs.umich.edu compared = true; 6963584Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 6973506Ssaidi@eecs.umich.edu } 6983584Ssaidi@eecs.umich.edu } // while 6993584Ssaidi@eecs.umich.edu } // if not microop 7003506Ssaidi@eecs.umich.edu } 7013584Ssaidi@eecs.umich.edu#endif 7022SN/A} 7032SN/A 7044054Sbinkertn@umich.edu/* namespace Trace */ } 705