exetrace.cc revision 3748
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 363506Ssaidi@eecs.umich.edu#include <sys/ipc.h> 373506Ssaidi@eecs.umich.edu#include <sys/shm.h> 382SN/A 392973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 403584Ssaidi@eecs.umich.edu#include "arch/utility.hh" 4156SN/A#include "base/loader/symtab.hh" 423614Sgblack@eecs.umich.edu#include "config/full_system.hh" 431717SN/A#include "cpu/base.hh" 442518SN/A#include "cpu/exetrace.hh" 4556SN/A#include "cpu/static_inst.hh" 462518SN/A#include "sim/param.hh" 472518SN/A#include "sim/system.hh" 482SN/A 493614Sgblack@eecs.umich.edu#if FULL_SYSTEM 503614Sgblack@eecs.umich.edu#include "arch/tlb.hh" 513614Sgblack@eecs.umich.edu#endif 523614Sgblack@eecs.umich.edu 533065Sgblack@eecs.umich.edu//XXX This is temporary 543065Sgblack@eecs.umich.edu#include "arch/isa_specific.hh" 553506Ssaidi@eecs.umich.edu#include "cpu/m5legion_interface.h" 563065Sgblack@eecs.umich.edu 572SN/Ausing namespace std; 582973Sgblack@eecs.umich.eduusing namespace TheISA; 592SN/A 603506Ssaidi@eecs.umich.edunamespace Trace { 613506Ssaidi@eecs.umich.eduSharedData *shared_data = NULL; 623506Ssaidi@eecs.umich.edu} 633506Ssaidi@eecs.umich.edu 642SN/A//////////////////////////////////////////////////////////////////////// 652SN/A// 662SN/A// Methods for the InstRecord object 672SN/A// 682SN/A 693748Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 703748Sgblack@eecs.umich.edu 713748Sgblack@eecs.umich.eduinline char * genCenteredLabel(int length, char * buffer, char * label) 723748Sgblack@eecs.umich.edu{ 733748Sgblack@eecs.umich.edu int labelLength = strlen(label); 743748Sgblack@eecs.umich.edu assert(labelLength <= length); 753748Sgblack@eecs.umich.edu int leftPad = (length - labelLength) / 2; 763748Sgblack@eecs.umich.edu int rightPad = length - leftPad - labelLength; 773748Sgblack@eecs.umich.edu char format[64]; 783748Sgblack@eecs.umich.edu sprintf(format, "%%%ds%%s%%%ds", leftPad, rightPad); 793748Sgblack@eecs.umich.edu sprintf(buffer, format, "", label, ""); 803748Sgblack@eecs.umich.edu return buffer; 813748Sgblack@eecs.umich.edu} 823748Sgblack@eecs.umich.edu 833748Sgblack@eecs.umich.eduinline void printRegPair(ostream & os, char const * title, uint64_t a, uint64_t b) 843748Sgblack@eecs.umich.edu{ 853748Sgblack@eecs.umich.edu ccprintf(os, " %16s | %#018x %s %#-018x \n", 863748Sgblack@eecs.umich.edu title, a, (a == b) ? "|" : "X", b); 873748Sgblack@eecs.umich.edu} 883748Sgblack@eecs.umich.edu 893748Sgblack@eecs.umich.eduinline void printColumnLabels(ostream & os) 903748Sgblack@eecs.umich.edu{ 913748Sgblack@eecs.umich.edu static char * regLabel = genCenteredLabel(16, new char[17], "Register"); 923748Sgblack@eecs.umich.edu static char * m5Label = genCenteredLabel(18, new char[18], "M5"); 933748Sgblack@eecs.umich.edu static char * legionLabel = genCenteredLabel(18, new char[18], "Legion"); 943748Sgblack@eecs.umich.edu ccprintf(os, " %s | %s | %s \n", regLabel, m5Label, legionLabel); 953748Sgblack@eecs.umich.edu ccprintf(os, "--------------------+-----------------------+-----------------------\n"); 963748Sgblack@eecs.umich.edu} 973748Sgblack@eecs.umich.edu 983748Sgblack@eecs.umich.eduinline void printSectionHeader(ostream & os, char * name) 993748Sgblack@eecs.umich.edu{ 1003748Sgblack@eecs.umich.edu char sectionString[70]; 1013748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, name); 1023748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1033748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1043748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1053748Sgblack@eecs.umich.edu} 1063748Sgblack@eecs.umich.edu 1073748Sgblack@eecs.umich.eduinline void printLevelHeader(ostream & os, int level) 1083748Sgblack@eecs.umich.edu{ 1093748Sgblack@eecs.umich.edu char sectionString[70]; 1103748Sgblack@eecs.umich.edu char levelName[70]; 1113748Sgblack@eecs.umich.edu sprintf(levelName, "Trap stack level %d", level); 1123748Sgblack@eecs.umich.edu genCenteredLabel(69, sectionString, levelName); 1133748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1143748Sgblack@eecs.umich.edu ccprintf(os, "%69s\n", sectionString); 1153748Sgblack@eecs.umich.edu ccprintf(os, "====================================================================\n"); 1163748Sgblack@eecs.umich.edu} 1173748Sgblack@eecs.umich.edu 1183748Sgblack@eecs.umich.edu#endif 1192SN/A 1202SN/Avoid 1212SN/ATrace::InstRecord::dump(ostream &outs) 1222SN/A{ 1232973Sgblack@eecs.umich.edu if (flags[PRINT_REG_DELTA]) 1242973Sgblack@eecs.umich.edu { 1253065Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 1263380Sgblack@eecs.umich.edu //Don't print what happens for each micro-op, just print out 1273380Sgblack@eecs.umich.edu //once at the last op, and for regular instructions. 1283380Sgblack@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 1293380Sgblack@eecs.umich.edu { 1303380Sgblack@eecs.umich.edu static uint64_t regs[32] = { 1313380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1323380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1333380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 1343380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 1353380Sgblack@eecs.umich.edu static uint64_t ccr = 0; 1363380Sgblack@eecs.umich.edu static uint64_t y = 0; 1373380Sgblack@eecs.umich.edu static uint64_t floats[32]; 1383380Sgblack@eecs.umich.edu uint64_t newVal; 1393380Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 1403065Sgblack@eecs.umich.edu 1413588Sgblack@eecs.umich.edu outs << hex; 1423588Sgblack@eecs.umich.edu outs << "PC = " << thread->readNextPC(); 1433588Sgblack@eecs.umich.edu outs << " NPC = " << thread->readNextNPC(); 1443380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); 1453380Sgblack@eecs.umich.edu if(newVal != ccr) 1463059Sgblack@eecs.umich.edu { 1473588Sgblack@eecs.umich.edu outs << " CCR = " << newVal; 1483380Sgblack@eecs.umich.edu ccr = newVal; 1493380Sgblack@eecs.umich.edu } 1503380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_Y); 1513380Sgblack@eecs.umich.edu if(newVal != y) 1523380Sgblack@eecs.umich.edu { 1533588Sgblack@eecs.umich.edu outs << " Y = " << newVal; 1543380Sgblack@eecs.umich.edu y = newVal; 1553380Sgblack@eecs.umich.edu } 1563380Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 1573380Sgblack@eecs.umich.edu { 1583380Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 1593059Sgblack@eecs.umich.edu { 1603380Sgblack@eecs.umich.edu int index = x + 8 * y; 1613380Sgblack@eecs.umich.edu newVal = thread->readIntReg(index); 1623380Sgblack@eecs.umich.edu if(regs[index] != newVal) 1633380Sgblack@eecs.umich.edu { 1643588Sgblack@eecs.umich.edu outs << " " << prefixes[y] << dec << x << " = " << hex << newVal; 1653380Sgblack@eecs.umich.edu regs[index] = newVal; 1663380Sgblack@eecs.umich.edu } 1673059Sgblack@eecs.umich.edu } 1683059Sgblack@eecs.umich.edu } 1693380Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 1703380Sgblack@eecs.umich.edu { 1713380Sgblack@eecs.umich.edu newVal = thread->readFloatRegBits(2 * y, 64); 1723380Sgblack@eecs.umich.edu if(floats[y] != newVal) 1733380Sgblack@eecs.umich.edu { 1743588Sgblack@eecs.umich.edu outs << " F" << dec << (2 * y) << " = " << hex << newVal; 1753380Sgblack@eecs.umich.edu floats[y] = newVal; 1763380Sgblack@eecs.umich.edu } 1773380Sgblack@eecs.umich.edu } 1783588Sgblack@eecs.umich.edu outs << dec << endl; 1793059Sgblack@eecs.umich.edu } 1803065Sgblack@eecs.umich.edu#endif 1812973Sgblack@eecs.umich.edu } 1822973Sgblack@eecs.umich.edu else if (flags[INTEL_FORMAT]) { 1831968SN/A#if FULL_SYSTEM 1843064Sgblack@eecs.umich.edu bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system); 1851968SN/A#else 1861968SN/A bool is_trace_system = true; 1871968SN/A#endif 1881968SN/A if (is_trace_system) { 1891967SN/A ccprintf(outs, "%7d ) ", cycle); 1901967SN/A outs << "0x" << hex << PC << ":\t"; 1911967SN/A if (staticInst->isLoad()) { 1921967SN/A outs << "<RD 0x" << hex << addr; 1931967SN/A outs << ">"; 1941967SN/A } else if (staticInst->isStore()) { 1951967SN/A outs << "<WR 0x" << hex << addr; 1961967SN/A outs << ">"; 1971967SN/A } 1981967SN/A outs << endl; 1991904SN/A } 2001904SN/A } else { 2011904SN/A if (flags[PRINT_CYCLE]) 2021904SN/A ccprintf(outs, "%7d: ", cycle); 203452SN/A 2043064Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 2052SN/A 2061904SN/A if (flags[TRACE_MISSPEC]) 2071904SN/A outs << (misspeculating ? "-" : "+") << " "; 2082SN/A 2091904SN/A if (flags[PRINT_THREAD_NUM]) 2103064Sgblack@eecs.umich.edu outs << "T" << thread->getThreadNum() << " : "; 2112SN/A 2122SN/A 2131904SN/A std::string sym_str; 2141904SN/A Addr sym_addr; 2151904SN/A if (debugSymbolTable 2162299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 2172299SN/A && flags[PC_SYMBOL]) { 2181904SN/A if (PC != sym_addr) 2191904SN/A sym_str += csprintf("+%d", PC - sym_addr); 2201904SN/A outs << "@" << sym_str << " : "; 2211904SN/A } 2221904SN/A else { 2231904SN/A outs << "0x" << hex << PC << " : "; 2241904SN/A } 225452SN/A 2261904SN/A // 2271904SN/A // Print decoded instruction 2281904SN/A // 2292SN/A 2302SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 2311904SN/A // There's a bug in gcc 2.x library that prevents setw() 2321904SN/A // from working properly on strings 2331904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 2341904SN/A while (mc.length() < 26) 2351904SN/A mc += " "; 2361904SN/A outs << mc; 2372SN/A#else 2381904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 2392SN/A#endif 2402SN/A 2411904SN/A outs << " : "; 2422SN/A 2431904SN/A if (flags[PRINT_OP_CLASS]) { 2441904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 2451904SN/A } 2461904SN/A 2471904SN/A if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 2481904SN/A outs << " D="; 2491904SN/A#if 0 2501904SN/A if (data_status == DataDouble) 2511904SN/A ccprintf(outs, "%f", data.as_double); 2521904SN/A else 2531904SN/A ccprintf(outs, "%#018x", data.as_int); 2541904SN/A#else 2551904SN/A ccprintf(outs, "%#018x", data.as_int); 2561904SN/A#endif 2571904SN/A } 2581904SN/A 2591904SN/A if (flags[PRINT_EFF_ADDR] && addr_valid) 2601904SN/A outs << " A=0x" << hex << addr; 2611904SN/A 2621904SN/A if (flags[PRINT_INT_REGS] && regs_valid) { 2632525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 2641904SN/A for (int j = i + 1; i <= j; i++) 2652525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 2662525SN/A iregs->regs.readReg(i), 2672525SN/A ((i == j) ? "\n" : " ")); 2681904SN/A outs << "\n"; 2691904SN/A } 2701904SN/A 2711904SN/A if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 2721904SN/A outs << " FetchSeq=" << dec << fetch_seq; 2731904SN/A 2741904SN/A if (flags[PRINT_CP_SEQ] && cp_seq_valid) 2751904SN/A outs << " CPSeq=" << dec << cp_seq; 2761967SN/A 2771967SN/A // 2781967SN/A // End of line... 2791967SN/A // 2801967SN/A outs << endl; 2812SN/A } 2823584Ssaidi@eecs.umich.edu#if THE_ISA == SPARC_ISA 2833506Ssaidi@eecs.umich.edu // Compare 2843506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) 2853506Ssaidi@eecs.umich.edu { 2863506Ssaidi@eecs.umich.edu bool compared = false; 2873506Ssaidi@eecs.umich.edu bool diffPC = false; 2883506Ssaidi@eecs.umich.edu bool diffInst = false; 2893506Ssaidi@eecs.umich.edu bool diffRegs = false; 2903748Sgblack@eecs.umich.edu bool diffTpc = false; 2913748Sgblack@eecs.umich.edu bool diffTnpc = false; 2923748Sgblack@eecs.umich.edu bool diffTstate = false; 2933748Sgblack@eecs.umich.edu bool diffTt = false; 2943748Sgblack@eecs.umich.edu bool diffTba = false; 2953748Sgblack@eecs.umich.edu bool diffHpstate = false; 2963748Sgblack@eecs.umich.edu bool diffHtstate = false; 2973748Sgblack@eecs.umich.edu bool diffHtba = false; 2983748Sgblack@eecs.umich.edu bool diffPstate = false; 2993748Sgblack@eecs.umich.edu bool diffY = false; 3003748Sgblack@eecs.umich.edu bool diffCcr = false; 3013748Sgblack@eecs.umich.edu bool diffTl = false; 3023748Sgblack@eecs.umich.edu bool diffGl = false; 3033748Sgblack@eecs.umich.edu bool diffAsi = false; 3043748Sgblack@eecs.umich.edu bool diffPil = false; 3053748Sgblack@eecs.umich.edu bool diffCwp = false; 3063748Sgblack@eecs.umich.edu bool diffCansave = false; 3073748Sgblack@eecs.umich.edu bool diffCanrestore = false; 3083748Sgblack@eecs.umich.edu bool diffOtherwin = false; 3093748Sgblack@eecs.umich.edu bool diffCleanwin = false; 3103603Ssaidi@eecs.umich.edu Addr m5Pc, lgnPc; 3113603Ssaidi@eecs.umich.edu 3123506Ssaidi@eecs.umich.edu 3133584Ssaidi@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { 3143584Ssaidi@eecs.umich.edu while (!compared) { 3153584Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 3163748Sgblack@eecs.umich.edu m5Pc = PC & TheISA::PAddrImplMask; 3173748Sgblack@eecs.umich.edu lgnPc = shared_data->pc & TheISA::PAddrImplMask; 3183603Ssaidi@eecs.umich.edu if (lgnPc != m5Pc) 3193584Ssaidi@eecs.umich.edu diffPC = true; 3203743Sgblack@eecs.umich.edu if (shared_data->instruction != 3213743Sgblack@eecs.umich.edu (SparcISA::MachInst)staticInst->machInst) { 3223584Ssaidi@eecs.umich.edu diffInst = true; 3233743Sgblack@eecs.umich.edu } 3243603Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumRegularIntRegs; i++) { 3253603Ssaidi@eecs.umich.edu if (thread->readIntReg(i) != shared_data->intregs[i]) { 3263584Ssaidi@eecs.umich.edu diffRegs = true; 3273603Ssaidi@eecs.umich.edu } 3283584Ssaidi@eecs.umich.edu } 3293748Sgblack@eecs.umich.edu uint64_t oldTl = thread->readMiscReg(MISCREG_TL); 3303748Sgblack@eecs.umich.edu if (oldTl != shared_data->tl) 3313748Sgblack@eecs.umich.edu diffTl = true; 3323748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 3333748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, i); 3343748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TPC) != 3353748Sgblack@eecs.umich.edu shared_data->tpc[i]) 3363748Sgblack@eecs.umich.edu diffTpc = true; 3373748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TNPC) != 3383748Sgblack@eecs.umich.edu shared_data->tnpc[i]) 3393748Sgblack@eecs.umich.edu diffTnpc = true; 3403748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TSTATE) != 3413748Sgblack@eecs.umich.edu shared_data->tstate[i]) 3423748Sgblack@eecs.umich.edu diffTstate = true; 3433748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_TT) != 3443748Sgblack@eecs.umich.edu shared_data->tt[i]) 3453748Sgblack@eecs.umich.edu diffTt = true; 3463748Sgblack@eecs.umich.edu if (thread->readMiscReg(MISCREG_HTSTATE) != 3473748Sgblack@eecs.umich.edu shared_data->htstate[i]) 3483748Sgblack@eecs.umich.edu diffHtstate = true; 3493748Sgblack@eecs.umich.edu } 3503748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, oldTl); 3513584Ssaidi@eecs.umich.edu 3523748Sgblack@eecs.umich.edu if(shared_data->tba != thread->readMiscReg(MISCREG_TBA)) 3533748Sgblack@eecs.umich.edu diffTba = true; 3543748Sgblack@eecs.umich.edu //When the hpstate register is read by an instruction, 3553748Sgblack@eecs.umich.edu //legion has bit 11 set. When it's in storage, it doesn't. 3563748Sgblack@eecs.umich.edu //Since we don't directly support seperate interpretations 3573748Sgblack@eecs.umich.edu //of the registers like that, the bit is always set to 1 and 3583748Sgblack@eecs.umich.edu //we just don't compare it. It's not supposed to matter 3593748Sgblack@eecs.umich.edu //anyway. 3603748Sgblack@eecs.umich.edu if((shared_data->hpstate | (1 << 11)) != thread->readMiscReg(MISCREG_HPSTATE)) 3613748Sgblack@eecs.umich.edu diffHpstate = true; 3623748Sgblack@eecs.umich.edu if(shared_data->htba != thread->readMiscReg(MISCREG_HTBA)) 3633748Sgblack@eecs.umich.edu diffHtba = true; 3643748Sgblack@eecs.umich.edu if(shared_data->pstate != thread->readMiscReg(MISCREG_PSTATE)) 3653748Sgblack@eecs.umich.edu diffPstate = true; 3663748Sgblack@eecs.umich.edu if(shared_data->y != thread->readMiscReg(MISCREG_Y)) 3673748Sgblack@eecs.umich.edu diffY = true; 3683748Sgblack@eecs.umich.edu if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR)) 3693748Sgblack@eecs.umich.edu diffCcr = true; 3703748Sgblack@eecs.umich.edu if(shared_data->gl != thread->readMiscReg(MISCREG_GL)) 3713748Sgblack@eecs.umich.edu diffGl = true; 3723748Sgblack@eecs.umich.edu if(shared_data->asi != thread->readMiscReg(MISCREG_ASI)) 3733748Sgblack@eecs.umich.edu diffAsi = true; 3743748Sgblack@eecs.umich.edu if(shared_data->pil != thread->readMiscReg(MISCREG_PIL)) 3753748Sgblack@eecs.umich.edu diffPil = true; 3763748Sgblack@eecs.umich.edu if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP)) 3773748Sgblack@eecs.umich.edu diffCwp = true; 3783748Sgblack@eecs.umich.edu if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE)) 3793748Sgblack@eecs.umich.edu diffCansave = true; 3803748Sgblack@eecs.umich.edu if(shared_data->canrestore != 3813748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CANRESTORE)) 3823748Sgblack@eecs.umich.edu diffCanrestore = true; 3833748Sgblack@eecs.umich.edu if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN)) 3843748Sgblack@eecs.umich.edu diffOtherwin = true; 3853748Sgblack@eecs.umich.edu if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN)) 3863748Sgblack@eecs.umich.edu diffCleanwin = true; 3873748Sgblack@eecs.umich.edu 3883748Sgblack@eecs.umich.edu if (diffPC || diffInst || diffRegs || diffTpc || diffTnpc || 3893748Sgblack@eecs.umich.edu diffTstate || diffTt || diffHpstate || 3903748Sgblack@eecs.umich.edu diffHtstate || diffHtba || diffPstate || diffY || 3913748Sgblack@eecs.umich.edu diffCcr || diffTl || diffGl || diffAsi || diffPil || 3923748Sgblack@eecs.umich.edu diffCwp || diffCansave || diffCanrestore || 3933748Sgblack@eecs.umich.edu diffOtherwin || diffCleanwin) { 3943584Ssaidi@eecs.umich.edu outs << "Differences found between M5 and Legion:"; 3953584Ssaidi@eecs.umich.edu if (diffPC) 3963584Ssaidi@eecs.umich.edu outs << " [PC]"; 3973584Ssaidi@eecs.umich.edu if (diffInst) 3983584Ssaidi@eecs.umich.edu outs << " [Instruction]"; 3993584Ssaidi@eecs.umich.edu if (diffRegs) 4003584Ssaidi@eecs.umich.edu outs << " [IntRegs]"; 4013748Sgblack@eecs.umich.edu if (diffTpc) 4023748Sgblack@eecs.umich.edu outs << " [Tpc]"; 4033748Sgblack@eecs.umich.edu if (diffTnpc) 4043748Sgblack@eecs.umich.edu outs << " [Tnpc]"; 4053748Sgblack@eecs.umich.edu if (diffTstate) 4063748Sgblack@eecs.umich.edu outs << " [Tstate]"; 4073748Sgblack@eecs.umich.edu if (diffTt) 4083748Sgblack@eecs.umich.edu outs << " [Tt]"; 4093748Sgblack@eecs.umich.edu if (diffHpstate) 4103748Sgblack@eecs.umich.edu outs << " [Hpstate]"; 4113748Sgblack@eecs.umich.edu if (diffHtstate) 4123748Sgblack@eecs.umich.edu outs << " [Htstate]"; 4133748Sgblack@eecs.umich.edu if (diffHtba) 4143748Sgblack@eecs.umich.edu outs << " [Htba]"; 4153748Sgblack@eecs.umich.edu if (diffPstate) 4163748Sgblack@eecs.umich.edu outs << " [Pstate]"; 4173748Sgblack@eecs.umich.edu if (diffY) 4183748Sgblack@eecs.umich.edu outs << " [Y]"; 4193748Sgblack@eecs.umich.edu if (diffCcr) 4203748Sgblack@eecs.umich.edu outs << " [Ccr]"; 4213748Sgblack@eecs.umich.edu if (diffTl) 4223748Sgblack@eecs.umich.edu outs << " [Tl]"; 4233748Sgblack@eecs.umich.edu if (diffGl) 4243748Sgblack@eecs.umich.edu outs << " [Gl]"; 4253748Sgblack@eecs.umich.edu if (diffAsi) 4263748Sgblack@eecs.umich.edu outs << " [Asi]"; 4273748Sgblack@eecs.umich.edu if (diffPil) 4283748Sgblack@eecs.umich.edu outs << " [Pil]"; 4293748Sgblack@eecs.umich.edu if (diffCwp) 4303748Sgblack@eecs.umich.edu outs << " [Cwp]"; 4313748Sgblack@eecs.umich.edu if (diffCansave) 4323748Sgblack@eecs.umich.edu outs << " [Cansave]"; 4333748Sgblack@eecs.umich.edu if (diffCanrestore) 4343748Sgblack@eecs.umich.edu outs << " [Canrestore]"; 4353748Sgblack@eecs.umich.edu if (diffOtherwin) 4363748Sgblack@eecs.umich.edu outs << " [Otherwin]"; 4373748Sgblack@eecs.umich.edu if (diffCleanwin) 4383748Sgblack@eecs.umich.edu outs << " [Cleanwin]"; 4393603Ssaidi@eecs.umich.edu outs << endl << endl; 4403584Ssaidi@eecs.umich.edu 4413603Ssaidi@eecs.umich.edu outs << right << setfill(' ') << setw(15) 4423584Ssaidi@eecs.umich.edu << "M5 PC: " << "0x"<< setw(16) << setfill('0') 4433603Ssaidi@eecs.umich.edu << hex << m5Pc << endl; 4443584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 4453584Ssaidi@eecs.umich.edu << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex 4463603Ssaidi@eecs.umich.edu << lgnPc << endl << endl; 4473584Ssaidi@eecs.umich.edu 4483584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 4493584Ssaidi@eecs.umich.edu << "M5 Inst: " << "0x"<< setw(8) 4503584Ssaidi@eecs.umich.edu << setfill('0') << hex << staticInst->machInst 4513603Ssaidi@eecs.umich.edu << staticInst->disassemble(m5Pc, debugSymbolTable) 4523584Ssaidi@eecs.umich.edu << endl; 4533584Ssaidi@eecs.umich.edu 4543748Sgblack@eecs.umich.edu StaticInstPtr legionInst = 4553748Sgblack@eecs.umich.edu StaticInst::decode(makeExtMI(shared_data->instruction, 4563748Sgblack@eecs.umich.edu thread)); 4573584Ssaidi@eecs.umich.edu outs << setfill(' ') << setw(15) 4583584Ssaidi@eecs.umich.edu << " Legion Inst: " 4593584Ssaidi@eecs.umich.edu << "0x" << setw(8) << setfill('0') << hex 4603584Ssaidi@eecs.umich.edu << shared_data->instruction 4613603Ssaidi@eecs.umich.edu << legionInst->disassemble(lgnPc, debugSymbolTable) 4623748Sgblack@eecs.umich.edu << endl << endl; 4633584Ssaidi@eecs.umich.edu 4643748Sgblack@eecs.umich.edu printSectionHeader(outs, "General State"); 4653748Sgblack@eecs.umich.edu printColumnLabels(outs); 4663748Sgblack@eecs.umich.edu printRegPair(outs, "HPstate", 4673748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HPSTATE), 4683748Sgblack@eecs.umich.edu shared_data->hpstate | (1 << 11)); 4693748Sgblack@eecs.umich.edu printRegPair(outs, "Htba", 4703748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HTBA), 4713748Sgblack@eecs.umich.edu shared_data->htba); 4723748Sgblack@eecs.umich.edu printRegPair(outs, "Pstate", 4733748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_PSTATE), 4743748Sgblack@eecs.umich.edu shared_data->pstate); 4753748Sgblack@eecs.umich.edu printRegPair(outs, "Y", 4763748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_Y), 4773748Sgblack@eecs.umich.edu shared_data->y); 4783748Sgblack@eecs.umich.edu printRegPair(outs, "Ccr", 4793748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CCR), 4803748Sgblack@eecs.umich.edu shared_data->ccr); 4813748Sgblack@eecs.umich.edu printRegPair(outs, "Tl", 4823748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TL), 4833748Sgblack@eecs.umich.edu shared_data->tl); 4843748Sgblack@eecs.umich.edu printRegPair(outs, "Gl", 4853748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_GL), 4863748Sgblack@eecs.umich.edu shared_data->gl); 4873748Sgblack@eecs.umich.edu printRegPair(outs, "Asi", 4883748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_ASI), 4893748Sgblack@eecs.umich.edu shared_data->asi); 4903748Sgblack@eecs.umich.edu printRegPair(outs, "Pil", 4913748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_PIL), 4923748Sgblack@eecs.umich.edu shared_data->pil); 4933748Sgblack@eecs.umich.edu printRegPair(outs, "Cwp", 4943748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CWP), 4953748Sgblack@eecs.umich.edu shared_data->cwp); 4963748Sgblack@eecs.umich.edu printRegPair(outs, "Cansave", 4973748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CANSAVE), 4983748Sgblack@eecs.umich.edu shared_data->cansave); 4993748Sgblack@eecs.umich.edu printRegPair(outs, "Canrestore", 5003748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CANRESTORE), 5013748Sgblack@eecs.umich.edu shared_data->canrestore); 5023748Sgblack@eecs.umich.edu printRegPair(outs, "Otherwin", 5033748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_OTHERWIN), 5043748Sgblack@eecs.umich.edu shared_data->otherwin); 5053748Sgblack@eecs.umich.edu printRegPair(outs, "Cleanwin", 5063748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_CLEANWIN), 5073748Sgblack@eecs.umich.edu shared_data->cleanwin); 5083748Sgblack@eecs.umich.edu outs << endl; 5093748Sgblack@eecs.umich.edu for (int i = 1; i <= MaxTL; i++) { 5103748Sgblack@eecs.umich.edu printLevelHeader(outs, i); 5113748Sgblack@eecs.umich.edu printColumnLabels(outs); 5123748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, i); 5133748Sgblack@eecs.umich.edu printRegPair(outs, "Tpc", 5143748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TPC), 5153748Sgblack@eecs.umich.edu shared_data->tpc[i]); 5163748Sgblack@eecs.umich.edu printRegPair(outs, "Tnpc", 5173748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TNPC), 5183748Sgblack@eecs.umich.edu shared_data->tnpc[i]); 5193748Sgblack@eecs.umich.edu printRegPair(outs, "Tstate", 5203748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TSTATE), 5213748Sgblack@eecs.umich.edu shared_data->tstate[i]); 5223748Sgblack@eecs.umich.edu printRegPair(outs, "Tt", 5233748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_TT), 5243748Sgblack@eecs.umich.edu shared_data->tt[i]); 5253748Sgblack@eecs.umich.edu printRegPair(outs, "Htstate", 5263748Sgblack@eecs.umich.edu thread->readMiscReg(MISCREG_HTSTATE), 5273748Sgblack@eecs.umich.edu shared_data->htstate[i]); 5283748Sgblack@eecs.umich.edu } 5293748Sgblack@eecs.umich.edu thread->setMiscReg(MISCREG_TL, oldTl); 5303584Ssaidi@eecs.umich.edu outs << endl; 5313584Ssaidi@eecs.umich.edu 5323748Sgblack@eecs.umich.edu printSectionHeader(outs, "General Purpose Registers"); 5333584Ssaidi@eecs.umich.edu static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; 5343584Ssaidi@eecs.umich.edu for(int y = 0; y < 4; y++) 5353584Ssaidi@eecs.umich.edu { 5363584Ssaidi@eecs.umich.edu for(int x = 0; x < 8; x++) 5373584Ssaidi@eecs.umich.edu { 5383748Sgblack@eecs.umich.edu char label[8]; 5393748Sgblack@eecs.umich.edu sprintf(label, "%s%d", regtypes[y], x); 5403748Sgblack@eecs.umich.edu printRegPair(outs, label, 5413748Sgblack@eecs.umich.edu thread->readIntReg(y*8+x), 5423748Sgblack@eecs.umich.edu shared_data->intregs[y*8+x]); 5433748Sgblack@eecs.umich.edu /*outs << regtypes[y] << x << " " ; 5443748Sgblack@eecs.umich.edu outs << "0x" << hex << setw(16) 5453748Sgblack@eecs.umich.edu << thread->readIntReg(y*8+x); 5463748Sgblack@eecs.umich.edu if (thread->readIntReg(y*8 + x) 5473748Sgblack@eecs.umich.edu != shared_data->intregs[y*8+x]) 5483584Ssaidi@eecs.umich.edu outs << " X "; 5493584Ssaidi@eecs.umich.edu else 5503584Ssaidi@eecs.umich.edu outs << " | "; 5513748Sgblack@eecs.umich.edu outs << "0x" << setw(16) << hex 5523748Sgblack@eecs.umich.edu << shared_data->intregs[y*8+x] 5533748Sgblack@eecs.umich.edu << endl;*/ 5543584Ssaidi@eecs.umich.edu } 5553584Ssaidi@eecs.umich.edu } 5563584Ssaidi@eecs.umich.edu fatal("Differences found between Legion and M5\n"); 5573584Ssaidi@eecs.umich.edu } 5583584Ssaidi@eecs.umich.edu 5593584Ssaidi@eecs.umich.edu compared = true; 5603584Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 5613506Ssaidi@eecs.umich.edu } 5623584Ssaidi@eecs.umich.edu } // while 5633584Ssaidi@eecs.umich.edu } // if not microop 5643506Ssaidi@eecs.umich.edu } 5653584Ssaidi@eecs.umich.edu#endif 5662SN/A} 5672SN/A 5682SN/A 5692SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS); 5701967SN/Astring Trace::InstRecord::trace_system; 5712SN/A 5722SN/A//////////////////////////////////////////////////////////////////////// 5732SN/A// 5742SN/A// Parameter space for per-cycle execution address tracing options. 5752SN/A// Derive from ParamContext so we can override checkParams() function. 5762SN/A// 5772SN/Aclass ExecutionTraceParamContext : public ParamContext 5782SN/A{ 5792SN/A public: 5802SN/A ExecutionTraceParamContext(const string &_iniSection) 5812SN/A : ParamContext(_iniSection) 5822SN/A { 5832SN/A } 5842SN/A 5852SN/A void checkParams(); // defined at bottom of file 5862SN/A}; 5872SN/A 5882SN/AExecutionTraceParamContext exeTraceParams("exetrace"); 5892SN/A 5902SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative", 5911413SN/A "capture speculative instructions", true); 5922SN/A 5932SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 5942SN/A "print cycle number", true); 5952SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 5962SN/A "print op class", true); 5972SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 5982SN/A "print thread number", true); 5992SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 6002SN/A "print effective address", true); 6012SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data", 6022SN/A "print result data", true); 6032SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 6042SN/A "print all integer regs", false); 6052SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 6062SN/A "print fetch sequence number", false); 6072SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 6082SN/A "print correct-path sequence number", false); 6092973Sgblack@eecs.umich.eduParam<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 6102973Sgblack@eecs.umich.edu "print which registers changed to what", false); 6112299SN/AParam<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 6122299SN/A "Use symbols for the PC if available", true); 6131904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 6141904SN/A "print trace in intel compatible format", false); 6153506Ssaidi@eecs.umich.eduParam<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep", 6163506Ssaidi@eecs.umich.edu "Compare sim state to legion state every cycle", 6173506Ssaidi@eecs.umich.edu false); 6181967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system", 6191967SN/A "print trace of which system (client or server)", 6201967SN/A "client"); 6211904SN/A 6222SN/A 6232SN/A// 6242SN/A// Helper function for ExecutionTraceParamContext::checkParams() just 6252SN/A// to get us into the InstRecord namespace 6262SN/A// 6272SN/Avoid 6282SN/ATrace::InstRecord::setParams() 6292SN/A{ 6302SN/A flags[TRACE_MISSPEC] = exe_trace_spec; 6312SN/A 6322SN/A flags[PRINT_CYCLE] = exe_trace_print_cycle; 6332SN/A flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 6342SN/A flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 6352SN/A flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 6362SN/A flags[PRINT_EFF_ADDR] = exe_trace_print_data; 6372SN/A flags[PRINT_INT_REGS] = exe_trace_print_iregs; 6382SN/A flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 6392SN/A flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 6402973Sgblack@eecs.umich.edu flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 6412299SN/A flags[PC_SYMBOL] = exe_trace_pc_symbol; 6421904SN/A flags[INTEL_FORMAT] = exe_trace_intel_format; 6433506Ssaidi@eecs.umich.edu flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep; 6441967SN/A trace_system = exe_trace_system; 6453506Ssaidi@eecs.umich.edu 6463506Ssaidi@eecs.umich.edu // If were going to be in lockstep with Legion 6473506Ssaidi@eecs.umich.edu // Setup shared memory, and get otherwise ready 6483506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) { 6493603Ssaidi@eecs.umich.edu int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777); 6503506Ssaidi@eecs.umich.edu if (shmfd < 0) 6513506Ssaidi@eecs.umich.edu fatal("Couldn't get shared memory fd. Is Legion running?"); 6523506Ssaidi@eecs.umich.edu 6533506Ssaidi@eecs.umich.edu shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 6543506Ssaidi@eecs.umich.edu if (shared_data == (SharedData*)-1) 6553506Ssaidi@eecs.umich.edu fatal("Couldn't allocate shared memory"); 6563506Ssaidi@eecs.umich.edu 6573506Ssaidi@eecs.umich.edu if (shared_data->flags != OWN_M5) 6583506Ssaidi@eecs.umich.edu fatal("Shared memory has invalid owner"); 6593506Ssaidi@eecs.umich.edu 6603506Ssaidi@eecs.umich.edu if (shared_data->version != VERSION) 6613506Ssaidi@eecs.umich.edu fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 6623506Ssaidi@eecs.umich.edu shared_data->version); 6633506Ssaidi@eecs.umich.edu 6643603Ssaidi@eecs.umich.edu // step legion forward one cycle so we can get register values 6653603Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 6663506Ssaidi@eecs.umich.edu } 6672SN/A} 6682SN/A 6692SN/Avoid 6702SN/AExecutionTraceParamContext::checkParams() 6712SN/A{ 6722SN/A Trace::InstRecord::setParams(); 6732SN/A} 6742SN/A 675