exetrace.cc revision 3506
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Lisa Hsu 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312665Ssaidi@eecs.umich.edu * Steve Raasch 322SN/A */ 332SN/A 342SN/A#include <fstream> 352SN/A#include <iomanip> 363506Ssaidi@eecs.umich.edu#include <sys/ipc.h> 373506Ssaidi@eecs.umich.edu#include <sys/shm.h> 382SN/A 392973Sgblack@eecs.umich.edu#include "arch/regfile.hh" 4056SN/A#include "base/loader/symtab.hh" 411717SN/A#include "cpu/base.hh" 422518SN/A#include "cpu/exetrace.hh" 4356SN/A#include "cpu/static_inst.hh" 442518SN/A#include "sim/param.hh" 452518SN/A#include "sim/system.hh" 462SN/A 473065Sgblack@eecs.umich.edu//XXX This is temporary 483065Sgblack@eecs.umich.edu#include "arch/isa_specific.hh" 493506Ssaidi@eecs.umich.edu#include "cpu/m5legion_interface.h" 503065Sgblack@eecs.umich.edu 512SN/Ausing namespace std; 522973Sgblack@eecs.umich.eduusing namespace TheISA; 532SN/A 543506Ssaidi@eecs.umich.edunamespace Trace { 553506Ssaidi@eecs.umich.eduSharedData *shared_data = NULL; 563506Ssaidi@eecs.umich.edu} 573506Ssaidi@eecs.umich.edu 582SN/A//////////////////////////////////////////////////////////////////////// 592SN/A// 602SN/A// Methods for the InstRecord object 612SN/A// 622SN/A 632SN/A 642SN/Avoid 652SN/ATrace::InstRecord::dump(ostream &outs) 662SN/A{ 672973Sgblack@eecs.umich.edu if (flags[PRINT_REG_DELTA]) 682973Sgblack@eecs.umich.edu { 693065Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA 703506Ssaidi@eecs.umich.edu#if 0 713380Sgblack@eecs.umich.edu //Don't print what happens for each micro-op, just print out 723380Sgblack@eecs.umich.edu //once at the last op, and for regular instructions. 733380Sgblack@eecs.umich.edu if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 743380Sgblack@eecs.umich.edu { 753380Sgblack@eecs.umich.edu static uint64_t regs[32] = { 763380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 773380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 783380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0, 793380Sgblack@eecs.umich.edu 0, 0, 0, 0, 0, 0, 0, 0}; 803380Sgblack@eecs.umich.edu static uint64_t ccr = 0; 813380Sgblack@eecs.umich.edu static uint64_t y = 0; 823380Sgblack@eecs.umich.edu static uint64_t floats[32]; 833380Sgblack@eecs.umich.edu uint64_t newVal; 843380Sgblack@eecs.umich.edu static const char * prefixes[4] = {"G", "O", "L", "I"}; 853065Sgblack@eecs.umich.edu 863380Sgblack@eecs.umich.edu char buf[256]; 873380Sgblack@eecs.umich.edu sprintf(buf, "PC = 0x%016llx", thread->readNextPC()); 883059Sgblack@eecs.umich.edu outs << buf; 893380Sgblack@eecs.umich.edu sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC()); 903059Sgblack@eecs.umich.edu outs << buf; 913380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); 923380Sgblack@eecs.umich.edu if(newVal != ccr) 933059Sgblack@eecs.umich.edu { 943380Sgblack@eecs.umich.edu sprintf(buf, " CCR = 0x%016llx", newVal); 953380Sgblack@eecs.umich.edu outs << buf; 963380Sgblack@eecs.umich.edu ccr = newVal; 973380Sgblack@eecs.umich.edu } 983380Sgblack@eecs.umich.edu newVal = thread->readMiscReg(SparcISA::MISCREG_Y); 993380Sgblack@eecs.umich.edu if(newVal != y) 1003380Sgblack@eecs.umich.edu { 1013380Sgblack@eecs.umich.edu sprintf(buf, " Y = 0x%016llx", newVal); 1023380Sgblack@eecs.umich.edu outs << buf; 1033380Sgblack@eecs.umich.edu y = newVal; 1043380Sgblack@eecs.umich.edu } 1053380Sgblack@eecs.umich.edu for(int y = 0; y < 4; y++) 1063380Sgblack@eecs.umich.edu { 1073380Sgblack@eecs.umich.edu for(int x = 0; x < 8; x++) 1083059Sgblack@eecs.umich.edu { 1093380Sgblack@eecs.umich.edu int index = x + 8 * y; 1103380Sgblack@eecs.umich.edu newVal = thread->readIntReg(index); 1113380Sgblack@eecs.umich.edu if(regs[index] != newVal) 1123380Sgblack@eecs.umich.edu { 1133380Sgblack@eecs.umich.edu sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal); 1143380Sgblack@eecs.umich.edu outs << buf; 1153380Sgblack@eecs.umich.edu regs[index] = newVal; 1163380Sgblack@eecs.umich.edu } 1173059Sgblack@eecs.umich.edu } 1183059Sgblack@eecs.umich.edu } 1193380Sgblack@eecs.umich.edu for(int y = 0; y < 32; y++) 1203380Sgblack@eecs.umich.edu { 1213380Sgblack@eecs.umich.edu newVal = thread->readFloatRegBits(2 * y, 64); 1223380Sgblack@eecs.umich.edu if(floats[y] != newVal) 1233380Sgblack@eecs.umich.edu { 1243380Sgblack@eecs.umich.edu sprintf(buf, " F%d = 0x%016llx", 2 * y, newVal); 1253380Sgblack@eecs.umich.edu outs << buf; 1263380Sgblack@eecs.umich.edu floats[y] = newVal; 1273380Sgblack@eecs.umich.edu } 1283380Sgblack@eecs.umich.edu } 1293380Sgblack@eecs.umich.edu outs << endl; 1303059Sgblack@eecs.umich.edu } 1313065Sgblack@eecs.umich.edu#endif 1323506Ssaidi@eecs.umich.edu#endif 1332973Sgblack@eecs.umich.edu } 1342973Sgblack@eecs.umich.edu else if (flags[INTEL_FORMAT]) { 1351968SN/A#if FULL_SYSTEM 1363064Sgblack@eecs.umich.edu bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system); 1371968SN/A#else 1381968SN/A bool is_trace_system = true; 1391968SN/A#endif 1401968SN/A if (is_trace_system) { 1411967SN/A ccprintf(outs, "%7d ) ", cycle); 1421967SN/A outs << "0x" << hex << PC << ":\t"; 1431967SN/A if (staticInst->isLoad()) { 1441967SN/A outs << "<RD 0x" << hex << addr; 1451967SN/A outs << ">"; 1461967SN/A } else if (staticInst->isStore()) { 1471967SN/A outs << "<WR 0x" << hex << addr; 1481967SN/A outs << ">"; 1491967SN/A } 1501967SN/A outs << endl; 1511904SN/A } 1521904SN/A } else { 1531904SN/A if (flags[PRINT_CYCLE]) 1541904SN/A ccprintf(outs, "%7d: ", cycle); 155452SN/A 1563064Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 1572SN/A 1581904SN/A if (flags[TRACE_MISSPEC]) 1591904SN/A outs << (misspeculating ? "-" : "+") << " "; 1602SN/A 1611904SN/A if (flags[PRINT_THREAD_NUM]) 1623064Sgblack@eecs.umich.edu outs << "T" << thread->getThreadNum() << " : "; 1632SN/A 1642SN/A 1651904SN/A std::string sym_str; 1661904SN/A Addr sym_addr; 1671904SN/A if (debugSymbolTable 1682299SN/A && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) 1692299SN/A && flags[PC_SYMBOL]) { 1701904SN/A if (PC != sym_addr) 1711904SN/A sym_str += csprintf("+%d", PC - sym_addr); 1721904SN/A outs << "@" << sym_str << " : "; 1731904SN/A } 1741904SN/A else { 1751904SN/A outs << "0x" << hex << PC << " : "; 1761904SN/A } 177452SN/A 1781904SN/A // 1791904SN/A // Print decoded instruction 1801904SN/A // 1812SN/A 1822SN/A#if defined(__GNUC__) && (__GNUC__ < 3) 1831904SN/A // There's a bug in gcc 2.x library that prevents setw() 1841904SN/A // from working properly on strings 1851904SN/A string mc(staticInst->disassemble(PC, debugSymbolTable)); 1861904SN/A while (mc.length() < 26) 1871904SN/A mc += " "; 1881904SN/A outs << mc; 1892SN/A#else 1901904SN/A outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 1912SN/A#endif 1922SN/A 1931904SN/A outs << " : "; 1942SN/A 1951904SN/A if (flags[PRINT_OP_CLASS]) { 1961904SN/A outs << opClassStrings[staticInst->opClass()] << " : "; 1971904SN/A } 1981904SN/A 1991904SN/A if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { 2001904SN/A outs << " D="; 2011904SN/A#if 0 2021904SN/A if (data_status == DataDouble) 2031904SN/A ccprintf(outs, "%f", data.as_double); 2041904SN/A else 2051904SN/A ccprintf(outs, "%#018x", data.as_int); 2061904SN/A#else 2071904SN/A ccprintf(outs, "%#018x", data.as_int); 2081904SN/A#endif 2091904SN/A } 2101904SN/A 2111904SN/A if (flags[PRINT_EFF_ADDR] && addr_valid) 2121904SN/A outs << " A=0x" << hex << addr; 2131904SN/A 2141904SN/A if (flags[PRINT_INT_REGS] && regs_valid) { 2152525SN/A for (int i = 0; i < TheISA::NumIntRegs;) 2161904SN/A for (int j = i + 1; i <= j; i++) 2172525SN/A ccprintf(outs, "r%02d = %#018x%s", i, 2182525SN/A iregs->regs.readReg(i), 2192525SN/A ((i == j) ? "\n" : " ")); 2201904SN/A outs << "\n"; 2211904SN/A } 2221904SN/A 2231904SN/A if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) 2241904SN/A outs << " FetchSeq=" << dec << fetch_seq; 2251904SN/A 2261904SN/A if (flags[PRINT_CP_SEQ] && cp_seq_valid) 2271904SN/A outs << " CPSeq=" << dec << cp_seq; 2281967SN/A 2291967SN/A // 2301967SN/A // End of line... 2311967SN/A // 2321967SN/A outs << endl; 2332SN/A } 2343506Ssaidi@eecs.umich.edu // Compare 2353506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) 2363506Ssaidi@eecs.umich.edu { 2373506Ssaidi@eecs.umich.edu bool compared = false; 2383506Ssaidi@eecs.umich.edu bool diffPC = false; 2393506Ssaidi@eecs.umich.edu bool diffInst = false; 2403506Ssaidi@eecs.umich.edu bool diffRegs = false; 2413506Ssaidi@eecs.umich.edu 2423506Ssaidi@eecs.umich.edu while (!compared) { 2433506Ssaidi@eecs.umich.edu if (shared_data->flags == OWN_M5) { 2443506Ssaidi@eecs.umich.edu if (shared_data->pc != PC) 2453506Ssaidi@eecs.umich.edu diffPC = true; 2463506Ssaidi@eecs.umich.edu if (shared_data->instruction != staticInst->machInst) 2473506Ssaidi@eecs.umich.edu diffInst = true; 2483506Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumIntRegs; i++) { 2493506Ssaidi@eecs.umich.edu if (thread->readIntReg(i) != shared_data->intregs[i]) 2503506Ssaidi@eecs.umich.edu diffRegs = true; 2513506Ssaidi@eecs.umich.edu } 2523506Ssaidi@eecs.umich.edu 2533506Ssaidi@eecs.umich.edu if (diffPC || diffInst || diffRegs ) { 2543506Ssaidi@eecs.umich.edu outs << "Differences found between M5 and Legion:"; 2553506Ssaidi@eecs.umich.edu if (diffPC) 2563506Ssaidi@eecs.umich.edu outs << " PC"; 2573506Ssaidi@eecs.umich.edu if (diffInst) 2583506Ssaidi@eecs.umich.edu outs << " Instruction"; 2593506Ssaidi@eecs.umich.edu if (diffRegs) 2603506Ssaidi@eecs.umich.edu outs << " IntRegs"; 2613506Ssaidi@eecs.umich.edu outs << endl; 2623506Ssaidi@eecs.umich.edu 2633506Ssaidi@eecs.umich.edu outs << "M5 PC: " << setw(20) << "0x" << hex << PC; 2643506Ssaidi@eecs.umich.edu outs << "Legion PC: " << setw(20) << "0x" << hex << 2653506Ssaidi@eecs.umich.edu shared_data->pc << endl; 2663506Ssaidi@eecs.umich.edu 2673506Ssaidi@eecs.umich.edu 2683506Ssaidi@eecs.umich.edu 2693506Ssaidi@eecs.umich.edu outs << "M5 Instruction: " << staticInst->machInst << "(" 2703506Ssaidi@eecs.umich.edu << staticInst->disassemble(PC, debugSymbolTable) 2713506Ssaidi@eecs.umich.edu << ")" << "Legion Instruction: " << 2723506Ssaidi@eecs.umich.edu shared_data->instruction << "(" 2733506Ssaidi@eecs.umich.edu /*<< legionInst->disassemble(shared_data->pc, 2743506Ssaidi@eecs.umich.edu debugSymbolTable)*/ 2753506Ssaidi@eecs.umich.edu << ")" << endl; 2763506Ssaidi@eecs.umich.edu 2773506Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumIntRegs; i++) { 2783506Ssaidi@eecs.umich.edu outs << setw(16) << "0x" << hex << thread->readIntReg(i) 2793506Ssaidi@eecs.umich.edu << setw(16) << "0x" << hex << shared_data->intregs[i]; 2803506Ssaidi@eecs.umich.edu 2813506Ssaidi@eecs.umich.edu if (thread->readIntReg(i) != shared_data->intregs[i]) 2823506Ssaidi@eecs.umich.edu outs << "<--- Different"; 2833506Ssaidi@eecs.umich.edu outs << endl; 2843506Ssaidi@eecs.umich.edu } 2853506Ssaidi@eecs.umich.edu } 2863506Ssaidi@eecs.umich.edu 2873506Ssaidi@eecs.umich.edu compared = true; 2883506Ssaidi@eecs.umich.edu shared_data->flags = OWN_LEGION; 2893506Ssaidi@eecs.umich.edu } 2903506Ssaidi@eecs.umich.edu } 2913506Ssaidi@eecs.umich.edu 2923506Ssaidi@eecs.umich.edu } 2932SN/A} 2942SN/A 2952SN/A 2962SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS); 2971967SN/Astring Trace::InstRecord::trace_system; 2982SN/A 2992SN/A//////////////////////////////////////////////////////////////////////// 3002SN/A// 3012SN/A// Parameter space for per-cycle execution address tracing options. 3022SN/A// Derive from ParamContext so we can override checkParams() function. 3032SN/A// 3042SN/Aclass ExecutionTraceParamContext : public ParamContext 3052SN/A{ 3062SN/A public: 3072SN/A ExecutionTraceParamContext(const string &_iniSection) 3082SN/A : ParamContext(_iniSection) 3092SN/A { 3102SN/A } 3112SN/A 3122SN/A void checkParams(); // defined at bottom of file 3132SN/A}; 3142SN/A 3152SN/AExecutionTraceParamContext exeTraceParams("exetrace"); 3162SN/A 3172SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative", 3181413SN/A "capture speculative instructions", true); 3192SN/A 3202SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 3212SN/A "print cycle number", true); 3222SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 3232SN/A "print op class", true); 3242SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 3252SN/A "print thread number", true); 3262SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 3272SN/A "print effective address", true); 3282SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data", 3292SN/A "print result data", true); 3302SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 3312SN/A "print all integer regs", false); 3322SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 3332SN/A "print fetch sequence number", false); 3342SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 3352SN/A "print correct-path sequence number", false); 3362973Sgblack@eecs.umich.eduParam<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 3372973Sgblack@eecs.umich.edu "print which registers changed to what", false); 3382299SN/AParam<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 3392299SN/A "Use symbols for the PC if available", true); 3401904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 3411904SN/A "print trace in intel compatible format", false); 3423506Ssaidi@eecs.umich.eduParam<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep", 3433506Ssaidi@eecs.umich.edu "Compare sim state to legion state every cycle", 3443506Ssaidi@eecs.umich.edu false); 3451967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system", 3461967SN/A "print trace of which system (client or server)", 3471967SN/A "client"); 3481904SN/A 3492SN/A 3502SN/A// 3512SN/A// Helper function for ExecutionTraceParamContext::checkParams() just 3522SN/A// to get us into the InstRecord namespace 3532SN/A// 3542SN/Avoid 3552SN/ATrace::InstRecord::setParams() 3562SN/A{ 3572SN/A flags[TRACE_MISSPEC] = exe_trace_spec; 3582SN/A 3592SN/A flags[PRINT_CYCLE] = exe_trace_print_cycle; 3602SN/A flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 3612SN/A flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 3622SN/A flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 3632SN/A flags[PRINT_EFF_ADDR] = exe_trace_print_data; 3642SN/A flags[PRINT_INT_REGS] = exe_trace_print_iregs; 3652SN/A flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 3662SN/A flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 3672973Sgblack@eecs.umich.edu flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 3682299SN/A flags[PC_SYMBOL] = exe_trace_pc_symbol; 3691904SN/A flags[INTEL_FORMAT] = exe_trace_intel_format; 3703506Ssaidi@eecs.umich.edu flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep; 3711967SN/A trace_system = exe_trace_system; 3723506Ssaidi@eecs.umich.edu 3733506Ssaidi@eecs.umich.edu // If were going to be in lockstep with Legion 3743506Ssaidi@eecs.umich.edu // Setup shared memory, and get otherwise ready 3753506Ssaidi@eecs.umich.edu if (flags[LEGION_LOCKSTEP]) { 3763506Ssaidi@eecs.umich.edu int shmfd = shmget(getuid(), sizeof(SharedData), 0777); 3773506Ssaidi@eecs.umich.edu if (shmfd < 0) 3783506Ssaidi@eecs.umich.edu fatal("Couldn't get shared memory fd. Is Legion running?"); 3793506Ssaidi@eecs.umich.edu 3803506Ssaidi@eecs.umich.edu shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 3813506Ssaidi@eecs.umich.edu if (shared_data == (SharedData*)-1) 3823506Ssaidi@eecs.umich.edu fatal("Couldn't allocate shared memory"); 3833506Ssaidi@eecs.umich.edu 3843506Ssaidi@eecs.umich.edu if (shared_data->flags != OWN_M5) 3853506Ssaidi@eecs.umich.edu fatal("Shared memory has invalid owner"); 3863506Ssaidi@eecs.umich.edu 3873506Ssaidi@eecs.umich.edu if (shared_data->version != VERSION) 3883506Ssaidi@eecs.umich.edu fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 3893506Ssaidi@eecs.umich.edu shared_data->version); 3903506Ssaidi@eecs.umich.edu 3913506Ssaidi@eecs.umich.edu } 3922SN/A} 3932SN/A 3942SN/Avoid 3952SN/AExecutionTraceParamContext::checkParams() 3962SN/A{ 3972SN/A Trace::InstRecord::setParams(); 3982SN/A} 3992SN/A 400