exetrace.cc revision 3065
12SN/A/*
21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
292665Ssaidi@eecs.umich.edu *          Lisa Hsu
302665Ssaidi@eecs.umich.edu *          Nathan Binkert
312665Ssaidi@eecs.umich.edu *          Steve Raasch
322SN/A */
332SN/A
342SN/A#include <fstream>
352SN/A#include <iomanip>
362SN/A
372973Sgblack@eecs.umich.edu#include "arch/regfile.hh"
3856SN/A#include "base/loader/symtab.hh"
391717SN/A#include "cpu/base.hh"
402518SN/A#include "cpu/exetrace.hh"
4156SN/A#include "cpu/static_inst.hh"
422518SN/A#include "sim/param.hh"
432518SN/A#include "sim/system.hh"
442SN/A
453065Sgblack@eecs.umich.edu//XXX This is temporary
463065Sgblack@eecs.umich.edu#include "arch/isa_specific.hh"
473065Sgblack@eecs.umich.edu
482SN/Ausing namespace std;
492973Sgblack@eecs.umich.eduusing namespace TheISA;
502SN/A
512SN/A////////////////////////////////////////////////////////////////////////
522SN/A//
532SN/A//  Methods for the InstRecord object
542SN/A//
552SN/A
562SN/A
572SN/Avoid
582SN/ATrace::InstRecord::dump(ostream &outs)
592SN/A{
602973Sgblack@eecs.umich.edu    if (flags[PRINT_REG_DELTA])
612973Sgblack@eecs.umich.edu    {
623065Sgblack@eecs.umich.edu#if THE_ISA == SPARC_ISA
633065Sgblack@eecs.umich.edu        static uint64_t regs[32] = {
643065Sgblack@eecs.umich.edu            0, 0, 0, 0, 0, 0, 0, 0,
653065Sgblack@eecs.umich.edu            0, 0, 0, 0, 0, 0, 0, 0,
663065Sgblack@eecs.umich.edu            0, 0, 0, 0, 0, 0, 0, 0,
673065Sgblack@eecs.umich.edu            0, 0, 0, 0, 0, 0, 0, 0};
683065Sgblack@eecs.umich.edu        static uint64_t ccr = 0;
693065Sgblack@eecs.umich.edu        static uint64_t y = 0;
703065Sgblack@eecs.umich.edu        static uint64_t floats[32];
713065Sgblack@eecs.umich.edu        uint64_t newVal;
723065Sgblack@eecs.umich.edu        static const char * prefixes[4] = {"G", "O", "L", "I"};
733065Sgblack@eecs.umich.edu
743059Sgblack@eecs.umich.edu        char buf[256];
753064Sgblack@eecs.umich.edu        sprintf(buf, "PC = 0x%016llx", thread->readNextPC());
763059Sgblack@eecs.umich.edu        outs << buf;
773064Sgblack@eecs.umich.edu        sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC());
783059Sgblack@eecs.umich.edu        outs << buf;
793064Sgblack@eecs.umich.edu        newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
803059Sgblack@eecs.umich.edu        if(newVal != ccr)
813059Sgblack@eecs.umich.edu        {
823059Sgblack@eecs.umich.edu            sprintf(buf, " CCR = 0x%016llx", newVal);
833059Sgblack@eecs.umich.edu            outs << buf;
843059Sgblack@eecs.umich.edu            ccr = newVal;
853059Sgblack@eecs.umich.edu        }
863064Sgblack@eecs.umich.edu        newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
873059Sgblack@eecs.umich.edu        if(newVal != y)
883059Sgblack@eecs.umich.edu        {
893059Sgblack@eecs.umich.edu            sprintf(buf, " Y = 0x%016llx", newVal);
903059Sgblack@eecs.umich.edu            outs << buf;
913059Sgblack@eecs.umich.edu            y = newVal;
923059Sgblack@eecs.umich.edu        }
933059Sgblack@eecs.umich.edu        for(int y = 0; y < 4; y++)
943059Sgblack@eecs.umich.edu        {
953059Sgblack@eecs.umich.edu            for(int x = 0; x < 8; x++)
963059Sgblack@eecs.umich.edu            {
973059Sgblack@eecs.umich.edu                int index = x + 8 * y;
983064Sgblack@eecs.umich.edu                newVal = thread->readIntReg(index);
993059Sgblack@eecs.umich.edu                if(regs[index] != newVal)
1003059Sgblack@eecs.umich.edu                {
1013059Sgblack@eecs.umich.edu                    sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal);
1023059Sgblack@eecs.umich.edu                    outs << buf;
1033059Sgblack@eecs.umich.edu                    regs[index] = newVal;
1043059Sgblack@eecs.umich.edu                }
1053059Sgblack@eecs.umich.edu            }
1063059Sgblack@eecs.umich.edu        }
1073059Sgblack@eecs.umich.edu        for(int y = 0; y < 32; y++)
1083059Sgblack@eecs.umich.edu        {
1093064Sgblack@eecs.umich.edu            newVal = thread->readFloatRegBits(2 * y, 64);
1103059Sgblack@eecs.umich.edu            if(floats[y] != newVal)
1113059Sgblack@eecs.umich.edu            {
1123059Sgblack@eecs.umich.edu                sprintf(buf, " F%d = 0x%016llx", y, newVal);
1133059Sgblack@eecs.umich.edu                outs << buf;
1143059Sgblack@eecs.umich.edu                floats[y] = newVal;
1153059Sgblack@eecs.umich.edu            }
1163059Sgblack@eecs.umich.edu        }
1173059Sgblack@eecs.umich.edu        outs << endl;
1183065Sgblack@eecs.umich.edu#endif
1192973Sgblack@eecs.umich.edu    }
1202973Sgblack@eecs.umich.edu    else if (flags[INTEL_FORMAT]) {
1211968SN/A#if FULL_SYSTEM
1223064Sgblack@eecs.umich.edu        bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system);
1231968SN/A#else
1241968SN/A        bool is_trace_system = true;
1251968SN/A#endif
1261968SN/A        if (is_trace_system) {
1271967SN/A            ccprintf(outs, "%7d ) ", cycle);
1281967SN/A            outs << "0x" << hex << PC << ":\t";
1291967SN/A            if (staticInst->isLoad()) {
1301967SN/A                outs << "<RD 0x" << hex << addr;
1311967SN/A                outs << ">";
1321967SN/A            } else if (staticInst->isStore()) {
1331967SN/A                outs << "<WR 0x" << hex << addr;
1341967SN/A                outs << ">";
1351967SN/A            }
1361967SN/A            outs << endl;
1371904SN/A        }
1381904SN/A    } else {
1391904SN/A        if (flags[PRINT_CYCLE])
1401904SN/A            ccprintf(outs, "%7d: ", cycle);
141452SN/A
1423064Sgblack@eecs.umich.edu        outs << thread->getCpuPtr()->name() << " ";
1432SN/A
1441904SN/A        if (flags[TRACE_MISSPEC])
1451904SN/A            outs << (misspeculating ? "-" : "+") << " ";
1462SN/A
1471904SN/A        if (flags[PRINT_THREAD_NUM])
1483064Sgblack@eecs.umich.edu            outs << "T" << thread->getThreadNum() << " : ";
1492SN/A
1502SN/A
1511904SN/A        std::string sym_str;
1521904SN/A        Addr sym_addr;
1531904SN/A        if (debugSymbolTable
1542299SN/A            && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)
1552299SN/A            && flags[PC_SYMBOL]) {
1561904SN/A            if (PC != sym_addr)
1571904SN/A                sym_str += csprintf("+%d", PC - sym_addr);
1581904SN/A            outs << "@" << sym_str << " : ";
1591904SN/A        }
1601904SN/A        else {
1611904SN/A            outs << "0x" << hex << PC << " : ";
1621904SN/A        }
163452SN/A
1641904SN/A        //
1651904SN/A        //  Print decoded instruction
1661904SN/A        //
1672SN/A
1682SN/A#if defined(__GNUC__) && (__GNUC__ < 3)
1691904SN/A        // There's a bug in gcc 2.x library that prevents setw()
1701904SN/A        // from working properly on strings
1711904SN/A        string mc(staticInst->disassemble(PC, debugSymbolTable));
1721904SN/A        while (mc.length() < 26)
1731904SN/A            mc += " ";
1741904SN/A        outs << mc;
1752SN/A#else
1761904SN/A        outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable);
1772SN/A#endif
1782SN/A
1791904SN/A        outs << " : ";
1802SN/A
1811904SN/A        if (flags[PRINT_OP_CLASS]) {
1821904SN/A            outs << opClassStrings[staticInst->opClass()] << " : ";
1831904SN/A        }
1841904SN/A
1851904SN/A        if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) {
1861904SN/A            outs << " D=";
1871904SN/A#if 0
1881904SN/A            if (data_status == DataDouble)
1891904SN/A                ccprintf(outs, "%f", data.as_double);
1901904SN/A            else
1911904SN/A                ccprintf(outs, "%#018x", data.as_int);
1921904SN/A#else
1931904SN/A            ccprintf(outs, "%#018x", data.as_int);
1941904SN/A#endif
1951904SN/A        }
1961904SN/A
1971904SN/A        if (flags[PRINT_EFF_ADDR] && addr_valid)
1981904SN/A            outs << " A=0x" << hex << addr;
1991904SN/A
2001904SN/A        if (flags[PRINT_INT_REGS] && regs_valid) {
2012525SN/A            for (int i = 0; i < TheISA::NumIntRegs;)
2021904SN/A                for (int j = i + 1; i <= j; i++)
2032525SN/A                    ccprintf(outs, "r%02d = %#018x%s", i,
2042525SN/A                            iregs->regs.readReg(i),
2052525SN/A                            ((i == j) ? "\n" : "    "));
2061904SN/A            outs << "\n";
2071904SN/A        }
2081904SN/A
2091904SN/A        if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid)
2101904SN/A            outs << "  FetchSeq=" << dec << fetch_seq;
2111904SN/A
2121904SN/A        if (flags[PRINT_CP_SEQ] && cp_seq_valid)
2131904SN/A            outs << "  CPSeq=" << dec << cp_seq;
2141967SN/A
2151967SN/A        //
2161967SN/A        //  End of line...
2171967SN/A        //
2181967SN/A        outs << endl;
2192SN/A    }
2202SN/A}
2212SN/A
2222SN/A
2232SN/Avector<bool> Trace::InstRecord::flags(NUM_BITS);
2241967SN/Astring Trace::InstRecord::trace_system;
2252SN/A
2262SN/A////////////////////////////////////////////////////////////////////////
2272SN/A//
2282SN/A// Parameter space for per-cycle execution address tracing options.
2292SN/A// Derive from ParamContext so we can override checkParams() function.
2302SN/A//
2312SN/Aclass ExecutionTraceParamContext : public ParamContext
2322SN/A{
2332SN/A  public:
2342SN/A    ExecutionTraceParamContext(const string &_iniSection)
2352SN/A        : ParamContext(_iniSection)
2362SN/A        {
2372SN/A        }
2382SN/A
2392SN/A    void checkParams();	// defined at bottom of file
2402SN/A};
2412SN/A
2422SN/AExecutionTraceParamContext exeTraceParams("exetrace");
2432SN/A
2442SN/AParam<bool> exe_trace_spec(&exeTraceParams, "speculative",
2451413SN/A                           "capture speculative instructions", true);
2462SN/A
2472SN/AParam<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle",
2482SN/A                                  "print cycle number", true);
2492SN/AParam<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass",
2502SN/A                                  "print op class", true);
2512SN/AParam<bool> exe_trace_print_thread(&exeTraceParams, "print_thread",
2522SN/A                                  "print thread number", true);
2532SN/AParam<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr",
2542SN/A                                  "print effective address", true);
2552SN/AParam<bool> exe_trace_print_data(&exeTraceParams, "print_data",
2562SN/A                                  "print result data", true);
2572SN/AParam<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs",
2582SN/A                                  "print all integer regs", false);
2592SN/AParam<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
2602SN/A                                  "print fetch sequence number", false);
2612SN/AParam<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
2622SN/A                                  "print correct-path sequence number", false);
2632973Sgblack@eecs.umich.eduParam<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta",
2642973Sgblack@eecs.umich.edu                                  "print which registers changed to what", false);
2652299SN/AParam<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
2662299SN/A                                  "Use symbols for the PC if available", true);
2671904SN/AParam<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
2681904SN/A                                   "print trace in intel compatible format", false);
2691967SN/AParam<string> exe_trace_system(&exeTraceParams, "trace_system",
2701967SN/A                                   "print trace of which system (client or server)",
2711967SN/A                                   "client");
2721904SN/A
2732SN/A
2742SN/A//
2752SN/A// Helper function for ExecutionTraceParamContext::checkParams() just
2762SN/A// to get us into the InstRecord namespace
2772SN/A//
2782SN/Avoid
2792SN/ATrace::InstRecord::setParams()
2802SN/A{
2812SN/A    flags[TRACE_MISSPEC]     = exe_trace_spec;
2822SN/A
2832SN/A    flags[PRINT_CYCLE]       = exe_trace_print_cycle;
2842SN/A    flags[PRINT_OP_CLASS]    = exe_trace_print_opclass;
2852SN/A    flags[PRINT_THREAD_NUM]  = exe_trace_print_thread;
2862SN/A    flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr;
2872SN/A    flags[PRINT_EFF_ADDR]    = exe_trace_print_data;
2882SN/A    flags[PRINT_INT_REGS]    = exe_trace_print_iregs;
2892SN/A    flags[PRINT_FETCH_SEQ]   = exe_trace_print_fetchseq;
2902SN/A    flags[PRINT_CP_SEQ]      = exe_trace_print_cp_seq;
2912973Sgblack@eecs.umich.edu    flags[PRINT_REG_DELTA]   = exe_trace_print_reg_delta;
2922299SN/A    flags[PC_SYMBOL]         = exe_trace_pc_symbol;
2931904SN/A    flags[INTEL_FORMAT]      = exe_trace_intel_format;
2941967SN/A    trace_system	     = exe_trace_system;
2952SN/A}
2962SN/A
2972SN/Avoid
2982SN/AExecutionTraceParamContext::checkParams()
2992SN/A{
3002SN/A    Trace::InstRecord::setParams();
3012SN/A}
3022SN/A
303